CN108712166B - Self-adaptive level conversion circuit - Google Patents
Self-adaptive level conversion circuit Download PDFInfo
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- CN108712166B CN108712166B CN201810161906.XA CN201810161906A CN108712166B CN 108712166 B CN108712166 B CN 108712166B CN 201810161906 A CN201810161906 A CN 201810161906A CN 108712166 B CN108712166 B CN 108712166B
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- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H03K19/017581—Coupling arrangements; Interface arrangements programmable
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Abstract
A self-adaptive level conversion circuit only starts a wide-range level conversion unit when the output voltage of a high-voltage power supply is not lower than a set threshold value, and then starts an acceleration level conversion unit when the output voltage of the high-voltage power supply is lower than the set threshold value, wherein the wide-range level conversion unit and the acceleration level conversion unit respectively control an output driving unit to output logic voltage corresponding to the logic of input data A. The requirement of various power supply voltages on the level conversion circuit is met by combining the wide-range level conversion unit with the acceleration level conversion unit, and the acceleration level conversion unit can be dynamically controlled by using the power supply voltage comparator, so that the self-adaptive level conversion capability under different power supply voltages is realized. Compared with the traditional level conversion circuit, the invention can provide a larger power supply voltage conversion range and can provide higher conversion speed under different power supply voltage environments.
Description
Technical Field
The invention relates to a self-adaptive level conversion circuit, in particular to a level conversion circuit which is optimally designed according to the application requirements of a programmable logic device and can adapt to various power supply voltages, belonging to the field of integrated circuits.
Background
The programmable logic device has the advantages of high flexibility, low cost, short period and the like, can greatly shorten the development period of products and maximally reduce risks, and becomes a core component in the integrated circuit industry. The programmable logic device comprises two power supplies, wherein one power supply is a kernel working power supply, the kernel power supply works under lower voltage for the performance and power consumption of the whole circuit, the other power supply is an input/output interface power supply, the programmable logic device has the communication function with other devices, and the input/output interface power supply works under higher voltage for ensuring the capability of driving other devices. The level shift circuit is a circuit which works at the boundary between the core power supply and the input/output interface and can shift the logic corresponding to the core power supply to the range of the power supply voltage of the input/output interface. In order to be compatible with a plurality of input and output protocols, an input/output interface of a programmable logic device needs to operate under different interface power supply voltages, so that a special level conversion circuit needs to be designed for the input/output interface to meet the requirements of various protocols and interface power supply voltages.
Conventional level shift circuits are designed for specific power supply voltages, and have limited capability for meeting the requirements of various power supply voltages in programmable logic devices. The proportion of a P-channel MOS tube and an N-channel MOS tube in a traditional level conversion circuit is designed according to a certain power supply voltage proportion. If the high-voltage power supply is designed to be much higher than the low-voltage power supply, the speed of the whole level conversion circuit cannot meet the requirement under the condition that the high-voltage power supply works at low voltage; if the high voltage power supply and the low voltage power supply are designed to be close to each other, a large chip area is consumed in order to meet the requirement that the high voltage power supply works at a high voltage. Therefore, a targeted level shifting circuit must be designed for the requirements of the programmable logic device for various supply voltages. The method not only ensures the level conversion speed under various power supply voltages, but also reduces the consumption of chip area and adapts to the application requirements of programmable logic devices.
Disclosure of Invention
The invention solves the problems that: the self-adaptive level conversion circuit overcomes the defects of the prior art, provides a self-adaptive level conversion circuit aiming at the requirement that a programmable logic device works under various power supply voltages, ensures the level conversion speed under various power supply voltages, reduces the consumption of the area of a chip, and meets the application requirement of the programmable logic device.
The technical scheme of the invention is as follows:
there is provided an adaptive level converting circuit including: a wide range level conversion unit, an acceleration level conversion unit, and an output driving unit;
when the output voltage of the high-voltage power supply is not lower than a set threshold, the wide-range level conversion unit controls a first driving module of the output driving unit to output a first logic voltage corresponding to the logic of the input data A; when the output voltage of the high-voltage power supply is lower than a set threshold value, the acceleration level conversion unit is started, and the wide-range level conversion unit and the acceleration level conversion unit respectively control the first driving module and the second driving module of the output driving unit to output a second logic voltage corresponding to the logic of the input data A in parallel.
Preferably, the power supply further comprises a power supply voltage comparator, which compares the output voltage of the high voltage power supply with a threshold, and controls the acceleration level conversion unit to be turned off when the output voltage is not lower than the threshold, and controls the acceleration level conversion unit to be turned on when the output voltage is lower than the threshold.
Preferably, the threshold is 2 times the output voltage of the low voltage power supply.
Preferably, the wide range level shifter unit outputs a logic signal X2 corresponding to the logic of the input data a, and a logic signal X1 which is the opposite of the logic of the data a;
when the output voltage of the high-voltage power supply is not lower than a set threshold, the first driving module outputs a first path of current corresponding to the first logic voltage based on a logic signal X2;
when the output voltage of the high-voltage power supply is lower than a set threshold value, the first driving module outputs a second current based on a logic signal X2; the acceleration level conversion unit generates a logic signal X3 corresponding to the logic of the input data a based on the logic signals X2 and X1; the second driving module outputs a third current based on the logic signal X3; the second path of current and the third path of current are output in a superposition mode, and the output voltage is a second logic voltage.
Preferably, the wide range level shift unit is configured as follows:
the source electrodes of the first P-channel MOS tube and the second P-channel MOS tube are connected with a high-voltage power supply; the drain electrode of the first P-channel MOS tube is connected with the source electrode of the third P-channel MOS tube; the drain electrode of the second P-channel MOS tube is connected with the source electrode of the fourth P-channel MOS tube; the drain electrode of the third P-channel MOS tube is connected with the drain electrode of the first N-channel MOS tube and serves as the output end of a logic signal X2; the drain electrode of the fourth P-channel MOS tube is connected with the drain electrode of the second N-channel MOS tube and serves as the output end of a logic signal X1; the source electrodes of the first N-channel MOS tube and the second N-channel MOS tube are connected to the ground;
The grid electrode of the first N-channel MOS tube and the grid electrode of the third P-channel MOS tube are connected with the data A; the grid electrode of the second N-channel MOS tube and the reverse signal AN of the fourth P-channel MOS tube, which is accessed to the data A, are connected;
the grid electrode of the first P-channel MOS tube is connected with the output end of a logic signal X1; the gate of the second P-channel MOS transistor is connected to the output terminal of the logic signal X2.
Preferably, the acceleration level conversion unit is configured as follows:
the source electrode of the fifth P-channel MOS tube, the source electrode of the sixth P-channel MOS tube, the source electrode of the seventh P-channel MOS tube and the source electrode of the eighth P-channel MOS tube are connected with a high-voltage power supply; one data end of the first transmission gate is connected with the drain electrode of the fifth P-channel MOS tube and the grid electrode of the seventh P-channel MOS tube; the other data end of the first transmission gate is connected with the drain electrode of the eighth P-channel MOS tube and is connected with a logic signal X1; one data end of the second transmission gate is connected with the drain electrode of the sixth P-channel MOS tube and the grid electrode of the fourth P-channel MOS tube and serves as an output end X3 of the acceleration level conversion unit; the other data end of the second transmission gate is connected with the drain electrode of the seventh P-channel MOS tube and is connected with a logic signal X2; the grid electrode of the fifth P-channel MOS tube, the grid electrode of the sixth P-channel MOS tube P6, the control end of the first transmission gate and the control end of the second transmission gate T2 are connected with the input end C of the acceleration level conversion unit and are connected with the starting control signal of the acceleration level conversion unit.
Preferably, the output driving unit is configured as follows:
the source electrode of the ninth P-channel MOS tube and the source electrode of the eleventh P-channel MOS tube are connected with a high-voltage power supply, and the drain electrode of the ninth P-channel MOS tube is connected with the source electrode of the tenth P-channel MOS tube; the drain electrode of the tenth P-channel MOS tube is connected with the drain electrode of the eleventh P-channel MOS tube P11 and serves as the output end Z of the output driving unit; the source electrode of the third N-channel MOS tube and the source electrode of the fourth N-channel MOS tube are connected to the ground; the drain electrode of the third N-channel MOS tube is connected with the drain electrode of the fourth N-channel MOS tube and is connected with the output end Z; the gate of the ninth P-channel MOS tube is connected with a logic signal X2; the grid electrode of the tenth P-channel MOS tube is connected with the grid electrode of the fourth N-channel MOS tube and is connected with the reverse signal AN of the data A; the gate of the eleventh P-channel MOS tube is connected with a logic signal X3; the gate of the third N-channel MOS transistor is connected to the logic signal X2.
Preferably, the device further comprises AN inverter, wherein the input end of the inverter is connected with the data A, the power end of the inverter is connected with the low-voltage power supply, and the output signal is AN inverted signal AN of the data A.
Preferably, a plurality of output driving units are used in parallel, and the number of output driving units connected in parallel is determined according to the magnitude of the output current.
Preferably, the width-to-length ratio of the seventh P-channel MOS transistor and the fourth P-channel MOS transistor is adjusted so that the switching speed of the logic voltage output by the first driving module is the same when the output voltage of the high-voltage power supply is higher than the threshold value and lower than the threshold value.
Compared with the prior art, the invention has the advantages that:
(1) the invention can provide the level conversion capability under various power supply voltages by using the wide-range level conversion unit and the acceleration level conversion unit, only starts the wide-range level conversion unit when the high-voltage power supply is higher, and simultaneously starts the wide-range level conversion unit and the acceleration level conversion unit to improve the level conversion speed when the high-voltage power supply is lower, so that the conversion speed can be kept consistent under the conditions of different power supply voltages.
(2) According to the invention, by using the wide-range level conversion unit and the acceleration level conversion unit, the wide-range level conversion unit is designed to have different proportions of the P-channel MOS tube and the N-channel MOS tube in the wide-range level conversion unit and the acceleration level conversion unit aiming at the condition that the high-voltage power supply works under a higher voltage and the acceleration level conversion unit aiming at the condition that the high-voltage power supply works under a lower voltage, so that the requirements of various power supply voltages on the area of a level conversion circuit device can be effectively reduced.
(3) The invention can adapt to the input/output interface of the programmable device under the requirements of various protocols by using the output driving unit; according to different protocols and requirements of driving capability, the programmable logic device can select the number of output interface parallel transistors, and the design requirements of the programmable logic device can be met only by adjusting the number of output driving units to match the number of output parallel transistors without changing the design of the wide-range level conversion unit and the acceleration level conversion unit.
(4) The invention can dynamically monitor the condition of the high-voltage power supply by using the power supply voltage comparator, thereby adaptively controlling the acceleration level conversion unit to be switched on and switched off.
(5) By using the power supply voltage comparator, a plurality of groups of interface power supplies can be designed in the programmable logic device, and each group of power supplies can share one power supply voltage comparator, so that the design efficiency of the programmable logic device is improved.
Drawings
FIG. 1 is a schematic diagram of an adaptive level conversion circuit of the present invention;
FIG. 2 is a circuit schematic of a wide range level shifting unit of the present invention;
FIG. 3 is a circuit diagram of an acceleration level shifting unit according to the present invention;
FIG. 4 is a circuit diagram of an output driving unit according to the present invention;
FIG. 5 is a waveform diagram of the high voltage power supply of the present invention operating at high voltage;
fig. 6 is a waveform diagram of the high voltage power supply of the present invention operating at a low voltage.
Detailed Description
The basic idea of the invention is as follows: an adaptive level shift circuit includes a wide range level shift unit, an acceleration level shift unit, an output drive unit, and a power supply voltage comparator. The combination of the wide-range level conversion unit and the acceleration level conversion unit is used for meeting the requirements of various power supply voltages on the level conversion circuit, when the high-voltage power supply is high, only the wide-range level conversion unit is started, and when the high-voltage power supply is low, the wide-range level conversion unit and the acceleration level conversion unit are simultaneously started to increase the level conversion speed, so that the conversion speeds under the conditions of different power supply voltages can be kept consistent. By using the wide-range level conversion unit and the acceleration level conversion unit, the wide-range level conversion unit is designed to have different proportions of a P-channel MOS tube and an N-channel MOS tube in the wide-range level conversion unit and the acceleration level conversion unit aiming at the condition that a high-voltage power supply works under a higher voltage and the acceleration level conversion unit aiming at the condition that the high-voltage power supply works under a lower voltage, and the requirements of various power supply voltages on the area of a level conversion circuit device can be effectively reduced. The accelerating level conversion unit can be dynamically controlled by using the power supply voltage comparator, so that the self-adaptive level conversion capability under different power supply voltages is realized. Compared with the traditional level conversion circuit, the invention can provide a larger power supply voltage conversion range and can provide higher conversion speed under different power supply voltage environments.
The invention is described in further detail below with reference to the figures and the specific embodiments,
an adaptive level converting circuit, as shown in fig. 1, includes: a wide range level shift unit (101), an acceleration level shift unit (102), an output drive unit (103), a power supply voltage comparator (105), and an inverter (104);
the wide-range level conversion unit (101) comprises 4P-channel MOS tubes and 2N-channel MOS tubes as shown in FIG. 2; the source of the first P-channel MOS transistor P1(205) is connected with a high voltage power supply VCC _ H (211), and the source of the second P-channel MOS transistor P2(206) is connected with the high voltage power supply VCC _ H (211); the drain electrode of the first P-channel MOS transistor P1(205) is connected with the source electrode of the third P-channel MOS transistor P3 (207); the drain electrode of the second P-channel MOS transistor P2(206) is connected with the source electrode of the fourth P-channel MOS transistor P4 (208); the drain of the third P-channel MOS transistor P3(207) is connected to the drain of the first N-channel MOS transistor N1(209) as the output X2(203) of the wide-range level shifter unit; the drain of the fourth P-channel MOS transistor P4(208) is connected to the drain of the second N-channel MOS transistor N2(210) as the output X1(204) of the wide-range level shifter unit; the source electrode of the first N-channel MOS tube N1(209) is connected with the ground; the source of the second N-channel MOS transistor N2(210) is connected to ground; the gate of the first N-channel MOS transistor N1(209) is connected with the input end A (201) of the wide-range level conversion unit; the gate of the second N-channel MOS transistor N2(210) is connected with the input end AN (202) of the wide-range level conversion unit; the gate of the first P-channel MOS transistor P1(205) is connected with the output end X1(204) of the wide-range level conversion unit; the gate of the second P-channel MOS transistor P2(206) is connected to the output X2(203) of the wide-range level shifter unit; the gate of the third P-channel MOS tube P2(207) is connected with the input end A (201) of the wide-range level conversion unit; the gate of the fourth P-channel MOS tube P4(208) is connected with the input end AN (202) of the wide-range level conversion unit;
The acceleration level conversion unit (102) comprises 4P-channel MOS tubes and 2 transmission gates as shown in FIG. 3; the source of the first P-channel MOS transistor P5(307) is connected with a high-voltage power supply VCC _ H (311); the source of the second P-channel MOS transistor P6(308) is connected to a high voltage power supply VCC _ H (311); the source of the third P-channel MOS transistor P7(305) is connected to the high voltage power supply VCC _ H (311); the source of the fourth P-channel MOS transistor P8(306) is connected to the high voltage power supply VCC _ H (311); one data end of the first transmission gate T1(309) is connected to the drain of the first P-channel MOS transistor P5(307) and the gate of the third P-channel MOS transistor P7 (305); the other data end of the first transmission gate T1 is connected with the drain of a fourth P-channel MOS transistor P8(306) and the input end X1(302) of the acceleration level conversion unit; a data terminal of the second transmission gate T2(310) is connected to the drain of the second P-channel MOS transistor P6(308) and the gate of the fourth P-channel MOS transistor P8(306), and serves as an output terminal X3(303) of the acceleration level shifting unit; the other data end of the second transmission gate T2(310) is connected to the drain of the third P-channel MOS transistor P7(305) and the input end X2(301) of the acceleration level shifting unit; the gate of the first P-channel MOS tube P5(307) is connected with the input end C (304) of the acceleration level conversion unit; the gate of the second P-channel MOS tube P6(308) is connected with the input end C (304) of the acceleration level conversion unit; the control end of the first transmission gate T1(309) is connected with the input end C (304) of the acceleration level conversion unit; the control terminal of the second transmission gate T2(310) is connected to the input terminal C (304) of the acceleration level shifting unit;
The output driving unit (103) comprises 3P-channel MOS tubes and 2N-channel MOS tubes as shown in FIG. 4; the source electrode of the first P-channel MOS tube P9(405) is connected with a high-voltage power supply VCC _ H (410); the drain electrode of the first P-channel MOS transistor P9(405) is connected with the source electrode of the second P-channel MOS transistor P10 (406); the drain electrode of the second P-channel MOS tube P10(406) is connected with the output end Z (404) of the output driving unit; the source of the third P-channel MOS transistor P11(407) is connected to the high voltage power supply VCC _ H (410); the drain electrode of a third P-channel MOS tube P11(407) is connected with the output end Z (404) of the output driving unit; the source of the first N-channel MOS transistor N3(408) is connected to the ground; the source electrode of the second N-channel MOS tube N4(409) is connected with the ground; the drain electrode of the first N-channel MOS tube N3(408) is connected with the output end Z (404) of the acceleration level conversion unit; the drain electrode of a second N-channel MOS tube N4(409) is connected with the output end Z (404) of the acceleration level conversion unit; the gate of the first P-channel MOS transistor P9(405) is connected with the input end X2(401) of the output drive unit; the gate of the second P-channel MOS tube P10(406) is connected with the input end AN (402) of the output drive unit; the gate of the third P-channel MOS transistor P11(407) is connected to the input terminal X3(403) of the output driving unit; the gate of the first N-channel MOS transistor N3(408) is connected with the input end X2(401) of the output driving unit; the gate of the second N-channel MOS transistor N4(409) is connected to the input terminal AN (402) of the output driving unit.
A power supply voltage comparator (105) compares the values of a higher voltage power supply VCC _ H (108) and a reference voltage VREF (109), and the output of the power supply voltage comparator (105) controls an input end C (304) of the acceleration level conversion unit (102); when the voltage of the high voltage power supply VCC _ H (108) is lower than 2 times of the low voltage power supply VCC _ L (110), the acceleration level conversion unit (102) is started; the condition for accelerating the level shifter unit to turn on may also be defined by adjusting the value of the reference voltage VREF (109).
A plurality of adaptive level converting circuits may share a power supply voltage comparator (105); when the voltages of the high voltage power supply VCC _ H (108) and the low voltage power supply VCC _ L (110) of the plurality of adaptive level converting circuits are the same, the same power supply voltage comparator (105) can be used to drive a plurality of different acceleration level converting units (102).
The working mode of the self-adaptive level conversion circuit designed in the invention is as follows: under the condition that a high-voltage power supply works at a higher voltage, a control input end C (304) of an acceleration level conversion unit (102) is at a low level, a transmission gate T1(309) and a transmission gate T2(310) are closed, gates of a P channel MOS tube P7(305) and a P channel MOS tube P8(306) are set at a high level by opening a P channel MOS tube P5(307) and a P channel MOS tube P6(308), so that the P channel MOS tube P7(305) and the P channel MOS tube P8(306) are closed, and the acceleration level conversion unit (102) is in a closed state at the moment; when the input signal a (106) changes from low level to high level, the output of the inverter I1(104) changes from high level to low level, the N-channel MOS transistor N1(209) in the wide-range level conversion unit (101) is turned on, the N-channel MOS transistor N2(210) is turned off, so that the output terminal X2(203) of the wide-range level conversion unit (101) changes to low level, the P-channel MOS transistor P2(206) and the P-channel MOS transistor P4(208) are turned on, the output terminal X1(204) of the wide-range level conversion unit (102) changes to high level, the P-channel MOS transistor P1(205) is turned off, the P-channel MOS transistor P9(405) and the P-channel MOS transistor P10(406) in the output driving unit (103) are turned on, and the output terminal Z (107) outputs the voltage value of the high-voltage power supply VCC _ H (108); when the input signal a (106) changes from high level to low level, the output of the inverter I1(104) changes from low level to high level, the N-channel MOS transistor N2(210) in the wide-range level conversion unit (101) is turned on, the N-channel MOS transistor N1(209) is turned off, so that the output terminal X1(204) of the wide-range level conversion unit (101) changes to low level, the P-channel MOS transistor P1(205) and the P-channel MOS transistor P3(207) are turned on, the output terminal X2(204) of the wide-range level conversion unit (101) changes to high level, the P-channel MOS transistor P2(206) is turned off, the P-channel MOS transistor P9(405) and the P-channel MOS transistor P10(406) in the output driving unit (103) are turned off, the N-channel MOS transistor N3(408) is turned on, and the output terminal Z (107) outputs a voltage value of ground;
Under the condition that the high-voltage power supply works at a lower voltage, the control input end C (304) of the acceleration level conversion unit (102) is at a high level, the transmission gate T1(309) and the transmission gate T2(310) are opened, and the P-channel MOS transistor P5(307) and the P-channel MOS transistor P6(308) are closed; when the input signal a (106) changes from low level to high level, the output of the inverter I1(104) changes from high level to low level, the N channel MOS transistor N1(209) in the wide range level shift unit (101) is turned on, the N channel MOS transistor N2(210) is turned off, so that the output terminal X2(203) of the wide range level shift unit (101) changes to low level, the P channel MOS transistor P2(206) and the P channel MOS transistor P4(208) are turned on, the output terminal X1(204) of the wide range level shift unit (102) changes to high level, the P channel MOS transistor P1(205) is turned off, and at the same time, the P channel MOS transistor P8(306) in the acceleration level shift unit (102) is turned on, the output terminal X3(303) of the acceleration level shift unit (102) changes to low level, the P channel MOS transistor P9(405) and the P channel MOS transistor P10(406) in the output drive unit (103) are turned on, and the P channel MOS transistor P11 in the output drive unit (103) is turned on, the output end Z (107) outputs the voltage value of the high-voltage power supply VCC _ H (108); when the input signal A (106) changes from high level to low level, the output of the inverter I1(104) changes from low level to high level, the N channel MOS tube N2(210) in the wide range level conversion unit (101) is turned on, the N channel MOS tube N1(209) is turned off, so that the output X1(204) of the wide range level conversion unit (101) changes to low level, the P channel MOS tube P1(205) and the P channel MOS tube P3(207) are turned on, the output X2(204) of the wide range level conversion unit (101) changes to high level, the P channel MOS tube P2(206) is turned off, meanwhile, the P channel MOS tube P8(306) in the acceleration level conversion unit (102) is turned off, the output X3(303) of the acceleration level conversion unit (102) changes to high level, the P channel MOS tube P9(405) and the P channel MOS tube P10(406) in the output driving unit (103) are turned off, and the N channel MOS tube N3) is turned on, the output terminal Z (107) outputs the voltage value of the ground.
Fig. 5 is waveforms of output voltages of the adaptive level shifter circuit and the conventional level shifter circuit of the present invention when the high voltage power supply operates at a higher voltage, where the solid line is the waveform of the adaptive level shifter circuit of the present invention and the dotted line is the waveform of the conventional level shifter circuit.
Fig. 6 shows waveforms of output voltages of the adaptive level shifter circuit and the conventional level shifter circuit when the high-voltage power supply operates at a lower voltage, where the solid line is the waveform of the adaptive level shifter circuit of the present invention and the dotted line is the waveform of the conventional level shifter circuit.
The above description is only for the best mode of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
Claims (10)
1. An adaptive level conversion circuit, comprising: a wide range level shift unit (101), an acceleration level shift unit (102), and an output drive unit (103);
when the output voltage of the high-voltage power supply is not lower than a set threshold, the wide-range level conversion unit (101) controls a first driving module of the output driving unit (103) to output a first logic voltage corresponding to the logic of the input data A; when the output voltage of the high-voltage power supply is lower than a set threshold value, the acceleration level conversion unit (102) is started, and the wide-range level conversion unit (101) and the acceleration level conversion unit (102) respectively control the first driving module and the second driving module of the output driving unit (103) to output a second logic voltage corresponding to the logic of the input data A in parallel.
2. The adaptive level shifting circuit of claim 1, further comprising a power supply voltage comparator (105) that compares the high voltage power supply output voltage to a threshold value, and controls the acceleration level shifting unit (102) to turn off when not below the threshold value and controls the acceleration level shifting unit (102) to turn on when below the threshold value.
3. The adaptive level shifting circuit of claim 1 or 2, wherein the threshold is 2 times the low voltage power supply output voltage.
4. The adaptive level converting circuit of claim 1 or 2,
the wide range level shift unit (101) outputs a logic signal X2 corresponding to the logic of the input data A and a logic signal X1 logically opposite to the data A;
when the output voltage of the high-voltage power supply is not lower than a set threshold, the first driving module outputs a first path of current corresponding to the first logic voltage based on a logic signal X2;
when the output voltage of the high-voltage power supply is lower than a set threshold, the first driving module outputs a second path of current based on a logic signal X2; the acceleration level conversion unit (102) generates a logic signal X3 corresponding to the logic of the input data A based on the logic signals X2 and X1; the second driving module outputs a third current based on the logic signal X3; the second path of current and the third path of current are output in a superposition mode, and the output voltage is a second logic voltage.
5. The adaptive level converting circuit according to claim 4, wherein the wide range level converting unit (101) is configured as follows:
the sources of the first P-channel MOS tube (205) and the second P-channel MOS tube (206) are connected with a high-voltage power supply (211); the drain electrode of the first P-channel MOS tube (205) is connected with the source electrode of the third P-channel MOS tube (207); the drain electrode of the second P-channel MOS tube (206) is connected with the source electrode of the fourth P-channel MOS tube (208); the drain electrode of the third P-channel MOS tube (207) is connected with the drain electrode of the first N-channel MOS tube (209) and is used as the output end (203) of the logic signal X2; the drain electrode of the fourth P-channel MOS tube (208) is connected with the drain electrode of the second N-channel MOS tube (210) and is used as the output end (204) of the logic signal X1; the sources of the first N-channel MOS tube (209) and the second N-channel MOS tube (210) are connected to the ground;
The grid electrode of the first N-channel MOS tube (209) and the grid electrode of the third P-channel MOS tube (207) are connected with the data A; the grid electrode of the second N-channel MOS tube (210) and the reverse signal AN of the access data A of the fourth P-channel MOS tube (208);
the gate of the first P-channel MOS tube (205) is connected with the output end (204) of the logic signal X1; the gate of the second P-channel MOS (206) is connected to the output (203) of the logic signal X2.
6. The adaptive level shifting circuit of claim 4, wherein the turbo level shifting unit (102) is configured as follows:
the source electrode of the fifth P-channel MOS tube (307), the source electrode of the sixth P-channel MOS tube (308), the source electrode of the seventh P-channel MOS tube (305) and the source electrode of the eighth P-channel MOS tube (306) are connected with a high-voltage power supply (311); one data end of the first transmission gate (309) is connected with the drain electrode of the fifth P-channel MOS tube (307) and the grid electrode of the seventh P-channel MOS tube (305); the other data end of the first transmission gate is connected with the drain electrode of the eighth P-channel MOS tube (306) and is connected with a logic signal X1; one data end of the second transmission gate (310) is connected with the drain electrode of the sixth P-channel MOS tube (308) and the grid electrode of the fourth P-channel MOS tube (306) and is used as an output end X3(303) of the acceleration level conversion unit; the other data end of the second transmission gate (310) is connected with the drain electrode of the seventh P-channel MOS tube (305) and is connected with a logic signal X2; the grid electrode of the fifth P-channel MOS tube (307), the grid electrode of the sixth P-channel MOS tube P6(308), the control end of the first transmission gate (309) and the control end of the second transmission gate (310) are connected with the input end C (304) of the acceleration level conversion unit and are connected with the starting control signal of the acceleration level conversion unit (102).
7. The adaptive level converting circuit according to claim 4, wherein the output driving unit (103) is constituted as follows:
the source electrode of the ninth P-channel MOS tube (405) and the source electrode of the eleventh P-channel MOS tube (407) are connected with a high-voltage power supply (410), and the drain electrode of the ninth P-channel MOS tube (405) is connected with the source electrode of the tenth P-channel MOS tube (406); the drain electrode of the tenth P-channel MOS tube (406) is connected with the drain electrode of the eleventh P-channel MOS tube P11(407) to serve as an output end Z (404) of the output driving unit; the source electrode of the third N-channel MOS tube (408) and the source electrode of the fourth N-channel MOS tube (409) are connected to the ground; the drain electrode of the third N-channel MOS tube (408) is connected with the drain electrode of the fourth N-channel MOS tube (409) and is connected with the output end Z (404); the gate of the ninth P-channel MOS tube (405) is switched on a logic signal X2; the grid electrode of the tenth P-channel MOS tube (406) is connected with the grid electrode of the fourth N-channel MOS tube (409) and is connected with the reverse signal AN of the data A; the gate of the eleventh P-channel MOS tube (407) is switched on a logic signal X3 (403); the gate of the third N-channel MOS transistor (408) is connected to the logic signal X2 (401).
8. The adaptive level shifter circuit of claim 1 or 2, further comprising AN inverter having AN input terminal connected to the data a, a power terminal connected to the low voltage power source, and AN output signal AN that is AN inverse of the data a.
9. The adaptive level shifting circuit of claim 4, wherein a plurality of output driver units (103) are used in parallel, and the number of output driver units (103) connected in parallel is determined according to the magnitude of the output current.
10. The adaptive level shifting circuit of claim 6, wherein the aspect ratio of the seventh P-channel MOS transistor (305) and the fourth P-channel MOS transistor (306) is adjusted such that the switching speed of the output logic voltage of the first driver module is the same when the output voltage of the high voltage power supply is higher than the threshold value and lower than the threshold value.
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