CN217037162U

CN217037162U - Interface circuit compatible with open drain and push-pull modes and IC chip

Info

Publication number: CN217037162U
Application number: CN202121380227.5U
Authority: CN
Inventors: 刘桂云; 王小康
Original assignee: Huimang Microelectronics Shenzhen Co ltd
Current assignee: Huimang Microelectronics Shenzhen Co ltd
Priority date: 2021-06-21
Filing date: 2021-06-21
Publication date: 2022-07-22
Anticipated expiration: 2031-06-21

Abstract

The utility model discloses an interface circuit and an IC chip compatible with open-drain and push-pull modes, wherein the interface circuit comprises a pull-up PMOS (P-channel metal oxide semiconductor) tube, a pull-down NMOS (N-channel metal oxide semiconductor) tube, a voltage isolating switch and a control and drive circuit.

Description

Interface circuit compatible with open drain and push-pull modes and IC chip

Technical Field

The utility model relates to the field of ICs (integrated circuits), in particular to an interface circuit compatible with an open-drain mode and a push-pull mode and an IC chip.

Background

ICs typically use open drain and push-pull modes as output interface schemes:

as shown in fig. 1, for a conventional open-drain mode output interface, a pull-down nmos is usually provided inside a chip, and a pull-up resistor res may be integrated inside the chip or externally connected. The scheme has the advantage of simple structure, and when the pull-up resistor res is externally connected, the selection of the external pull-up voltage Vext is flexible and independent (can be equal to, lower than or higher than the chip supply voltage). When pull-down nmos is started, the power supply has the defects of conducting current to the ground and high active power consumption, and the pull-down nmos is mostly applied to medium and low speed occasions.

As shown in fig. 2, compared to the conventional open-drain mode output interface, a pull-up pmos is added in the conventional push-pull mode output interface. To be compatible with the open drain mode, nmos and pmos are typically controlled independently. When the push-pull type inverter is operated in a push-pull mode, similar to a cmos inverter, power consumption is generated only at the moment of state switching, and the push-pull type inverter has the advantages of high speed and low power consumption. When the push-pull mode works in the open-drain mode, pmos is usually closed, since an N well (N-well) of the pmos is usually connected with an IO (input/output) power supply voltage Vddio of a chip, in order to prevent a body diode from being conducted in a forward bias mode, an external pull-up voltage Vext is lower than Vddio + Vdiode (diode conduction voltage), and Vext usually does not exceed Vddio in the safety aspect, so that the selection of the external pull-up voltage is limited, and the push-pull mode cannot be completely compatible with the open-drain mode and is limited in application.

SUMMERY OF THE UTILITY MODEL

The present invention provides an interface circuit and an IC chip that are fully compatible with an open-drain mode and a push-pull mode, aiming at the defect that the push-pull mode of the interface circuit in the prior art is not fully compatible with the open-drain mode.

The technical scheme adopted by the utility model for solving the technical problem is as follows: an interface circuit compatible with open drain and push-pull modes is constructed and applied to an IC chip, and the interface circuit comprises a pull-up PMOS tube, a pull-down NMOS tube, a voltage isolating switch and a control and drive circuit; the source electrode and the N well of the pull-up PMOS tube are connected with the IO voltage of a chip, the drain electrode of the pull-up PMOS tube is connected with a chip interface through the voltage isolating switch, the drain electrode of the pull-down NMOS tube is connected with the chip interface, the source electrode and the P-type substrate of the pull-down NMOS tube are grounded, and the control and drive circuit is respectively connected with the grid electrode of the pull-up PMOS tube, the grid electrode of the pull-down NMOS tube and the control end of the voltage isolating switch; the control and drive circuit is used for controlling the voltage isolating switch to be in a voltage penetration state when the chip interface works in a push-pull mode, realizing push-pull output by using the pull-up PMOS tube and the pull-down NMOS tube together, controlling the voltage isolating switch to be in a voltage isolation state when the chip interface works in a leakage opening mode, and realizing leakage opening output by using the pull-down NMOS tube and the pull-up resistor.

Preferably, when the chip interface operates in a push-pull mode, the high and low levels output by the chip interface are a chip IO voltage and 0, respectively; when the chip interface works in an open-drain mode, the chip interface is connected with external power supply voltage through a pull-up resistor, the pull-up PMOS tube is in a closed state, and under the action of the pull-down NMOS tube and the pull-up resistor, high and low levels output by the chip interface are the external power supply voltage and 0 respectively.

Preferably, the voltage isolating switch adopts a depletion type NMOS transistor, a P-type substrate of the depletion type NMOS transistor is grounded, a source electrode of the depletion type NMOS transistor is connected to the chip interface, a drain electrode of the depletion type NMOS transistor is connected to a drain electrode of the pull-up PMOS transistor, and a gate electrode of the depletion type NMOS transistor is connected to the control and drive circuit.

Preferably, the control and drive circuit comprises a control circuit, a positive phase driver, a first inverse phase driver and a second inverse phase driver, wherein the control circuit is connected with the gate of the pull-up PMOS transistor through the first inverse phase driver, connected with the gate of the pull-down NMOS transistor through the second inverse phase driver, and connected with the gate of the depletion NMOS transistor through the positive phase driver.

Another aspect of the utility model provides an IC chip comprising an open drain and push-pull mode compatible interface circuit as described in any of the preceding claims.

The interface circuit and the IC chip compatible with the open-drain and push-pull modes have the following beneficial effects: the voltage isolating switch is arranged between the pull-up PMOS tube and the chip interface, the voltage isolating switch is in a voltage transmission state in a push-pull mode, the pull-up PMOS tube and the pull-down NMOS tube are used for realizing push-pull output together, the voltage isolating switch is in a voltage isolation state in an open-drain mode, and the pull-down NMOS tube and the pull-up resistor are used for realizing open-drain output.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts:

FIG. 1 is a schematic diagram of an open drain mode interface circuit;

FIG. 2 is a schematic diagram of a push-pull mode interface circuit;

FIG. 3 is a schematic diagram of an interface circuit compatible with open drain and push-pull modes according to the present invention;

FIG. 4 is a schematic diagram of an interface circuit compatible with open drain and push-pull modes according to the present invention implementing open drain and push-pull modes;

fig. 5 is a schematic diagram of a voltage isolation switch using a depletion type NMOS transistor to realize open drain and push-pull modes.

Detailed Description

To facilitate an understanding of the utility model, the utility model will now be described more fully with reference to the accompanying drawings. Exemplary embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The terms "first", "second", and the like, including ordinal numbers, used in the present specification may be used to describe various components, but the components are not limited by the terms. These terms are used only for the purpose of distinguishing one constituent element from other constituent elements. For example, a first component may be termed a second component, and, similarly, a second component may be termed a first component, without departing from the scope of the present invention. "connected" or "connecting" as used herein includes not only the direct connection of two entities but also the indirect connection through other entities that may have beneficial and improved effects.

The general idea of the utility model is as follows: a voltage isolating switch is arranged between a pull-up PMOS tube and a chip interface, the voltage isolating switch is in a voltage transmission state in a push-pull mode, the pull-up PMOS tube and a pull-down NMOS tube are used for realizing push-pull output together, the voltage isolating switch is in a voltage isolation state in an open-drain mode, and the pull-down NMOS tube and a pull-up resistor are used for realizing open-drain output, so that the open-drain and push-pull modes can be completely compatible.

In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to the drawings and the specific embodiments of the specification, and it should be understood that the embodiments and specific features of the embodiments of the present invention are detailed descriptions of the technical solutions of the present application, and are not limited to the technical solutions of the present application, and the technical features of the embodiments and examples of the present invention may be combined with each other without conflict.

Referring to fig. 3, the interface circuit compatible with the open-drain and push-pull modes of the present invention includes a pull-up PMOS transistor M1, a pull-down NMOS transistor M2, a voltage isolation switch, and a control and driving circuit.

The source electrode and the N well of the pull-up PMOS tube M1 are connected with a chip IO voltage Vdi, the drain electrode is connected with a chip interface through the voltage isolating switch, the drain electrode of the pull-down NMOS tube M2 is connected with the chip interface, the source electrode of the pull-down NMOS tube M2 is grounded with the P-type substrate, and the control and drive circuit is respectively connected with the grid electrode of the pull-up PMOS tube M1, the grid electrode of the pull-down NMOS tube M2 and the control end of the voltage isolating switch; the control and drive circuit is used for controlling the voltage isolation switch to be in a voltage transmission state when the chip interface works in a push-pull mode, realizing push-pull output by using the pull-up PMOS tube M1 and the pull-down NMOS tube M2 together, controlling the voltage isolation switch to be in a voltage isolation state when the chip interface works in a leakage-open mode, and realizing leakage-open output by using the pull-down NMOS tube M2 and a pull-up resistor res connected with the chip interface.

As shown in the left diagram of fig. 4, when the interface operates in the open-drain mode, the pull-up PMOS transistor M1 is in an off state, and under the action of the pull-down NMOS transistor M2 and the pull-up resistor res, the high and low levels output by the chip interface are external power supply voltages Vext and 0, where the external power supply voltage Vext may be lower than, equal to, or higher than the chip IO voltage, or may be the chip IO voltage. In order to prevent the body diode of the pull-up PMOS transistor M1 from being forward biased and conducting when Vext is higher than Vddio, the voltage isolation switch is controlled to be in a voltage isolation state (in the present scheme, represented by logic '0', and others may be represented by logic '1', both of which are within the protection scope of the present invention) at this stage, so that the voltage Vx at the drain terminal of the pull-up PMOS transistor M1 is always smaller than Vddio, Vext is independent of Vddio, and the chip interface operates normally, thereby being completely compatible with the open-drain mode.

As shown in the right diagram of fig. 4, when the interface operates in the push-pull mode, there is no pull-up resistor res, the high and low levels output by the chip interface are chip IO voltages Vddio and 0, respectively, and since the voltage isolation switch and the pull-up PMOS transistor M1 are in a series relationship, in order to reduce the on-resistance of the voltage isolation switch to the maximum extent possible, the voltage isolation switch is controlled to be in a voltage-passing state at this stage (represented by logic '1' in the diagram of the present embodiment, and the others may also be represented by logic '0', both being within the protection range of the present invention), so that the chip interface can meet the requirement of speed more easily when operating in the push-pull mode.

Referring to fig. 5, preferably, in an embodiment, the voltage isolation switch is a depletion type NMOS transistor M3, the P-type substrate of the depletion type NMOS transistor M3 is grounded, the source of the depletion type NMOS transistor M3 is connected to the chip interface, the drain of the depletion type NMOS transistor M3 is connected to the drain of the pull-up PMOS transistor M1, and the gate of the depletion type NMOS transistor M3 is connected to the control and driving circuit. Specifically, the control and drive circuit includes a control circuit, a positive phase driver, a first reverse phase driver, and a second reverse phase driver, where the control circuit is connected to the gate of the pull-up PMOS transistor M1 through the first reverse phase driver, connected to the gate of the pull-down NMOS transistor M2 through the second reverse phase driver, and connected to the gate of the depletion NMOS transistor M3 through the positive phase driver. The control circuit outputs control signals p _ ctrl, d _ ctrl and n _ ctrl to the first inverting driver, the non-inverting driver and the second inverting driver to control M1, M2 and M3.

The threshold voltage vth of the depletion NMOS transistor M3 is-0.8V. As shown in the left diagram of fig. 5, in the open-drain mode, the voltage of the gate of the depletion NMOS transistor M3 is 0V, and the voltage at the drain terminal of the pull-up PMOS transistor M1 is less than 1V, which plays a role of voltage isolation; as shown in the right diagram of fig. 5, in the push-pull mode, the gate of the depletion type NMOS transistor M3 is connected to the chip for supplying high voltage, so as to ensure good conductivity.

Based on the same idea, the present invention also claims an IC chip comprising an interface circuit compatible with open drain and push-pull modes as described in the previous embodiments.

In summary, the interface circuit and the IC chip compatible with the open-drain and push-pull modes of the present invention have the following advantages: the utility model sets a voltage isolating switch between the pull-up PMOS tube and the chip interface, the voltage isolating switch is in a voltage-passing state in the push-pull mode, the pull-up PMOS tube and the pull-down NMOS tube are used for realizing the push-pull output together, the voltage isolating switch is in a voltage-isolating state in the open-drain mode, and the pull-down NMOS tube and the pull-up resistor are used for realizing the open-drain output, so the utility model can be completely compatible with the open-drain and push-pull modes.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the utility model as defined in the appended claims.

Claims

1. An interface circuit compatible with open drain and push-pull modes is applied to an IC chip and is characterized in that the interface circuit comprises a pull-up PMOS tube, a pull-down NMOS tube, a voltage isolating switch and a control and drive circuit; the source electrode and the N well of the pull-up PMOS tube are connected with the IO voltage of a chip, the drain electrode is connected with a chip interface through the voltage isolating switch, the drain electrode of the pull-down NMOS tube is connected with the chip interface, the source electrode and the P-type substrate of the pull-down NMOS tube are grounded, and the control and drive circuit is respectively connected with the grid electrode of the pull-up PMOS tube, the grid electrode of the pull-down NMOS tube and the control end of the voltage isolating switch; the control and drive circuit is used for controlling the voltage isolating switch to be in a voltage penetration state when the chip interface works in a push-pull mode, realizing push-pull output by using the pull-up PMOS tube and the pull-down NMOS tube together, controlling the voltage isolating switch to be in a voltage isolation state when the chip interface works in a leakage opening mode, and realizing leakage opening output by using the pull-up resistor connected with the pull-down NMOS tube and the chip interface.

2. The open-drain and push-pull mode compatible interface circuit of claim 1, wherein the pull-up resistor is integrated within the chip or externally attached to the chip.

3. The open-drain and push-pull mode compatible interface circuit of claim 1, wherein when the chip interface operates in the push-pull mode, the high and low levels of the chip interface output are a chip IO voltage and 0, respectively; when the chip interface works in an open-drain mode, the chip interface is connected with external power supply voltage through a pull-up resistor, the pull-up PMOS tube is in a closed state, and under the action of the pull-down NMOS tube and the pull-up resistor, high and low levels output by the chip interface are the external power supply voltage and 0 respectively.

4. The interface circuit compatible with the open-drain and push-pull modes according to claim 1, wherein the voltage isolation switch adopts a depletion type NMOS tube, a P-type substrate of the depletion type NMOS tube is grounded, a source electrode of the depletion type NMOS tube is connected with the chip interface, a drain electrode of the depletion type NMOS tube is connected with a drain electrode of the pull-up PMOS tube, and a grid electrode of the depletion type NMOS tube is connected with the control and drive circuit.

5. The interface circuit compatible with open-drain and push-pull modes as claimed in claim 4, wherein the control and driving circuit comprises a control circuit, a positive phase driver, a first inverse phase driver, and a second inverse phase driver, the control circuit is connected to the gate of the pull-up PMOS transistor via the first inverse phase driver, connected to the gate of the pull-down NMOS transistor via the second inverse phase driver, and connected to the gate of the depletion NMOS transistor via the positive phase driver.

6. An IC chip comprising an open drain and push-pull mode compatible interface circuit as claimed in any of claims 1 to 5.