CN213402974U - Level conversion circuit and terminal - Google Patents
Level conversion circuit and terminal Download PDFInfo
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- CN213402974U CN213402974U CN202022625120.4U CN202022625120U CN213402974U CN 213402974 U CN213402974 U CN 213402974U CN 202022625120 U CN202022625120 U CN 202022625120U CN 213402974 U CN213402974 U CN 213402974U
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Abstract
A level switching circuit and a terminal are provided, wherein the level switching circuit comprises a first PMOS tube, a third PMOS tube, a first NMOS tube and a third NMOS tube which are sequentially connected in series; the second PMOS tube, the fourth PMOS tube, the second NMOS tube and the fourth NMOS tube are sequentially connected in series; the fifth PMOS tube, the seventh PMOS tube, the fifth NMOS tube and the seventh NMOS tube are sequentially connected in series; a sixth PMOS tube, an eighth PMOS tube, a sixth NMOS tube and an eighth NMOS tube which are sequentially connected in series; the drain electrode of the third PMOS tube is coupled with the drain electrode of the fourth PMOS tube and used as a first output end of the level conversion circuit; the drain electrode of the seventh PMOS tube is coupled with the drain electrode of the eighth PMOS tube and used as a second output end of the level conversion circuit. The utility model discloses technical scheme can use same circuit structure to realize step-up conversion and step-down conversion.
Description
Technical Field
The utility model relates to an integrated circuit technical field especially relates to a level shift circuit and terminal.
Background
A level shifting circuit (levelshifting circuit) is used to shift an input voltage to a different output voltage.
However, the prior art needs to use different circuit structures for the input signal boosting (high level conversion) and the input signal reducing (low level conversion). For a terminal with the requirements of voltage boosting and voltage reducing, a high level conversion circuit and a low level conversion circuit need to be arranged at the same time, so that the circuit area is large, and the level conversion is complex.
Disclosure of Invention
The utility model provides a technical problem how use same circuit structure to realize step-up conversion and step-down conversion.
In order to solve the above technical problem, an embodiment of the present invention provides a level shift circuit, which includes: the power supply circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a third PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a third NMOS tube which are sequentially connected in series, wherein the source electrode of the first PMOS tube is connected with a positive power supply voltage, the grid electrode of the first PMOS tube is connected with an input signal, the grid electrode of the third PMOS tube is connected with a first voltage, the grid electrode of the first NMOS tube is connected with a second voltage, the source electrode of the third NMOS tube is connected with a negative power supply voltage, and the grid electrode of the third NMOS tube is connected with the input signal; the second PMOS tube, the fourth PMOS tube, the second NMOS tube and the fourth NMOS tube are sequentially connected in series, the source electrode of the second PMOS tube is connected with the positive power supply voltage, the grid electrode of the second PMOS tube is connected with the input signal, the source electrode of the fourth NMOS tube is connected with the negative power supply voltage, and the grid electrode of the fourth NMOS tube is connected with the input signal; a fifth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, and a seventh NMOS transistor connected in series in sequence, where a source of the fifth PMOS transistor is connected to the positive power supply voltage, a gate of the fifth PMOS transistor is connected to the inverse voltage of the input signal, a gate of the seventh PMOS transistor is coupled to a drain of the fourth PMOS transistor, a drain of the seventh PMOS transistor is coupled to a gate of the fourth PMOS transistor, a gate of the fifth NMOS transistor is coupled to a drain of the fourth PMOS transistor, a drain of the fifth NMOS transistor is coupled to a gate of the fourth NMOS transistor, a source of the seventh NMOS transistor is connected to the negative power supply voltage, and a gate of the seventh NMOS transistor is connected to the inverse voltage of the input signal; a sixth PMOS tube, an eighth PMOS tube, a sixth NMOS tube and an eighth NMOS tube which are sequentially connected in series, wherein a source electrode of the sixth PMOS tube is connected with the positive power voltage, a grid electrode of the sixth PMOS tube is connected with the inverse voltage of the input signal, a grid electrode of the eighth PMOS tube is connected with the first voltage, a grid electrode of the sixth NMOS tube is connected with the second voltage, a source electrode of the eighth NMOS tube is connected with the negative power voltage, and a grid electrode of the eighth NMOS tube is connected with the inverse voltage of the input signal; the drain electrode of the third PMOS tube is coupled with the drain electrode of the fourth PMOS tube and is used as a first output end of the level conversion circuit; and the drain electrode of the seventh PMOS tube is coupled with the drain electrode of the eighth PMOS tube and is used as a second output end of the level conversion circuit.
Optionally, the level shifter is configured to boost, where the first voltage is the positive power supply voltage, and the second voltage is a high level of the input signal.
Optionally, the positive power supply voltage is greater than a high level of the input signal.
Optionally, the level shift circuit is configured to step down, the first voltage is a low level of the input signal, and the second voltage is the negative power supply voltage.
Optionally, the negative supply voltage is less than a low level of the input signal.
Optionally, the level shift circuit further includes: and one end of the phase inverter is connected with the input signal, and the other end of the phase inverter is coupled with the grids of the fifth PMOS tube, the sixth PMOS tube, the seventh NMOS tube and the eighth NMOS tube.
In order to solve the above technical problem, an embodiment of the present invention further discloses a configuration method based on the level shift circuit, where the configuration method includes: configuring the first voltage to be the positive supply voltage, the positive supply voltage being greater than a high level of the input signal; and configuring the second voltage as a high level of the input signal.
In order to solve the above technical problem, an embodiment of the present invention further discloses a configuration method based on the level shift circuit, where the configuration method includes: configuring the first voltage to be a low level of the input signal; configuring the second voltage to be the negative supply voltage, the negative supply voltage being less than a low level of the input signal.
The embodiment of the utility model provides a still disclose a terminal, the terminal includes level conversion circuit.
Compared with the prior art, the utility model discloses technical scheme has following beneficial effect:
the utility model discloses among the technical scheme, through the mutual coupling relation of each MOS pipe for switching on and turn-off of the voltage control MOS pipe that the grid that inserts through each MOS pipe realizes stepping up or stepping down to input signal, also uses same circuit structure to realize the conversion of stepping up and step-down, reduces circuit area, realizes level conversion's convenience.
Further, the level shift circuit is configured to boost, the first voltage is the positive power supply voltage, and the second voltage is a high level of the input signal; the level shift circuit is configured to step down, the first voltage is a low level of the input signal, and the second voltage is the negative power supply voltage. Because the utility model discloses technical scheme's level shift circuit can enough realize the conversion that steps up and can realize the step-down conversion again, consequently through setting up different levels for first voltage and second voltage to satisfy different level conversion demands.
Drawings
Fig. 1 is a schematic structural diagram of a level shift circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a level shift circuit in a boost scenario according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of the level shift circuit according to the embodiment of the present invention in a voltage reduction scenario.
Detailed Description
As described in the background, the prior art requires different circuit configurations for the input signal step-up (high level transition) and step-down (low level transition). For a terminal with the requirements of voltage boosting and voltage reducing, a high level conversion circuit and a low level conversion circuit need to be arranged at the same time, so that the circuit area is large, and the level conversion is complex.
The utility model discloses among the technical scheme, through the mutual coupling relation of each MOS pipe for switching on and turn-off of the voltage control MOS pipe that the grid that inserts through each MOS pipe realizes stepping up or stepping down to input signal, also uses same circuit structure to realize the conversion of stepping up and step-down, reduces circuit area, realizes level conversion's convenience.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic structural diagram of a level shift circuit according to an embodiment of the present invention.
As shown in FIG. 1, the level shifter circuit includes PMOS transistors P1-P8, and NMOS transistors N1-N8.
The first PMOS transistor P1, the third PMOS transistor P3, the first NMOS transistor N1, and the third NMOS transistor N3 are sequentially connected in series, that is, the drain of the first PMOS transistor P1 is coupled to the source of the third PMOS transistor P3, the drain of the third PMOS transistor P3 is coupled to the drain of the first NMOS transistor N1, and the source of the first NMOS transistor N1 is coupled to the drain of the third NMOS transistor N3.
Specifically, the source of the first PMOS transistor P1 is connected to a positive power supply voltage VOH, the gate of the first PMOS transistor P1 is connected to an input signal IN, the gate of the third PMOS transistor P3 is connected to a first voltage, the gate of the first NMOS transistor N1 is connected to a second voltage, the source of the third NMOS transistor N3 is connected to a negative power supply voltage VOL, and the gate of the third NMOS transistor N3 is connected to the input signal IN.
The second PMOS transistor P2, the fourth PMOS transistor P4, the second NMOS transistor N2, and the fourth NMOS transistor N4 are sequentially connected in series, that is, the drain of the second PMOS transistor P2 is coupled to the source of the fourth PMOS transistor P4, the drain of the fourth PMOS transistor P4 is coupled to the drain of the second NMOS transistor N2, and the source of the second NMOS transistor N2 is coupled to the drain of the fourth NMOS transistor N4.
Specifically, the source of the second PMOS transistor P2 is connected to the positive power voltage VOH, the gate of the second PMOS transistor P2 is connected to the input signal IN, the source of the fourth NMOS transistor N4 is connected to the negative power voltage VOL, and the gate of the fourth NMOS transistor N4 is connected to the input signal IN.
The fifth PMOS transistor P5, the seventh PMOS transistor P7, the fifth NMOS transistor N5 and the seventh NMOS transistor N7 are sequentially connected in series, that is, the drain of the fifth PMOS transistor P5 is coupled to the source of the seventh PMOS transistor P7, the drain of the seventh PMOS transistor P7 is coupled to the drain of the fifth NMOS transistor N5, and the source of the fifth NMOS transistor N5 is coupled to the drain of the seventh NMOS transistor N7.
Specifically, the source of the fifth PMOS transistor P5 is connected to the positive power voltage VOH, the gate of the fifth PMOS transistor P5 is connected to the inverted voltage INB of the input signal IN, the gate of the seventh PMOS transistor P7 is coupled to the drain of the fourth PMOS transistor P4, the drain of the seventh PMOS transistor P7 is coupled to the gate of the fourth PMOS transistor P4, the gate of the fifth NMOS transistor N5 is coupled to the drain of the fourth PMOS transistor P4, the drain of the fifth NMOS transistor N5 is coupled to the gate of the fourth NMOS transistor N4, the source of the seventh NMOS transistor N7 is connected to the negative power voltage VOL, and the gate of the seventh NMOS transistor N7 is connected to the inverted voltage INB of the input signal IN.
A sixth PMOS transistor P6, an eighth PMOS transistor P8, a sixth NMOS transistor N6, and an eighth NMOS transistor N8 are sequentially connected in series, that is, the drain of the sixth PMOS transistor P6 is coupled to the source of the eighth PMOS transistor P8, the drain of the eighth PMOS transistor P8 is coupled to the drain of the sixth NMOS transistor N6, and the source of the sixth NMOS transistor N6 is coupled to the drain of the eighth NMOS transistor N8.
Specifically, the source of the sixth PMOS transistor P6 is connected to the positive power voltage VOH, the gate of the sixth PMOS transistor P6 is connected to the inverse voltage INB of the input signal IN, the gate of the eighth PMOS transistor P8 is connected to the first voltage, the gate of the sixth NMOS transistor N6 is connected to the second voltage, the source of the eighth NMOS transistor N8 is connected to the negative power voltage VOL, and the gate of the eighth NMOS transistor N8 is connected to the inverse voltage INB of the input signal IN;
the drain of the third PMOS transistor P3 and the drain of the fourth PMOS transistor P4 are coupled to serve as the first output OUT of the level shift circuit; the drain of the seventh PMOS transistor P7 is coupled to the drain of the eighth PMOS transistor P8 to serve as the second output node OUTB of the level shifter circuit.
In this embodiment, when the level shifter is used for the step-up conversion, the level shifter can convert the input signal operating in the voltage domain VIH to VIL into the output signal operating in the voltage domain VOH to VIL, where VIH represents the high level of the input signal, VIL represents the low level of the input signal, and VOH represents the positive power supply voltage.
The level conversion circuit is used for converting input signals working in VIH-VIL voltage domains into output signals working in VIH-VOL voltage domains when voltage is reduced, wherein VOL represents negative power supply voltage.
The embodiment of the utility model provides an in, through the mutual coupling relation of each MOS pipe for switching on and turn-off of the voltage control MOS pipe that the grid that inserts through each MOS pipe realizes stepping up or stepping down to input signal, also uses same circuit structure to realize step-up conversion and step-down conversion, reduces circuit area, realizes level conversion's convenience.
In a non-limiting embodiment of the present invention, the level shift circuit is used for boosting, the first voltage is the positive power voltage, and the second voltage is the high level of the input signal.
Further, the positive power supply voltage is greater than the high level of the input signal.
Specifically, referring to fig. 2, the level shifter is used for converting an input signal of 0 to 1.8V into an output signal of 0 to 6V.
IN this embodiment, the input signal IN is 1.8V, and the inverted voltage INB of the input signal is 0V; the first voltage VP connected to the gate of the third PMOS transistor P3 and the gate of the eighth PMOS transistor P8 is 6V, and the second voltage VN connected to the gates of the first NMOS transistor N1 and the sixth NMOS transistor N6 is 1.8V.
In a specific implementation, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4 are turned off under the control of respective gate voltages, and the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are turned on under the control of respective gate voltages, so that the output voltage OUT output by the first output terminal is 0V.
Correspondingly, the fifth PMOS transistor P5, the sixth PMOS transistor P6, and the seventh PMOS transistor P7 are turned on under the control of the respective gate voltages, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 are turned off under the control of the respective gate voltages, and the output voltage OUTB output by the second output terminal is 6V.
In another non-limiting embodiment of the present invention, the level shift circuit is configured to step down, the first voltage is a low level of the input signal, and the second voltage is the negative power voltage.
Further, the negative supply voltage is less than a low level of the input signal.
Specifically, referring to fig. 3, the level shifter is used for converting an input signal of 0-1.8V into an output signal of 1.8-4.2V.
IN this embodiment, the input signal IN is 1.8V, and the inverted voltage INB of the input signal is 0V; the first voltage VP connected to the gate of the third PMOS transistor P3 and the gate of the eighth PMOS transistor P8 is 0V, and the second voltage VN connected to the gates of the first NMOS transistor N1 and the sixth NMOS transistor N6 is-4.2V.
In a specific implementation, the first PMOS transistor P1, the second PMOS transistor P2, and the fourth PMOS transistor P4 are turned off under the control of the respective gate voltages, and the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are turned on under the control of the respective gate voltages, so that the output voltage OUT output by the first output terminal is-4.2V.
Correspondingly, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7, and the eighth PMOS transistor P8 are turned on under the control of the respective gate voltages, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 are turned off under the control of the respective gate voltages, and the output voltage OUTB output by the second output terminal is 1.8V.
It should be understood by those skilled in the art that the input signal, the positive power voltage, the negative power voltage, the first voltage and the second voltage may also be set to any other applicable voltage values according to the actual level shift requirement, and the embodiment of the present invention is not limited thereto.
In a non-limiting embodiment of the present invention, the level shift circuit may include a phase inverter (not shown), one end of which is coupled to the input signal, and the other end of which is coupled to the gates of the fifth PMOS transistor, the sixth PMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor.
The embodiment of the present invention provides a non-limiting embodiment, the embodiment of the present invention also discloses a configuration method of a level shift circuit, the configuration method may include the following steps:
configuring the first voltage to be the positive supply voltage, the positive supply voltage being greater than a high level of the input signal; and configuring the second voltage as a high level of the input signal.
The utility model discloses configuration method can be used for the scene that steps up. And boosting the input signal according to the configured first voltage and the second voltage.
The embodiment of the present invention provides a non-limiting embodiment, the embodiment of the present invention also discloses a configuration method of a level shift circuit, the configuration method may include the following steps:
configuring the first voltage to be a low level of the input signal; configuring the second voltage to be the negative supply voltage, the negative supply voltage being less than a low level of the input signal.
The utility model discloses configuration method can be used for the decompression scene. And the step-down operation of the input signal is realized according to the configured first voltage and the second voltage.
By last, the embodiment of the utility model provides a can be through the different voltage value of configuration for first voltage, second voltage, positive supply voltage and negative supply voltage, can realize stepping up or stepping down to input signal, also can require to select different configurations according to the output level, realize level shift circuit's multiplexing, need not to dispose two sets of level shift circuit in the terminal.
The embodiment of the utility model provides a terminal is still disclosed, the terminal can include the level shift circuit that fig. 1, fig. 2 or fig. 3 show. The terminal includes, but is not limited to, a mobile phone, a computer, a tablet computer and other terminal devices.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention, and the scope of the present invention is defined by the appended claims.
Claims (7)
1. A level shift circuit, comprising:
the power supply circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a third PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a third NMOS tube which are sequentially connected in series, wherein the source electrode of the first PMOS tube is connected with a positive power supply voltage, the grid electrode of the first PMOS tube is connected with an input signal, the grid electrode of the third PMOS tube is connected with a first voltage, the grid electrode of the first NMOS tube is connected with a second voltage, the source electrode of the third NMOS tube is connected with a negative power supply voltage, and the grid electrode of the third NMOS tube is connected with the input signal;
the second PMOS tube, the fourth PMOS tube, the second NMOS tube and the fourth NMOS tube are sequentially connected in series, the source electrode of the second PMOS tube is connected with the positive power supply voltage, the grid electrode of the second PMOS tube is connected with the input signal, the source electrode of the fourth NMOS tube is connected with the negative power supply voltage, and the grid electrode of the fourth NMOS tube is connected with the input signal;
a fifth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, and a seventh NMOS transistor connected in series in sequence, where a source of the fifth PMOS transistor is connected to the positive power supply voltage, a gate of the fifth PMOS transistor is connected to the inverse voltage of the input signal, a gate of the seventh PMOS transistor is coupled to a drain of the fourth PMOS transistor, a drain of the seventh PMOS transistor is coupled to a gate of the fourth PMOS transistor, a gate of the fifth NMOS transistor is coupled to a drain of the fourth PMOS transistor, a drain of the fifth NMOS transistor is coupled to a gate of the fourth NMOS transistor, a source of the seventh NMOS transistor is connected to the negative power supply voltage, and a gate of the seventh NMOS transistor is connected to the inverse voltage of the input signal;
a sixth PMOS tube, an eighth PMOS tube, a sixth NMOS tube and an eighth NMOS tube which are sequentially connected in series, wherein a source electrode of the sixth PMOS tube is connected with the positive power voltage, a grid electrode of the sixth PMOS tube is connected with the inverse voltage of the input signal, a grid electrode of the eighth PMOS tube is connected with the first voltage, a grid electrode of the sixth NMOS tube is connected with the second voltage, a source electrode of the eighth NMOS tube is connected with the negative power voltage, and a grid electrode of the eighth NMOS tube is connected with the inverse voltage of the input signal;
the drain electrode of the third PMOS tube is coupled with the drain electrode of the fourth PMOS tube and is used as a first output end of the level conversion circuit; and the drain electrode of the seventh PMOS tube is coupled with the drain electrode of the eighth PMOS tube and is used as a second output end of the level conversion circuit.
2. The level shift circuit of claim 1, wherein the level shift circuit is configured to boost, the first voltage is the positive power supply voltage, and the second voltage is a high level of the input signal.
3. The level shift circuit of claim 2, wherein the positive supply voltage is greater than a high level of the input signal.
4. The level shift circuit of claim 1, wherein the level shift circuit is configured to step down, wherein the first voltage is a low level of the input signal, and wherein the second voltage is the negative supply voltage.
5. The level shift circuit of claim 4, wherein the negative supply voltage is less than a low level of the input signal.
6. The level shift circuit of claim 1, further comprising:
and one end of the phase inverter is connected with the input signal, and the other end of the phase inverter is coupled with the grids of the fifth PMOS tube, the sixth PMOS tube, the seventh NMOS tube and the eighth NMOS tube.
7. A terminal, characterized in that it comprises a level shifting circuit according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022625120.4U CN213402974U (en) | 2020-11-13 | 2020-11-13 | Level conversion circuit and terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022625120.4U CN213402974U (en) | 2020-11-13 | 2020-11-13 | Level conversion circuit and terminal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213402974U true CN213402974U (en) | 2021-06-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022625120.4U Active CN213402974U (en) | 2020-11-13 | 2020-11-13 | Level conversion circuit and terminal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213402974U (en) |
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2020
- 2020-11-13 CN CN202022625120.4U patent/CN213402974U/en active Active
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