CN112286276B - Positive and negative voltage control circuit based on MOS pipe - Google Patents

Positive and negative voltage control circuit based on MOS pipe Download PDF

Info

Publication number
CN112286276B
CN112286276B CN202011220948.XA CN202011220948A CN112286276B CN 112286276 B CN112286276 B CN 112286276B CN 202011220948 A CN202011220948 A CN 202011220948A CN 112286276 B CN112286276 B CN 112286276B
Authority
CN
China
Prior art keywords
resistor
tube
pmos
nmos
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202011220948.XA
Other languages
Chinese (zh)
Other versions
CN112286276A (en
Inventor
周阳阳
张�浩
万川川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 14 Research Institute
Original Assignee
CETC 14 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 14 Research Institute filed Critical CETC 14 Research Institute
Priority to CN202011220948.XA priority Critical patent/CN112286276B/en
Publication of CN112286276A publication Critical patent/CN112286276A/en
Application granted granted Critical
Publication of CN112286276B publication Critical patent/CN112286276B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
    • G05F1/571—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector

Abstract

The invention discloses a positive and negative voltage control circuit based on an MOS (metal oxide semiconductor) tube, which is characterized in that under the condition that only an MOS tube with lower working voltage is provided, a positive voltage domain voltage conversion module, a negative voltage domain voltage conversion module and an output stage are formed by a phase inverter and a plurality of MOS tubes, a resistor and a diode, positive voltage signals are input, positive and negative voltage is adopted for supplying power, the signal level value is improved, the MOS tube works normally, the positive and negative voltage signals are output, the time sequence problem of grid and body port control is solved, the MOS tube is prevented from being broken down due to overlarge differential pressure between the grid and the body port, and the negative voltage control of a radio frequency switching tube is realized.

Description

Positive and negative voltage control circuit based on MOS pipe
Technical Field
The invention belongs to the technical field of integrated circuit design and manufacture, and particularly relates to a MOS transistor circuit transformation technology.
Background
With the rapid development of communication systems, the requirements of radio frequency systems for radio frequency switch chips are higher and higher. The SOI has remarkable advantages in the aspects of insertion loss, isolation, power resistance and the like, and is widely used in the design of radio frequency switch products in recent years. With the continuous development of the integrated circuit SOI manufacturing process, the size of the transistor is smaller and smaller, and the operating voltage is also lower and lower. In the switch design, +3.3/-3 control significantly improves the linearity, 1dB compression point, and isolation of the switch. In the advanced SOI technology, as shown in FIG. 1, the gate of the RF switch tube needs +3.3/-3V control, and the body port needs 0/-3V control. Under the condition that only an MOS tube with the working voltage of 2.5V is used, the control of +3.3/-3V and 0/-3V is realized, which is one of the difficulties of the design of a radio frequency switch under the advanced SOI process.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a positive and negative voltage control circuit based on an MOS (metal oxide semiconductor) tube, and in order to achieve the purpose, the invention adopts the following technical scheme.
The circuit comprises a first phase inverter, a second phase inverter, a positive voltage domain voltage conversion module, a negative voltage domain voltage conversion module, a first output stage and a second output stage, wherein positive voltage low level signals are input, positive and negative voltages are adopted for power supply, the signal level value is improved, and positive and negative voltage high level signals are output.
The input end of the first phase inverter is used as the input of the circuit, the output end of the first phase inverter is connected with the input end of the second phase inverter, the first input end of the positive voltage domain voltage transformation module and the first input end of the negative voltage domain voltage transformation module, and the output end of the second phase inverter is connected with the second input end of the positive voltage domain voltage transformation module and the second input end of the negative voltage domain voltage transformation module.
The first, second, third and fourth output ends of the positive voltage domain voltage conversion module are connected with the first, second, third and fourth input ends of the first output stage, and the first, second, third and fourth output ends of the negative voltage domain voltage conversion module are connected with the seventh, eighth, ninth and tenth input ends of the first output stage.
The fifth output end of the positive voltage domain voltage conversion module and the fifth output end of the negative voltage domain voltage conversion module are connected in series through two resistors R1, the middle tap is connected with the fifth input end of the first output stage, the sixth output end of the positive voltage domain voltage conversion module and the sixth output end of the negative voltage domain voltage conversion module are connected in series through another two resistors R1, and the middle tap is connected with the sixth input end of the first output stage.
The first and second output terminals of the first output stage are used as the first and second outputs of the circuit, and are connected with the first and second output terminals of the second output stage,
And the first output end and the second output end of the second output stage are used as the third output and the fourth output of the circuit.
The positive voltage domain voltage conversion module adopts a bilateral symmetry design and comprises eight resistors R4, four resistors R3, four resistors R2, four PMOS tubes and eight NMOS tubes.
The left first resistor R4, the left second resistor R4, the left third resistor R4 and the left fourth resistor R4 are connected in series, the middle tap of the left first resistor R4 and the middle tap of the left second resistor R4 are used as second output ends, the middle tap of the left third resistor R4 and the middle tap of the left fourth resistor R4 are used as third output ends, the left first resistor R4 is connected with the source electrode of a left six-channel metal oxide semiconductor (PMOS) transistor, and the left fourth resistor R4 is connected with the source electrode of a left three-channel metal oxide semiconductor (NMOS) transistor.
The common drain of the left four NMOS tubes and the left five PMOS tubes is connected with the middle tap of the left two resistor R4 and the left three resistor R4 to be used as a fifth output end, and the source electrode of the left four NMOS tubes is connected with the drain electrode of the left three NMOS tubes.
The source electrode of the left second NMOS tube is connected with the drain electrode of the left first NMOS tube, the left first NMOS tube and the left third NMOS tube are connected in a common grid and common source mode, the common grid is used as a first input end through a left first resistor R2, and a left second resistor R2 is connected in parallel with the common grid and the common source.
The right first resistor R4, the right second resistor R4, the right third resistor R4 and the right fourth resistor R4 are connected in series, the middle tap of the right first resistor R4 and the middle tap of the right second resistor R4 are used as a first output end, the middle tap of the right third resistor R4 and the middle tap of the right fourth resistor R4 are used as a fourth output end, the right first resistor R4 is connected with the source electrode of the right six PMOS tube, and the right fourth resistor R4 is connected with the source electrode of the right three NMOS tubes.
The common drain of the right four NMOS tubes and the right five PMOS tubes is connected with the middle tap of the right two and right three resistors R4 to serve as a sixth output end, and the source electrode of the right four NMOS tubes is connected with the drain electrode of the right three NMOS tubes.
The source electrode of the right second NMOS tube is connected with the drain electrode of the right first NMOS tube, the right first NMOS tube and the right third NMOS tube are connected in a common grid and common source mode, the common grid is used as a second input end through a right first resistor R2, and a right second resistor R2 is connected in parallel with the common grid and the common source.
The left resistor R3 is connected with the grid and the source of the right six PMOS tube in parallel, the right resistor R3 is connected with the grid and the source of the left six PMOS tube in parallel, the drain of the left two NMOS tubes is connected with the grid of the right six PMOS tube through the left two resistor R3, and the drain of the right two NMOS tubes is connected with the grid of the left six PMOS tube through the right two resistor R3.
The left six PMOS tube and the right six PMOS tube share a common source as a positive power supply end, and the left three NMOS tube and the right three NMOS tube share a common source as a negative power supply end.
The negative voltage domain voltage conversion module adopts a bilateral symmetry design and comprises eight resistors R8, four resistors R7, two resistors R5, two resistors R6, four NMOS transistors and eight PMOS transistors.
The left first resistor R8, the left second resistor R8, the left third resistor R8 and the left fourth resistor R8 are connected in series, the middle tap of the left first resistor R8 and the middle tap of the left second resistor R8 are used as second output ends, the middle tap of the left third resistor R8 and the middle tap of the left fourth resistor R8 are used as third output ends, the left first resistor R8 is connected with the source electrode of a left nine PMOS tube, and the left fourth resistor R8 is connected with the source electrode of a left twelve NMOS tube.
The common drain of the left ten PMOS tube and the left eleven NMOS tube is connected with a middle tap of a left two-resistor R8 and a left three-resistor R8 to serve as a sixth output end, the source electrode of the left ten PMOS tube is connected with the drain electrode of a left nine PMOS tube, and the source electrode of the left eleven NMOS tube is connected with the drain electrode of a left twelve NMOS tube.
The left second resistor R7 is connected in parallel with the grid and the source of the left twelve NMOS transistors, the grid is connected with the drain of the left eight PMOS transistor through the left first resistor R7, the source is connected with the grid of the left seven PMOS transistor through the left first resistor R6, and the source of the left eight PMOS transistor is connected with the drain of the left seven PMOS transistor.
The right first resistor R8, the right second resistor R8, the right third resistor R8 and the right fourth resistor R8 are connected in series, the middle tap of the right first resistor R8 and the middle tap of the right second resistor R8 are used as a first output end, the middle tap of the right third resistor R8 and the middle tap of the right fourth resistor R8 are used as a fourth output end, the right first resistor R8 is connected with the source electrode of a right nine PMOS tube, and the right fourth resistor R8 is connected with the source electrode of a right twelve NMOS tube.
The common leakage of the right ten PMOS tube and the right eleven NMOS tube is connected with a middle tap of a right two-resistor R8 and a right three-resistor R8 to serve as a fifth output end, the source electrode of the right ten PMOS tube is connected with the drain electrode of a right nine PMOS tube, and the source electrode of the right eleven NMOS tube is connected with the drain electrode of a right twelve NMOS tube.
The right two-resistor R7 is connected in parallel with the grid and the source of the twelve right NMOS transistor, the grid is connected with the drain of the eight right PMOS transistor through the right one-resistor R7, the source is connected with the grid of the seven right PMOS transistor through the right one-resistor R6, and the source of the eight right PMOS transistor is connected with the drain of the seven right PMOS transistor.
The left seven PMOS tube and the right nine PMOS tube are connected in a common grid and a common source, the common grid is used as a first input end through a left resistor R5, and the common source is connected with the source electrode of the left nine PMOS tube.
The seven right PMOS tubes are connected with the nine left PMOS tubes in a common grid and common source mode, the common grid is used as a second input end through a right resistor R5, and the common source is connected with the source electrodes of the nine right PMOS tubes.
The common source of the left seven PMOS tube and the right seven PMOS tube is used as a positive power supply end, and the common source of the left twelve NMOS tube and the right twelve NMOS tube is used as a negative power supply end.
The first output stage is designed in a bilateral symmetry mode and comprises eight PMOS tubes and eight NMOS tubes.
A common gate of the left twenty NMOS tube and the left twenty-one PMOS tube is used as a fifth input end, and a common drain is used as a second output end; the source electrode of the left twenty-one NMOS tube is connected with the drain electrode of the left nineteen NMOS tube, and the source electrode of the left twenty-one PMOS tube is connected with the drain electrode of the left twenty-two PMOS tube.
The grid electrode of the nineteen left NMOS tube is used as a seventh input end, and the source electrode is connected with the drain electrode of the eighteen left NMOS tube; and the grid electrode of the seventeen left NMOS tube is used as a ninth input end, and the drain electrode of the seventeen left NMOS tube is connected with the source electrode of the eighteen left NMOS tube.
The grid electrode of the left twenty-two PMOS tube is used as a third input end, and the source electrode of the left twenty-three PMOS tube is connected with the drain electrode of the left twenty-three PMOS tube; the grid electrode of the left twenty-four PMOS tube is used as a first input end, and the drain electrode of the left twenty-four PMOS tube is connected with the source electrode of the left twenty-three PMOS tube.
The common gate of the twenty-right NMOS tube and the twenty-first PMOS tube is used as a sixth input end, and the common drain is used as a first output end; the source electrode of the twenty-right NMOS tube is connected with the drain electrode of the nineteen-right NMOS tube, and the source electrode of the twenty-first PMOS tube is connected with the drain electrode of the twenty-second PMOS tube.
The grid electrode of the nineteen right NMOS tube is used as an eighth input end, and the source electrode is connected with the drain electrode of the eighteen right NMOS tube; and the grid electrode of the seventeenth right NMOS tube is used as a tenth input end, and the drain electrode of the seventeenth right NMOS tube is connected with the source electrode of the eighteenth right NMOS tube.
The grid electrode of the twenty-two right PMOS tube is used as a fourth input end, and the source electrode of the twenty-two right PMOS tube is connected with the drain electrode of the twenty-three right PMOS tube; and the grid electrode of the right twenty-four PMOS tube is used as a second input end, and the drain electrode of the right twenty-four PMOS tube is connected with the source electrode of the right twenty-three PMOS tube.
The common source of the left twenty-four PMOS tube and the right twenty-four PMOS tube is used as a positive power supply end, and the common source of the left seventeen NMOS tube and the right seventeen NMOS tube is used as a negative power supply end.
The second output stage adopts a bilateral symmetry design and comprises four PMOS tubes, four NMOS tubes, two resistors R9, two resistors R10 and two diode groups.
The common drain of the left fifteen PMOS tubes and the left fourteen NMOS tubes is used as a first output end, the source electrode of the left fifteen PMOS tubes is connected with the drain electrode of the left sixteen PMOS tubes, and the grid electrode of the left sixteen PMOS tubes is used as a fourth input end.
The source electrode of the left fourteen NMOS tube is connected with the drain electrode of the left thirteen NMOS tube, the left resistor R10 is connected with the grid electrode and the source electrode of the left thirteen NMOS tube in parallel, the anode of the left diode group is used as a first input end, and the cathode of the left diode group is connected with the grid electrode of the left thirteen NMOS tube through the left resistor R9.
The common drain of the fifteenth right PMOS tube and the fourteenth right NMOS tube is used as a second output end, the source electrode of the fifteenth right PMOS tube is connected with the drain electrode of the sixteenth right PMOS tube, and the grid electrode of the sixteenth right PMOS tube is used as a third input end.
The source electrode of the fourteen right NMOS tube is connected with the drain electrode of the thirteen right NMOS tube, the right resistor R10 is connected with the grid electrode and the source electrode of the thirteen right NMOS tube in parallel, the anode of the right diode group is used as a second input end, and the cathode of the right diode group is connected with the grid electrode of the thirteen right NMOS tube through the right resistor R9.
And the common source of the lefthand sixteen PMOS tube and the righthand sixteen PMOS tube is used as a positive power supply end, and the common source of the lefthand thirteen NMOS tube and the righthand thirteen NMOS tube is used as a negative power supply end.
The MOS tube adopts a 2.5V process, resistors R1, R2, R3, R4, R5, R6, R7, R8, R9 and R10 adopt thousands of ohms, wherein R5/R6 is 25/33, R9/R10 is 23/33, and the left diode group and the right diode group respectively adopt 5 0.7V diodes which are connected in series.
The first phase inverter and the second phase inverter are powered by 2.5V, the positive power supply end of the positive voltage domain voltage conversion module is powered by 3.3V, the negative power supply end of the positive voltage domain voltage conversion module is grounded, the positive power supply end of the negative voltage domain voltage conversion module is grounded, the negative power supply end of the negative voltage domain voltage conversion module is powered by-3.3V, the positive power supply end of the first output stage is powered by 3.3V, the negative power supply end of the negative voltage domain voltage conversion module is powered by-3.3V, the positive power supply end of the second output stage is grounded, and the negative power supply end of the second output stage is powered by-3.3V.
The grid electrodes of the MOS tubes of the left two, the left four, the left five, the left twenty three, the right two, the right four, the right five and the right twenty three are powered by 1.65V, and the grid electrodes of the MOS tubes of the left eight, the left ten, the left eleven, the left fourteen, the left fifteen, the left eighteen, the right eight, the right ten, the right eleven, the right fourteen, the right fifteen and the right eighteen are powered by-1.65V.
The high and low levels of the control signal are respectively input to be 0/2.5V, the first phase inverter 101 outputs 2.5V/0, the second phase inverter outputs 0/2.5V, each MOS tube is correspondingly switched on or switched off, and each node presents the high and low levels.
The input and output levels of the positive voltage domain voltage conversion module are as follows:
the first input end is 2.5V/0, the fifth output end is 0/3.3V, the third output end is 0/1.65V, and the second output end
1.65V/3.3V, a second input end of 0/2.5V, a sixth output end of 3.3V/0, a first output end of 3.3V/1.65V and a fourth output end of 1.65V/0.
The input and output levels of the negative voltage domain voltage conversion module are as follows:
a first input terminal of 2.5V/0, a fifth output terminal of-3.3V/0, a first output terminal of-1.65V/0, a fourth output terminal of-3.3V/-1.65V, a second input terminal of 0/2.5V, a sixth output terminal of 0/-3.3V, a third output terminal of-1.65V/-3.3V, and a second output terminal of 0/-1.65V.
First output stage input-output level:
the first input terminal is 3.3V/1.65V, the second input terminal is 1.65V/3.3V, the third input terminal is 0/1.65V, the fourth input terminal is 1.65V/0, the fifth input terminal is-1.65V/1.65V, the sixth input terminal is 1.65V/-1.65V, the seventh input terminal is-1.65V/0, the eighth input terminal is 0/-1.65V, the ninth input terminal is-1.65V/-3.3V, the tenth input terminal is-3.3V/-1.65V, the first output terminal is 3.3V/-3V, and the second output terminal is-3V/3.3V.
Second output stage input-output level:
a first input terminal of 3.3V/-3V, a second input terminal of-3V/3.3V, a third input terminal of 0/-1.65V, a fourth input terminal of-1.65V/0, a first output terminal of 0/-3V, a second output terminal of-3V/0.
The input signal rises from-3V to 0.5V, the diode group is not conducted, and the grid level of the MOS tube keeps-3V; when the input signal exceeds 0.5V, the diode group is conducted, the voltage drop is 0.7V multiplied by 5, and the grid level of the MOS transistor is the input signal minus 3.5V.
The voltage difference between any two ports of each MOS tube is less than or equal to 2.5V and is in a voltage range of safe operation.
The invention outputs the positive and negative voltage control signals with higher voltage value under the condition of only the MOS tube with lower working voltage, so that the switch MOS tube works normally, the time sequence problem of the control of the grid electrode and the body port is solved, the breakdown of the switch MOS tube due to overlarge pressure difference between the grid electrode and the body port is avoided, and the negative pressure control of the radio frequency switch tube is realized.
Drawings
Fig. 1 is a schematic diagram of on/off of a MOS transistor, fig. 2 is a schematic diagram of a circuit configuration, fig. 3 is a schematic diagram of a positive voltage domain voltage conversion module circuit, fig. 4 is a schematic diagram of a negative voltage domain voltage conversion module circuit, fig. 5 is a schematic diagram of a first output stage circuit, fig. 6 is a schematic diagram of a second output stage circuit, fig. 7 is a schematic diagram of levels of respective nodes of the positive voltage domain voltage conversion module, fig. 8 is a schematic diagram of levels of respective nodes of the negative voltage domain voltage conversion module, fig. 9 is a schematic diagram of levels of respective nodes of the first output stage, fig. 10 is a schematic diagram of levels of respective nodes of the second output stage, fig. 11 is a waveform diagram of levels of a port of a switching MOS transistor not using a diode group, and fig. 12 is a waveform diagram of levels of a port of a switching MOS transistor using a diode group.
Reference numerals: 101-inverter, 102-positive voltage domain voltage transformation module, 103-negative voltage domain voltage transformation module, 104-first output stage, 105-second output stage, M1L … … M24L-left one MOS tube … …, left twenty-four MOS tube, M1R … … M24R-right one MOS tube … …, gate level of v 2L-left thirteen MOS tube and gate level of v 2R-right thirteen MOS tube.
Detailed Description
The technical scheme of the invention is specifically described below by taking a 2.5V process MOS tube as an example in combination with the attached drawings.
The circuit comprises a first inverter 101, a second inverter 101, a positive voltage domain voltage transformation module 102, a negative voltage domain voltage transformation module 103, a first output stage 104 and a second output stage 105, and the principle is as shown in fig. 2:
an input end of the first inverter 101 serves as an input of the circuit, an output end of the first inverter 101 is connected to an input end of the second inverter 101, a first input end of the positive voltage domain voltage transformation module 102 and a first input end of the negative voltage domain voltage transformation module 103, and an output end of the second inverter 101 is connected to a second input end of the positive voltage domain voltage transformation module 102 and a second input end of the negative voltage domain voltage transformation module 103.
The first, second, third and fourth output terminals of the positive voltage domain voltage transformation module 102 are connected to the first, second, third and fourth input terminals of the first output stage 104, and the first, second, third and fourth output terminals of the negative voltage domain voltage transformation module 103 are connected to the seventh, eighth, ninth and tenth input terminals of the first output stage 104.
The fifth output end of the positive voltage domain voltage conversion module 102 and the fifth output end of the negative voltage domain voltage conversion module 103 are connected through two resistors R1, a middle tap is connected with the fifth input end of the first output stage 104, a sixth output end of the positive voltage domain voltage conversion module 102 and a sixth output end of the negative voltage domain voltage conversion module 103 are connected through two resistors R1, and the middle tap is connected with the sixth input end of the first output stage 104.
The first and second output terminals of the first output stage 104 are used as the first and second outputs of the circuit, and are connected to the first and second input terminals of the second output stage 105, the first and second output terminals of the negative voltage domain voltage conversion module 103 are connected to the fourth and third input terminals of the second output stage 105, and the first and second output terminals of the second output stage 105 are used as the third and fourth outputs of the circuit.
The positive voltage domain voltage conversion module 102 adopts a bilateral symmetry design, and the principle is as shown in fig. 3:
the left first resistor R4, the left second resistor R4, the left third resistor R4 and the left fourth resistor R4 are connected in series, the middle tap of the left first resistor R4 and the middle tap of the left second resistor R4 are used as second output ends, the middle tap of the left third resistor R4 and the middle tap of the left fourth resistor R4 are used as third output ends, the left first resistor R4 is connected with the source electrode of a left six-PMOS transistor M6L, and the left fourth resistor R4 is connected with the source electrode of a left three-NMOS transistor M3L.
The common drain of the left four NMOS transistor M4L and the left five PMOS transistor M5L is connected with the middle tap of the left two resistor R4 and the left three resistor R4 to serve as a fifth output end, and the source electrode of the left four NMOS transistor M4L is connected with the drain electrode of the left three NMOS transistor M3L.
The source electrode of the left second NMOS transistor M2L is connected with the drain electrode of the left first NMOS transistor M1L, the left first NMOS transistor M1L is connected with the left third NMOS transistor M3L in a common-gate and common-source mode, the common-gate electrode is used as a first input end through a left first resistor R2, and a left second resistor R2 is connected with the common-gate electrode and the common-source electrode in parallel.
The right first resistor R4, the right second resistor R4, the right third resistor R4 and the right fourth resistor R4 are connected in series, the middle tap of the right first resistor R4 and the right second resistor R4 is used as a first output end, the middle tap of the right third resistor R4 and the right fourth resistor R4 is used as a fourth output end, the right first resistor R4 is connected with the source electrode of a right six PMOS tube M6R, and the right fourth resistor R4 is connected with the source electrode of a right three NMOS tube M3R.
The common drain of the right four NMOS transistor M4R and the right five PMOS transistor M5R is connected with the middle tap of the right two and right three resistors R4 to serve as a sixth output end, and the source electrode of the right four NMOS transistor M4R is connected with the drain electrode of the right three NMOS transistor M3R.
The source electrode of the right second NMOS transistor M2R is connected with the drain electrode of the right first NMOS transistor M1R, the right first NMOS transistor M1R is connected with the common gate and the common source of the right third NMOS transistor M3R, the common gate is used as a second input end through a right first resistor R2, and a right second resistor R2 is connected with the common gate and the common source in parallel.
The left resistor R3 is connected in parallel with the grid and the source of the right six PMOS tube M6R, the right resistor R3 is connected in parallel with the grid and the source of the left six PMOS tube M6L, the drain of the left two NMOS tubes M2L is connected with the grid of the right six PMOS tube through the left two resistor R3, and the drain of the right two NMOS tubes M2R is connected with the grid of the left six PMOS tube through the right two resistor R3.
The left six PMOS tube M6L and the right six PMOS tube M6R share common sources as a positive power supply end, and the left three NMOS tube M3L and the right three NMOS tube M3R share common sources as a negative power supply end.
The negative voltage domain voltage conversion module 103 adopts a bilateral symmetry design, and the principle is as shown in fig. 4:
the left first resistor R8, the left second resistor R8, the left third resistor R8 and the left fourth resistor R8 are connected in series, the middle tap of the left first resistor R8 and the middle tap of the left second resistor R8 are used as second output ends, the middle tap of the left third resistor R8 and the middle tap of the left fourth resistor R8 are used as third output ends, the left first resistor R8 is connected with the source electrode of a left nine PMOS tube M9L, and the left fourth resistor R8 is connected with the source electrode of a left twelve NMOS tube M12L.
The common drain of the left ten PMOS tube M10L and the left eleven NMOS tube M11L is connected with the middle tap of the left two and left three resistors R8 to serve as a sixth output end, the source electrode of the left ten PMOS tube M10L is connected with the drain electrode of the left nine PMOS tube M9L, and the source electrode of the left eleven NMOS tube M11L is connected with the drain electrode of the left twelve NMOS tube M12L.
The left second resistor R7 is connected in parallel with the grid and the source of the left twelve NMOS transistor M12L, the grid is connected with the drain of the left eight PMOS transistor M8L through the left first resistor R7, the source is connected with the grid of the left seven PMOS transistor M7L through the left first resistor R6, and the source of the left eight PMOS transistor M8L is connected with the drain of the left seven PMOS transistor M7L.
The right first resistor R8, the right second resistor R8, the right third resistor R8 and the right fourth resistor R8 are connected in series, the middle tap of the right first resistor R8 and the right second resistor R8 is used as a first output end, the middle tap of the right third resistor R8 and the right fourth resistor R8 is used as a fourth output end, the right first resistor R8 is connected with the source electrode of a right nine PMOS tube M9R, and the right fourth resistor R8 is connected with the source electrode of a right twelve NMOS tube M12R.
The common drain of the right ten PMOS tube M10R and the right eleven NMOS tube M11R is connected with the middle tap of the right two and right three resistors R8 to serve as a fifth output end, the source electrode of the right ten PMOS tube M10R is connected with the drain electrode of the right nine PMOS tube M9R, and the source electrode of the right eleven NMOS tube M11R is connected with the drain electrode of the right twelve NMOS tube M12R.
The right second resistor R7 is connected in parallel with the grid and the source of the right twelve NMOS transistor M12R, the grid is connected with the drain of the right eight PMOS transistor M8R through the right first resistor R7, the source is connected with the grid of the right seven PMOS transistor M7R through the right first resistor R6, and the source of the right eight PMOS transistor M8R is connected with the drain of the right seven PMOS transistor M7R.
The left seven PMOS tube M7L and the right nine PMOS tube M9R are connected in a common grid and a common source, the common grid is used as a first input end through a left resistor R5, and the common source is connected with the source electrode of the left nine PMOS tube M9L.
The right seven PMOS tube M7R and the left nine PMOS tube M9L are connected in common grid and common source, the common grid is used as a second input end through a right resistor R5, and the common source is connected with the source electrode of the right nine PMOS tube M9R.
The common source of the left seven PMOS tube M7L and the right seven PMOS tube M7R is used as a positive power supply end, and the common source of the left twelve NMOS tube M12L and the right twelve NMOS tube M12R is used as a negative power supply end.
The first output stage 104 adopts a bilateral symmetry design, and the principle is shown in fig. 5:
the common gate of the left twenty NMOS transistor M20L and the left twenty-one PMOS transistor M21L is used as a fifth input end, and the common drain is used as a second output end; the source of the left twenty-NMOS transistor M20L is connected to the drain of the left nineteen-NMOS transistor M19L, and the source of the left twenty-one-PMOS transistor M21L is connected to the drain of the left twenty-two-PMOS transistor M22L.
The grid electrode of the nineteen left NMOS transistor M19L is used as a seventh input end, and the source electrode is connected with the drain electrode of the eighteen left NMOS transistor M18L; the grid electrode of the seventeen left NMOS tube M17L is used as a ninth input end, and the drain electrode is connected with the source electrode of the eighteen left NMOS tube M18L.
The grid electrode of the left twenty-two PMOS tube M22L is used as a third input end, and the source electrode is connected with the drain electrode of the left twenty-three PMOS tube M23L; the gate of the twenty-four left PMOS transistor M24L is used as the first input terminal, and the drain is connected to the source of the twenty-three left PMOS transistor M23L.
The common gates of the twenty-right NMOS transistor M20R and the twenty-first PMOS transistor M21R are used as a sixth input end, and the common drains are used as a first output end; the source electrode of the twenty-right NMOS transistor M20R is connected with the drain electrode of the nineteen NMOS transistor M19R, and the source electrode of the twenty-first PMOS transistor M21R is connected with the drain electrode of the twenty-second PMOS transistor M22R.
The grid electrode of the nineteen right NMOS tube M19R is used as an eighth input end, and the source electrode is connected with the drain electrode of the eighteen right NMOS tube; the grid electrode of the seventeenth right NMOS tube M17R is used as a tenth input end, and the drain electrode is connected with the source electrode of the eighteenth right NMOS tube.
The grid electrode of the right twenty-two PMOS tube M22R is used as a fourth input end, and the source electrode is connected with the drain electrode of the right twenty-three PMOS tube M23R; the gate of the right twenty-four PMOS transistor M24R is used as a second input end, and the drain is connected with the source of the right twenty-three PMOS transistor M23R.
The common source of the left twenty-four PMOS tube M24L and the right twenty-four PMOS tube M24R is used as a positive power supply end, and the common source of the left seventeen NMOS tube M17L and the right seventeen NMOS tube M17R is used as a negative power supply end.
The second output stage 105 is designed in a bilateral symmetry mode, and the principle is shown in fig. 6:
the common drain of the fifteenth left PMOS transistor M15L and the fourteenth left NMOS transistor M14L serves as a first output terminal, the source of the fifteenth left PMOS transistor M15L is connected to the drain of the sixteenth left PMOS transistor M16L, and the gate of the sixteenth left PMOS transistor M16L serves as a fourth input terminal.
The source electrode of the left fourteen NMOS tube M14L is connected with the drain electrode of the left thirteen NMOS tube M13L, the left first resistor R10 is connected with the grid electrode and the source electrode of the left thirteen NMOS tube M13L in parallel, the anode of the left diode group D15 is used as a first input end, and the cathode of the left diode group D15 is connected with the grid electrode of the left thirteen NMOS tube M13L through the left first resistor R9.
The common drain of the fifteenth right PMOS transistor M15R and the fourteenth right NMOS transistor M14R serves as a second output terminal, the source of the fifteenth right PMOS transistor M15R is connected to the drain of the sixteenth right PMOS transistor M16R, and the gate of the sixteenth right PMOS transistor M16R serves as a third input terminal.
The source of the fourteenth right NMOS transistor M14R is connected to the drain of the thirteenth right NMOS transistor M13R, the first right resistor R10 is connected in parallel to the gate and the source of the thirteenth right NMOS transistor M13R, the anode of the right diode group D15 is used as the second input end, and the cathode is connected to the gate of the thirteenth right NMOS transistor M13R through the first right resistor R9.
The common source of the left sixteen PMOS tube M16L and the right sixteen PMOS tube M16R is used as a positive power supply terminal, and the common source of the left thirteen NMOS tube M13L and the right thirteen NMOS tube M13R is used as a negative power supply terminal.
The first inverter 101 and the second inverter 101 are powered by 2.5V, the positive power supply end of the positive voltage domain voltage conversion module 102 is powered by 3.3V, the negative power supply end is grounded, the positive power supply end of the negative voltage domain voltage conversion module 103 is grounded, the negative power supply end is powered by-3.3V, the positive power supply end of the first output stage 104 is powered by 3.3V, the negative power supply end is powered by-3.3V, the positive power supply end of the second output stage 105 is grounded, and the negative power supply end is powered by-3.3V.
The gates of the left twenty-second MOS transistor M2L, the left four MOS transistor M4L, the left five MOS transistor M5L, the left twenty-third MOS transistor M23L, the right two MOS transistor M2R, the right four MOS transistor M4R, the right five MOS transistor M5R and the right twenty-third MOS transistor M23R are powered by 1.65V, and the gates of the left eight MOS transistor M8L, the left ten MOS transistor M10L, the left eleventh MOS transistor M11L, the left fourteen MOS transistor M14L, the left fifteen MOS transistor M15L, the left eighteen MOS transistor M18L, the right eight MOS transistor M8R, the right ten MOS transistor M10R, the right eleventh MOS transistor M11R, the right fourteen MOS transistor M14R, the right fifteen MOS transistor M15R and the right eighteen MOS transistor M18R are powered by-1.65V.
The resistors R1, R2, R3 and R4 are 20 kilo-ohms, R5 is 25 kilo-ohms, R6 is 33 kilo-ohms, R7 and R8 are 20 kilo-ohms, R9 is 23 kilo-ohms and R10 is 33 kilo-ohms, wherein R5/R6 is 25/33, R9/R10 is 23/33, and the diode group D15 adopts 5 0.7V diodes which are connected in series.
The high and low levels of the control signal are respectively input to be 0/2.5V, the first phase inverter 101 outputs 2.5V/0, the second phase inverter outputs 0/2.5V, each MOS tube is correspondingly switched on or switched off, and each node presents the high and low levels.
The node levels of the positive voltage domain voltage conversion module 102 are shown in fig. 7:
the first input end is 2.5V/0, the common gate of M1L and M3L is 1.25V/0, and the source of M2L and M4L is 0/1.65V; the drain electrode of M2L is 0/3.3V, the grid electrode of M6R is 1.65V/3.3V, and the drain electrode is 3.3V/1.65V; the fifth output end is 0/3.3V, the third output end is 0/1.65V, and the second output end is 1.65V/3.3V.
The second input end is 0/2.5V, the common gate of M1R and M3R is 0/1.25V, and the source of M2R and M4R is 1.65V/0; the drain electrode of M2R is 3.3V/0, the grid electrode of M6L is 3.3V/1.65V, and the drain electrode is 1.65V/3.3V; the sixth output end is 3.3V/0, the first output end is 3.3V/1.65V, and the fourth output end is 1.65V/0.
The voltage difference between any two ports of each MOS tube is less than or equal to 2.5V and is in a voltage range of safe operation.
The node levels of the negative voltage domain voltage conversion module 103 are shown in fig. 8:
the first input terminal is 2.5V/0, the common gate 0/-1.42V of M7L and M9R, and the source-1.65V/0 of M8L and M10R; drain-3.3V/0 of M8L, gate-3.3V/-1.65V of M12L, drain-1.65V/-3.3V; the fifth output terminal is-3.3V/0, the first output terminal is-1.65V/0, and the fourth output terminal is-3.3V/-1.65V.
The second input terminal is 0/2.5V, the common gate of M7R and M9L is-1.42V/0, and the source of M8R and M10L is 0/-1.65V; drain 0/-3.3V of M8R, gate-1.65V/-3.3V of M12R, drain-3.3V/-1.65V; sixth output 0/-3.3V, third output-1.65V/-3.3V, second output 0/-1.65V.
The voltage difference between any two ports of each MOS tube is less than or equal to 2.5V and is in a voltage range of safe operation.
The node levels of the first output stage 104 are shown in fig. 9:
the first input terminal is 3.3V/1.65V, the second input terminal is 1.65V/3.3V, the third input terminal is 0/1.65V, the fourth input terminal is 1.65V/0, the fifth input terminal is-1.65V/1.65V, the sixth input terminal is 1.65V/-1.65V, the seventh input terminal is-1.65V/0, the eighth input terminal is 0/-1.65V, the ninth input terminal is-1.65V/-3.3V, and the tenth input terminal is-3.3V/-1.65V.
The first output terminal is 3.3V/-3V, and the second output terminal is-3V/3.3V.
The voltage difference between any two ports of each MOS tube is less than or equal to 2.5V and is in a voltage range of safe operation.
The node levels of the second output stage 105 are shown in fig. 10:
the first input terminal is 3.3V/-3V, the second input terminal is-3V/3.3V, the third input terminal is 0/-1.65V, and the fourth input terminal is-1.65V/0.
The first output terminal is 0/-3V, and the second output terminal is-3V/0.
When the input signal rises from-3V to 0.5V, the diode group is not conducted, and the grid level V2L of M13L or the grid level V2R of M13R keeps-3V; when the input signal exceeds 0.5V, the diode group is turned on, the voltage drop is 0.7V multiplied by 5, and the gate level V2L of M13L and the gate level V2R of M13R are the input signal minus 3.5V.
The waveform of the port level of the switching MOS transistor not adopting the diode group D15 is shown in fig. 11, and the waveform of the port level of the switching MOS transistor adopting the diode group D15 is shown in fig. 12, and the diode group D15 solves the timing problem of the gate and body port control of the switching MOS transistor, and prevents the breakdown of the MOS transistor due to an excessively large voltage difference between the gate and the body port.
The voltage difference between any two ports of each MOS tube is less than or equal to 2.5V and is in a voltage range of safe operation.
The above-described embodiments are not intended to limit the present invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention are included in the scope of the present invention.

Claims (9)

1. A positive and negative voltage control circuit based on MOS pipe, characterized by that, includes: the positive voltage low level signal is input, positive and negative voltage power supply is adopted, the signal level value is improved, and the positive and negative voltage high level signal is output; the input end of a first phase inverter is used as the input end of the circuit, the output end of the first phase inverter is connected with the input end of a second phase inverter, the first input end of a positive voltage domain voltage conversion module and the first input end of a negative voltage domain voltage conversion module, the output end of the second phase inverter is connected with the second input end of the positive voltage domain voltage conversion module and the second input end of the negative voltage domain voltage conversion module, the first, second, third and fourth output ends of the positive voltage domain voltage conversion module are connected with the first, second, third and fourth input ends of a first output stage, the first, second, third and fourth output ends of the negative voltage domain voltage conversion module are connected with the seventh, eighth, ninth and tenth input ends of the first output stage, the fifth output end of the positive voltage domain voltage conversion module and the fifth output end of the negative voltage domain voltage conversion module are connected in series through two resistors R1, and the middle tap is connected with the fifth input end of the first output stage, the sixth output end of the positive voltage domain voltage conversion module and the sixth output end of the negative voltage domain voltage conversion module are connected in series through another two resistors R1, a middle tap is connected with the sixth input end of the first output stage, the first output end and the second output end of the first output stage are used as the first output end and the second output end of the circuit and are connected with the first input end and the second input end of the second output stage, the first output end and the second output end of the negative voltage domain voltage conversion module are connected with the fourth input end and the third input end of the second output stage, and the first output end and the second output end of the second output stage are used as the third output end and the fourth output end of the circuit.
2. The MOS transistor-based positive-negative voltage control circuit of claim 1, wherein the positive voltage domain voltage transformation module comprises: eight resistors R4, four resistors R3, four resistors R2, four PMOS tubes and eight NMOS tubes, which adopt bilateral symmetry design, input two paths of signals and output six paths of signals; the left first resistor R4, the left second resistor R4, the left third resistor R4 and the left fourth resistor R4 are connected in series, the middle tap of the left first resistor R4 and the middle tap of the left second resistor R4 are used as second output ends, the middle tap of the left third resistor R4 and the middle tap of the left fourth resistor R4 are used as third output ends, the left first resistor R4 is connected with the source electrode of a left six-channel metal oxide semiconductor (PMOS) transistor, and the left fourth resistor R4 is connected with the source electrode of a left three-channel metal oxide semiconductor (NMOS) transistor; the common drain of the left four NMOS tubes and the left five PMOS tube is connected with a middle tap of a left two resistor R4 and a left three resistor R4 to serve as a fifth output end, and the source electrode of the left four NMOS tubes is connected with the drain electrode of the left three NMOS tubes; the source electrode of the left second NMOS tube is connected with the drain electrode of the left first NMOS tube, the left first NMOS tube and the left third NMOS tube are connected in a common grid and common source mode, the common grid is used as a first input end through a left first resistor R2, and a left second resistor R2 is connected in parallel with the common grid and the common source; the right first resistor R4, the right second resistor R4, the right third resistor R4 and the right fourth resistor R4 are connected in series, the middle tap of the right first resistor R4 and the middle tap of the right second resistor R4 are used as a first output end, the middle tap of the right third resistor R4 and the middle tap of the right fourth resistor R4 are used as a fourth output end, the right first resistor R4 is connected with the source electrode of a right six PMOS tube, and the right fourth resistor R4 is connected with the source electrode of a right three NMOS tube; the common drain of the right four NMOS tubes and the right five PMOS tube is connected with a middle tap of a right two resistor R4 and a right three resistor R4 to serve as a sixth output end, and the source electrode of the right four NMOS tube is connected with the drain electrode of the right three NMOS tube; the source electrode of the right second NMOS tube is connected with the drain electrode of the right first NMOS tube, the right first NMOS tube and the right third NMOS tube are connected in a common grid and common source mode, the common grid is used as a second input end through a right first resistor R2, and a right second resistor R2 is connected in parallel with the common grid and the common source; the left resistor R3 is connected with the grid and the source of the right six PMOS tube in parallel, the right resistor R3 is connected with the grid and the source of the left six PMOS tube in parallel, the drain of the left two NMOS tubes is connected with the grid of the right six PMOS tube through the left two resistor R3, and the drain of the right two NMOS tubes is connected with the grid of the left six PMOS tube through the right two resistor R3; the left six PMOS tube and the right six PMOS tube share a common source as a positive power supply end, and the left three NMOS tube and the right three NMOS tube share a common source as a negative power supply end.
3. The MOS transistor-based positive-negative voltage control circuit according to claim 2, wherein the negative voltage domain voltage transformation module comprises: eight resistors R8, four resistors R7, two resistors R5, two resistors R6, four NMOS tubes and eight PMOS tubes are designed in a bilateral symmetry mode, two paths of signals are input, and six paths of signals are output; the left first resistor R8, the left second resistor R8, the left third resistor R8 and the left fourth resistor R8 are connected in series, the middle tap of the left first resistor R8 and the middle tap of the left second resistor R8 are used as second output ends, the middle tap of the left third resistor R8 and the middle tap of the left fourth resistor R8 are used as third output ends, the left first resistor R8 is connected with the source electrode of a left nine PMOS tube, and the left fourth resistor R8 is connected with the source electrode of a left twelve NMOS tube; the common drain of the left ten PMOS tube and the left eleven NMOS tube is connected with a middle tap of a left two-resistor R8 and a left three-resistor R8 to serve as a sixth output end, the source electrode of the left ten PMOS tube is connected with the drain electrode of a left nine PMOS tube, and the source electrode of the left eleven NMOS tube is connected with the drain electrode of a left twelve NMOS tube; the left second resistor R7 is connected with the grid and the source of the left twelve NMOS transistors in parallel, the grid is connected with the drain of the left eight PMOS transistor through the left first resistor R7, the source is connected with the grid of the left seven PMOS transistor through the left first resistor R6, and the source of the left eight PMOS transistor is connected with the drain of the left seven PMOS transistor; the right first resistor R8, the right second resistor R8, the right third resistor R8 and the right fourth resistor R8 are connected in series, the middle tap of the right first resistor R8 and the middle tap of the right second resistor R8 are used as a first output end, the middle tap of the right third resistor R8 and the middle tap of the right fourth resistor R8 are used as a fourth output end, the right first resistor R8 is connected with the source electrode of a right nine PMOS tube, and the right fourth resistor R8 is connected with the source electrode of a right twelve NMOS tube; a common drain of the right ten PMOS tube and the right eleven NMOS tube is connected with a middle tap of a right two-resistor R8 and a right three-resistor R8 to serve as a fifth output end, a source electrode of the right ten PMOS tube is connected with a drain electrode of a right nine PMOS tube, and a source electrode of the right eleven NMOS tube is connected with a drain electrode of a right twelve NMOS tube; the right second resistor R7 is connected in parallel with the grid and the source of the twelve right NMOS tubes, the grid is connected with the drain of the eight right PMOS tube through the right first resistor R7, the source is connected with the grid of the seven right PMOS tube through the right first resistor R6, and the source of the eight right PMOS tube is connected with the drain of the seven right PMOS tube; the left seven PMOS tube and the right nine PMOS tube are connected in a common grid and common source mode, the common grid is used as a first input end through a left resistor R5, and the common source is connected with the source electrode of the left nine PMOS tube; the right seven PMOS tube and the left nine PMOS tube are connected in a common grid and common source mode, the common grid is used as a second input end through a right resistor R5, and the common source is connected with the source electrode of the right nine PMOS tube; the common source of the left seven PMOS tube and the right seven PMOS tube is used as a positive power supply end, and the common source of the left twelve NMOS tube and the right twelve NMOS tube is used as a negative power supply end.
4. The MOS transistor-based positive-negative voltage control circuit of claim 3, wherein the first output stage comprises: eight PMOS tubes and eight NMOS tubes are designed in a bilateral symmetry mode; a common gate of the left twenty NMOS tube and the left twenty-one PMOS tube is used as a fifth input end, and a common drain is used as a second output end; the source electrode of the left twenty NMOS tube is connected with the drain electrode of the left nineteen NMOS tube, and the source electrode of the left twenty-one PMOS tube is connected with the drain electrode of the left twenty-two PMOS tube; the grid electrode of the nineteen left NMOS tube is used as a seventh input end, and the source electrode is connected with the drain electrode of the eighteen left NMOS tube; the grid electrode of the seventeen left NMOS tube is used as a ninth input end, and the drain electrode of the seventeen left NMOS tube is connected with the source electrode of the eighteen left NMOS tube; the grid electrode of the left twenty-two PMOS tube is used as a third input end, and the source electrode of the left twenty-three PMOS tube is connected with the drain electrode of the left twenty-three PMOS tube; the grid electrode of the left twenty-four PMOS tube is used as a first input end, and the drain electrode of the left twenty-four PMOS tube is connected with the source electrode of the left twenty-three PMOS tube; the common gate of the twenty-right NMOS tube and the twenty-first PMOS tube is used as a sixth input end, and the common drain is used as a first output end; the source electrode of the twenty-right NMOS tube is connected with the drain electrode of the nineteen NMOS tube, and the source electrode of the twenty-first PMOS tube is connected with the drain electrode of the twenty-second PMOS tube; the grid electrode of the nineteen right NMOS tube is used as an eighth input end, and the source electrode is connected with the drain electrode of the eighteen right NMOS tube; the grid electrode of the seventeenth right NMOS tube is used as a tenth input end, and the drain electrode of the seventeenth right NMOS tube is connected with the source electrode of the eighteenth right NMOS tube; the grid electrode of the twenty-two right PMOS tube is used as a fourth input end, and the source electrode of the twenty-two right PMOS tube is connected with the drain electrode of the twenty-three right PMOS tube; the grid electrode of the right twenty-four PMOS tube is used as a second input end, and the drain electrode of the right twenty-four PMOS tube is connected with the source electrode of the right twenty-three PMOS tube; the common source of the left twenty-four PMOS tube and the right twenty-four PMOS tube is used as a positive power supply end, and the common source of the left seventeen NMOS tube and the right seventeen NMOS tube is used as a negative power supply end.
5. The MOS transistor-based positive-negative voltage control circuit according to claim 4, wherein the second output stage comprises: four PMOS tubes, four NMOS tubes, two resistors R9, two resistors R10 and two diode groups are designed in a bilateral symmetry mode; the common drain of the left fifteen PMOS tubes and the left fourteen NMOS tubes is used as a first output end, the source electrode of the left fifteen PMOS tubes is connected with the drain electrode of the left sixteen PMOS tubes, and the grid electrode of the left sixteen PMOS tubes is used as a fourth input end; the source electrode of the left fourteen NMOS tube is connected with the drain electrode of the left thirteen NMOS tube, the left resistor R10 is connected with the grid electrode and the source electrode of the left thirteen NMOS tube in parallel, the anode of the left diode group is used as a first input end, and the cathode of the left diode group is connected with the grid electrode of the left thirteen NMOS tube through the left resistor R9; common leakage of the fifteenth right PMOS tube and the fourteenth right NMOS tube is used as a second output end, a source electrode of the fifteenth right PMOS tube is connected with a drain electrode of the sixteenth right PMOS tube, and a grid electrode of the sixteenth right PMOS tube is used as a third input end; the source electrode of the fourteen right NMOS tube is connected with the drain electrode of the thirteen right NMOS tube, the right resistor R10 is connected with the grid electrode and the source electrode of the thirteen right NMOS tube in parallel, the anode of the right diode group is used as a second input end, and the cathode of the right diode group is connected with the grid electrode of the thirteen right NMOS tube through the right resistor R9; and the common source of the lefthand sixteen PMOS tube and the righthand sixteen PMOS tube is used as a positive power supply end, and the common source of the lefthand thirteen NMOS tube and the righthand thirteen NMOS tube is used as a negative power supply end.
6. The MOS tube-based positive and negative voltage control circuit according to claim 5, wherein the MOS tube adopts a 2.5V process; the resistors R1, R2, R3, R4, R5, R6, R7, R8, R9 and R10 adopt thousands of ohms, wherein R5/R6 is 25/33, and R9/R10 is 23/33; the left diode group and the right diode group are respectively connected in series by 5 0.7V diodes.
7. The MOS transistor-based positive and negative voltage control circuit according to claim 6, wherein the first and second inverters are powered by 2.5V; the positive power supply end of the positive voltage domain voltage conversion module adopts 3.3V power supply, and the negative power supply end is grounded; the positive power supply end of the negative voltage domain voltage conversion module is grounded, and the negative power supply end adopts-3.3V power supply; in the first output stage, a positive power supply end adopts 3.3V power supply, and a negative power supply end adopts-3.3V power supply; in the second output stage, the positive power supply end is grounded, and the negative power supply end adopts-3.3V power supply; the gates of the left two, left four, left five, left twenty three, right two, right four, right five and right twenty three MOS tubes are powered by 1.65V; MOS tubes of the left eight, the left ten, the left eleven, the left fourteen, the left fifteen, the left eighteen, the right eight, the right ten, the right eleven, the right fourteen, the right fifteen and the right eighteen are powered by-1.65V at a grid; the pressure difference between any two ports of each MOS tube is less than or equal to 2.5V.
8. The MOS transistor-based positive and negative voltage control circuit of claim 7, wherein the high and low levels of the input signal are 0/2.5V, the first inverter 101 outputs 2.5V/0, and the second inverter outputs 0/2.5V; the positive voltage domain voltage conversion module has a first input end of 2.5V/0, a fifth output end of 0/3.3V, a third output end of 0/1.65V, a second output end of 1.65V/3.3V, a second input end of 0/2.5V, a sixth output end of 3.3V/0, a first output end of 3.3V/1.65V and a fourth output end of 1.65V/0; the negative voltage domain voltage conversion module comprises a first input end of 2.5V/0, a fifth output end of-3.3V/0, a first output end of-1.65V/0, a fourth output end of-3.3V/-1.65V, a second input end of 0/2.5V, a sixth output end of 0/-3.3V, a third output end of-1.65V/-3.3V and a second output end of 0/-1.65V; a first output stage having a first input terminal of 3.3V/1.65V, a second input terminal of 1.65V/3.3V, a third input terminal of 0/1.65V, a fourth input terminal of 1.65V/0, a fifth input terminal of-1.65V/1.65V, a sixth input terminal of 1.65V/-1.65V, a seventh input terminal of-1.65V/0, an eighth input terminal of 0/-1.65V, a ninth input terminal of-1.65V/-3.3V, a tenth input terminal of-3.3V/-1.65V, a first output terminal of 3.3V/-3V, and a second output terminal of-3V/3.3V; a second output stage, a first input terminal of 3.3V/-3V, a second input terminal of-3V/3.3V, a third input terminal of 0/-1.65V, a fourth input terminal of-1.65V/0, a first output terminal of 0/-3V, a second output terminal of-3V/0.
9. The MOS transistor-based positive-negative voltage control circuit of claim 8, wherein the second output stage comprises: the input signal rises from-3V to 0.5V, the diode group is not conducted, and the grid level of the MOS tube keeps-3V; when the input signal exceeds 0.5V, the diode group is conducted, the voltage drop is 0.7V multiplied by 5, and the grid level of the MOS transistor is the input signal minus 3.5V.
CN202011220948.XA 2020-11-05 2020-11-05 Positive and negative voltage control circuit based on MOS pipe Active CN112286276B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011220948.XA CN112286276B (en) 2020-11-05 2020-11-05 Positive and negative voltage control circuit based on MOS pipe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011220948.XA CN112286276B (en) 2020-11-05 2020-11-05 Positive and negative voltage control circuit based on MOS pipe

Publications (2)

Publication Number Publication Date
CN112286276A CN112286276A (en) 2021-01-29
CN112286276B true CN112286276B (en) 2022-04-05

Family

ID=74352000

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011220948.XA Active CN112286276B (en) 2020-11-05 2020-11-05 Positive and negative voltage control circuit based on MOS pipe

Country Status (1)

Country Link
CN (1) CN112286276B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007145752A2 (en) * 2006-06-06 2007-12-21 Skyworks Solutions, Inc. Voltage up-conversion circuit using low voltage transistors
CN102545903A (en) * 2010-12-23 2012-07-04 上海贝岭股份有限公司 Digital to analog conversion switch circuit
CN103812500A (en) * 2014-03-07 2014-05-21 上海华虹宏力半导体制造有限公司 Level conversion circuit
CN104796171A (en) * 2015-03-25 2015-07-22 广州钧衡微电子科技有限公司 Control circuit applied to SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) radiofrequency switches
CN108616269A (en) * 2018-07-27 2018-10-02 无锡安趋电子有限公司 A kind of downlink level shift circuit of low-work voltage
CN210041792U (en) * 2019-07-05 2020-02-07 中国电子科技集团公司第二十四研究所 Positive-voltage-to-negative-voltage logic circuit based on GaAs HEMT technology

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI330922B (en) * 2006-12-06 2010-09-21 Princeton Technology Corp Boost circuit and level shifter
TWI359340B (en) * 2008-03-13 2012-03-01 Via Tech Inc Level shifters
CN103856207A (en) * 2012-12-06 2014-06-11 艾尔瓦特集成电路科技（天津）有限公司 Electrical level switching circuit and electrical level switching method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007145752A2 (en) * 2006-06-06 2007-12-21 Skyworks Solutions, Inc. Voltage up-conversion circuit using low voltage transistors
CN102545903A (en) * 2010-12-23 2012-07-04 上海贝岭股份有限公司 Digital to analog conversion switch circuit
CN103812500A (en) * 2014-03-07 2014-05-21 上海华虹宏力半导体制造有限公司 Level conversion circuit
CN104796171A (en) * 2015-03-25 2015-07-22 广州钧衡微电子科技有限公司 Control circuit applied to SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) radiofrequency switches
CN108616269A (en) * 2018-07-27 2018-10-02 无锡安趋电子有限公司 A kind of downlink level shift circuit of low-work voltage
CN210041792U (en) * 2019-07-05 2020-02-07 中国电子科技集团公司第二十四研究所 Positive-voltage-to-negative-voltage logic circuit based on GaAs HEMT technology

Also Published As

Publication number Publication date
CN112286276A (en) 2021-01-29

Similar Documents

Publication Publication Date Title
KR101787758B1 (en) Level shifter
CN110149050B (en) Level transfer circuit and chip based on DMOS tube
CN115567049A (en) Level shift circuit and high-voltage analog switch
US10164637B2 (en) Level shifter for voltage conversion
CN209823645U (en) Level shift circuit and chip based on DMOS pipe
CN112286276B (en) Positive and negative voltage control circuit based on MOS pipe
CN103269217A (en) Output buffer
CN210517788U (en) Overvoltage protection circuit
CN109391258A (en) Level displacement circuit based on low-voltage tube
WO2023115888A1 (en) Logic process-based level translation circuit of flash-based fpga
CN112600547B (en) Wide-range input/output interface circuit
CN114142842A (en) Positive and negative pressure bidirectional switch circuit
CN116633331B (en) Switching circuit capable of switching positive and negative voltage complementary output
CN208739097U (en) Level displacement circuit based on low-voltage tube
CN110545098B (en) CMOS level converter, operation method, device and equipment
CN220798250U (en) Level conversion circuit for radio frequency switch
CN214626959U (en) Negative-pressure level conversion unit
CN112491408B (en) Level conversion circuit
CN213426122U (en) Novel power MOS module structure
CN210518249U (en) Novel output switch
CN117200776B (en) Depletion type switch circuit architecture for improving unidirectional or bidirectional isolation signals
CN212305144U (en) Level conversion circuit with ultra-wide voltage range
CN209767493U (en) Output buffer circuit
CN113054992B (en) Reconfigurable dynamic logic cell
CN219740350U (en) Novel high-speed low-power consumption level conversion circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant