CN115567049A - Level shift circuit and high-voltage analog switch - Google Patents

Level shift circuit and high-voltage analog switch Download PDF

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Publication number
CN115567049A
CN115567049A CN202211367082.4A CN202211367082A CN115567049A CN 115567049 A CN115567049 A CN 115567049A CN 202211367082 A CN202211367082 A CN 202211367082A CN 115567049 A CN115567049 A CN 115567049A
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China
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voltage
low
withstand voltage
level shift
low withstand
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Inventor
来新泉
丁晨涛
汤彭钰
张伟
周宏哲
李继生
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Xi'an Shuimuxinbang Semiconductor Design Co ltd
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Xi'an Shuimuxinbang Semiconductor Design Co ltd
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Priority to CN202211367082.4A priority Critical patent/CN115567049A/en
Publication of CN115567049A publication Critical patent/CN115567049A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

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  • Computer Hardware Design (AREA)
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  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a level shift circuit and a high-voltage analog switch, wherein the level shift circuit comprises an upper level shift circuit and a lower level shift circuit, the upper level shift circuit comprises a first level shift unit, the first level shift unit comprises a first input end, the first input end is used for accessing a low-voltage logic signal of a low-voltage domain, and the first level shift unit is used for converting the low-voltage logic signal of the low-voltage domain into a high-voltage control signal of the high-voltage domain; the lower level shift circuit comprises a second level shift unit, the second level shift unit comprises a second input end, the second input end is used for accessing a low-voltage logic signal of a low-voltage domain, and the second level shift unit is used for converting the low-voltage logic signal of the low-voltage domain into a negative-voltage control signal of a negative-voltage domain; the first input end and the second input end are in common. The invention adopts the same input through the upper level shift circuit and the lower level shift circuit, realizes the cooperative work of high-voltage output and negative-voltage output, and provides a proper control signal for the high-voltage analog switch.

Description

Level shift circuit and high-voltage analog switch
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a level shift circuit and a high-voltage analog switch.
Background
The high-voltage analog switch chip consists of a low-voltage logic circuit, a level shift circuit, a switch driving circuit and an analog switch, and can work under the voltage of up to 300V. The level shift circuit has the function of connecting the low-voltage logic circuit and the switch driving circuit, can convert the low-voltage logic signal into a high-voltage driving control signal, and is an important component of the high-voltage analog switch. The high voltage resistance, low power consumption, high driving capability and high anti-interference capability of the level shift circuit are all important to the performance influence of the high-voltage analog switch.
A level shift circuit of a conventional cross-coupled structure, which can convert a low voltage logic signal of 0-L (low voltage logic high level) V into a high voltage control signal of 0-H (high voltage logic high level) V, is shown in fig. 1, and can output only a signal of 0 or HV although the static power consumption is very small. In the application of the high-voltage analog switch chip, although the mainstream commercial DMOS can realize higher drain-source breakdown voltage, the gate oxide layer of the mainstream commercial DMOS is thinner and cannot bear higher gate-source voltage, which means that the traditional cross-coupled level shift circuit cannot meet the use requirement of the high-voltage analog switch chip.
In addition, the high voltage analog switch chip usually operates in a wide voltage range of 0-300V, and in order to ensure the operating range, the switch driving circuit is generally wider than 0-300V, which means that the driving circuit operates in a negative voltage. Under the condition, the original low-voltage logic signal can not be combined with the high-voltage control signal to realize switching control, and the logic control signal of negative pressure is matched with the high-voltage control signal to control the switching process.
Disclosure of Invention
The embodiment of the invention provides a level shift circuit and a high-voltage analog switch, and aims to solve the problem that when a driving circuit of an existing high-voltage analog switch chip works under negative voltage, a low-voltage logic signal provided by the level shift circuit cannot be combined with a high-voltage control signal to realize switch control.
In a first aspect, the present invention provides a level shift circuit, including: the up-level shift circuit comprises a first level shift unit and a first output unit, wherein the first level shift unit comprises a first input end and a first output end, the first input end is used for accessing a low-voltage logic signal in a low-voltage domain, the first output end is connected with the first output unit, and the first level shift unit is used for converting the low-voltage logic signal in the low-voltage domain into a high-voltage control signal in a high-voltage domain; the lower level shift circuit comprises a second level shift unit and a second output unit, wherein the second level shift unit comprises a second input end and a second output end, the second input end is used for accessing a low-voltage logic signal of a low-voltage domain, the second output end is connected with the second output unit, and the second level shift unit is used for converting the low-voltage logic signal of the low-voltage domain into a negative-voltage control signal of a negative-voltage domain; wherein the first input terminal is common to the second input terminal.
In the level shift circuit provided by the present invention, each of the first level shift unit and the second level shift unit includes a first switch module, a second switch module and a signal conversion module, the first switch module is connected to the second switch module, the first switch module and the second switch module are connected to the signal conversion module, and the signal conversion module is further connected to a first voltage power supply and a second voltage power supply; the on-off of the first switch module and the second switch module controls the signal conversion module to output a first voltage control signal or a second voltage control signal, and the first voltage is greater than the second voltage.
In the level shift circuit provided by the present invention, the signal conversion module of the first level shift unit includes a first high withstand voltage PMOS transistor, a second high withstand voltage PMOS transistor, a third low withstand voltage PMOS transistor, and a fourth low withstand voltage PMOS transistor; the drain electrode of the first high voltage-resistant PMOS tube is connected with the first switch module, the grid electrode of the first high voltage-resistant PMOS tube is connected with the grid electrode of the second high voltage-resistant PMOS tube and the second voltage power supply, and the source electrode of the first high voltage-resistant PMOS tube is connected with the drain electrode of the third low voltage-resistant PMOS tube, the grid electrode of the fourth low voltage-resistant PMOS tube and the first output end; the drain electrode of the second high voltage-resistant PMOS tube is connected with the second switch module, and the source electrode of the second high voltage-resistant PMOS tube is connected with the drain electrode of the fourth low voltage-resistant PMOS tube and the grid electrode of the third low voltage-resistant PMOS tube; and the source electrode of the third low voltage-withstanding PMOS tube is connected with the source electrode of the fourth low voltage-withstanding PMOS tube and the first voltage power supply.
In the level shift circuit provided by the present invention, the signal conversion module of the first level shift unit further includes a first diode, a second diode, a third diode, and a fourth diode; the anode of the first diode is connected with the grid electrode of the first high voltage-resistant PMOS tube, and the cathode of the first diode is connected with the source electrode of the first high voltage-resistant PMOS tube and the anode of the third diode; the anode of the second diode is connected with the grid electrode of the second high voltage-resistant PMOS tube, and the cathode of the second diode is connected with the source electrode of the second high voltage-resistant PMOS tube and the anode of the fourth diode; the anode of the third diode is connected with the drain electrode of the third low voltage-withstanding PMOS tube, and the cathode of the third diode is connected with the source electrode of the third low voltage-withstanding PMOS tube; and the anode of the fourth diode is connected with the drain electrode of the fourth low voltage-withstanding PMOS tube, and the cathode of the fourth diode is connected with the source electrode of the fourth low voltage-withstanding PMOS tube.
In the level shift circuit provided by the present invention, the first switch module of the first level shift unit includes a first low withstand voltage NMOS transistor, a first low withstand voltage PMOS transistor, and a first high withstand voltage NMOS transistor, and the second switch module of the first level shift unit includes a second low withstand voltage NMOS transistor, a second low withstand voltage PMOS transistor, and a second high withstand voltage NMOS transistor; the source electrode of the first low withstand voltage NMOS tube is grounded, the drain electrode of the first low withstand voltage NMOS tube is connected with the drain electrode of the first low withstand voltage PMOS tube, the grid electrode of the first high withstand voltage NMOS tube, the grid electrodes of the two low withstand voltage NMOS tubes and the grid electrode of the second low withstand voltage PMOS tube, and the grid electrode of the first low withstand voltage NMOS tube is connected with the grid electrode of the first low withstand voltage PMOS tube and the first input end; the source electrode of the first low voltage-resistant PMOS tube is connected with an external power supply; the source electrode of the NMOS tube of the first high voltage-resistant tube is grounded, and the drain electrode of the NMOS tube of the first high voltage-resistant tube is connected with the drain electrode of the PMOS tube of the first high voltage-resistant tube; the source electrode of the second low withstand voltage NMOS tube is grounded, the drain electrode of the second low withstand voltage NMOS tube is connected with the drain electrode of the second low withstand voltage PMOS tube and the grid electrode of the second high withstand voltage NMOS tube, and the grid electrode of the second low withstand voltage NMOS tube is connected with the grid electrode of the second low withstand voltage NMOS tube; the source electrode of the second low voltage-resistant PMOS tube is connected with an external power supply; and the source electrode of the second high withstand voltage NMOS tube is grounded, and the drain electrode of the second high withstand voltage NMOS tube is connected with the drain electrode of the second high withstand voltage PMOS tube.
In the level shift circuit provided by the present invention, the signal conversion module of the second level shift unit includes an eighth low withstand voltage NMOS transistor, a ninth low withstand voltage NMOS transistor, a tenth low withstand voltage NMOS transistor, and an eleventh low withstand voltage NMOS transistor; the drain electrode of the eighth low withstand voltage NMOS transistor is connected with the first switch module, the gate electrode of the eighth low withstand voltage NMOS transistor is connected with the gate electrode of the ninth low withstand voltage NMOS transistor and the first voltage power supply, and the source electrode of the eighth low withstand voltage NMOS transistor is connected with the drain electrode of the tenth low withstand voltage NMOS transistor, the gate electrode of the eleventh low withstand voltage NMOS transistor and the second output end; the drain electrode of the ninth low withstand voltage NMOS tube is connected with the second switch module, and the source electrode of the ninth low withstand voltage NMOS tube is connected with the drain electrode of the eleventh low withstand voltage NMOS tube and the grid electrode of the tenth low withstand voltage NMOS tube; and the source electrode of the tenth low withstand voltage NMOS transistor is connected with the source electrode of the eleventh low withstand voltage NMOS transistor and the second voltage power supply.
In the level shift circuit provided by the present invention, the signal conversion module further includes a fifth diode and a sixth diode, an anode of the fifth diode is connected to a gate of the eighth low withstand voltage NMOS transistor, and a cathode of the fifth diode is connected to a source of the eighth low withstand voltage NMOS transistor; the anode of the sixth diode is connected with the grid electrode of the ninth low withstand voltage NMOS tube, and the cathode of the sixth diode is connected with the source electrode of the ninth low withstand voltage NMOS tube.
In the level shift circuit provided by the present invention, the first switch module of the second level shift unit includes a sixth low withstand voltage NMOS transistor, an eighth low withstand voltage PMOS transistor, and a tenth low withstand voltage PMOS transistor, and the second switch module of the second level shift unit includes a seventh low withstand voltage NMOS transistor, a ninth low withstand voltage PMOS transistor, and an eleventh low withstand voltage PMOS transistor; the source electrode of the sixth low withstand voltage NMOS tube is grounded, the drain electrode of the sixth low withstand voltage NMOS tube is connected with the drain electrode of the eighth low withstand voltage PMOS tube, the grid electrode of the tenth low withstand voltage PMOS tube, the grid electrode of the seventh low withstand voltage NMOS tube and the grid electrode of the ninth low withstand voltage NMOS tube, and the grid electrode of the sixth low withstand voltage NMOS tube is connected with the grid electrode of the eighth low withstand voltage PMOS tube and the second input end; the source electrode of the eighth low-voltage-withstanding PMOS tube is connected with an external power supply; a source electrode of the tenth low withstand voltage PMOS tube is connected with an external power supply, and a drain electrode of the tenth low withstand voltage PMOS tube is connected with a drain electrode of the eighth low withstand voltage NMOS tube; the source electrode of the seventh low withstand voltage NMOS tube is grounded, the drain electrode of the seventh low withstand voltage NMOS tube is connected with the drain electrode of the ninth low withstand voltage PMOS and the grid electrode of the eleventh low withstand voltage PMOS tube, and the grid electrode of the seventh low withstand voltage NMOS tube is connected with the grid electrode of the ninth low withstand voltage PMOS tube; the source electrode of the ninth low-voltage-withstanding PMOS tube is connected with an external power supply; and the source electrode of the eleventh low withstand voltage PMOS tube is connected with an external power supply, and the drain electrode of the eleventh low withstand voltage PMOS tube is connected with the drain electrode of the ninth low withstand voltage NMOS tube.
In the level shift circuit provided by the invention, the first output unit and/or the second output unit are/is a schmitt trigger.
In a second aspect, the present invention further provides a high voltage analog switch, which includes a low voltage logic circuit, a level shift circuit, a switch driving circuit and an analog switch, wherein the level shift circuit is electrically connected to the low voltage logic circuit and the switch driving circuit, the switch driving circuit is connected to the analog switch, and the level shift circuit is the level shift circuit according to the first aspect.
The invention provides a level shift circuit and a high-voltage analog switch, wherein the level shift circuit comprises an upper level shift circuit and a lower level shift circuit, the upper level shift circuit comprises a first level shift unit and a first output unit, the first level shift unit comprises a first input end and a first output end, the first input end is used for accessing a low-voltage logic signal of a low-voltage domain, the first output end is connected with the first output unit, and the first level shift unit is used for converting the low-voltage logic signal of the low-voltage domain into a high-voltage control signal of a high-voltage domain; the lower level shift circuit comprises a second level shift unit and a second output unit, the second level shift unit comprises a second input end and a second output end, the second input end is used for accessing a low-voltage logic signal of a low-voltage domain, the second output end is connected with the second output unit, and the second level shift unit is used for converting the low-voltage logic signal of the low-voltage domain into a negative-voltage control signal of a negative-voltage domain; wherein the first input terminal is common to the second input terminal. According to the invention, the upper level shift circuit and the lower level shift circuit are arranged, the upper level shift circuit and the lower level shift circuit adopt the same input, the upper level shift circuit converts a low-voltage logic signal of a low-voltage domain into a high-voltage control signal of a high-voltage domain, and the lower level shift circuit converts the low-voltage logic signal of the low-voltage domain into a negative-voltage control signal of a negative-voltage domain, so that the cooperative work of high-voltage output and negative-voltage output is realized, and a proper control signal is provided for the high-voltage analog switch.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a circuit diagram of a prior art level shifting circuit;
FIG. 2 is a diagram of a level shift circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a level shift circuit according to an embodiment of the present invention;
reference numerals:
10. a power-up level shifting circuit; 11. a first level shift unit; 12. a first output unit; 20. a lower level shift circuit; 21. a second level shift unit; 22. a second output unit; (111, 211), a first switch module; (112, 212), a second switch module; (113, 213) and a signal conversion module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the present invention, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc. refer to directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding and is in no way limiting. Further, in the drawings, structures that are similar or identical are denoted by the same reference numerals.
Referring to fig. 2-3, and in particular to fig. 2, an embodiment of the invention provides a level shift circuit, including: the upper level shifter circuit 10 includes a first level shifter unit 11 and a first output unit 12, the first level shifter unit 11 includes a first input end and a first output end, the first input end is used for accessing a low-voltage logic signal in a low-voltage domain, the first output end is connected to the first output unit 12, and the first level shifter unit 11 is used for converting the low-voltage logic signal in the low-voltage domain into a high-voltage control signal in a high-voltage domain; the lower level shift circuit 20 includes a second level shift unit 21 and a second output unit 22, where the second level shift unit 21 includes a second input end and a second output end, the second input end is used to access a low-voltage logic signal in a low-voltage domain, the second output end is connected to the second output unit 22, and the second level shift unit 21 is used to convert the low-voltage logic signal in the low-voltage domain into a negative-voltage control signal in a negative-voltage domain; wherein the first input terminal is common to the second input terminal.
By implementing the embodiment, the level shift circuit includes an upper level shift circuit 10 and a lower level shift circuit 20, the upper level shift circuit 10 can convert signals of low voltage domains 0 to VDD into signals of high voltage domains VPPL to VPPH, and the lower level shift circuit 20 can convert signals of low voltage domains 0 to VDD into signals of negative voltage domains VNN-0. The upper level shift circuit 10 and the lower level shift circuit 20 both adopt cross-coupling structures to realize low static power consumption, and a Schmitt trigger structure is added to an output stage to enhance the anti-interference capability of the circuits and the stability of output signals. The upper and lower level shift circuits 20 adopt the same input to realize the cooperative work of high-voltage output and negative-voltage output, and provide a proper control signal for the high-voltage analog switch.
Referring to fig. 3, in an embodiment, each of the first level shift unit 11 and the second level shift unit 21 includes a first switch module, a second switch module, and a signal conversion module, where the first switch module is connected to the second switch module, the first switch module and the second switch module are connected to the signal conversion module, and the signal conversion module is further connected to a first voltage power supply and a second voltage power supply; the on-off of the first switch module and the second switch module controls the signal conversion module to output a first voltage control signal or a second voltage control signal, and the first voltage is greater than the second voltage.
It should be noted that, in the present embodiment, the first level shift unit 11 and the second level shift unit 21 both adopt circuit structures with the same function, and the functions of the circuits of the two are the same, and the difference is only that the specific circuit structures of the two are slightly different, but no matter how the circuit structures are changed, as long as the circuit structures realize the functions mentioned in the present embodiment, the circuit structures fall into the protection scope of the present application.
Specifically, the signal conversion module is powered by a first voltage power supply and a second voltage power supply, the first voltage and the second voltage are provided for the signal conversion module through the first voltage power supply and the second voltage power supply, the first voltage is greater than the second voltage, namely the first voltage is at a high level, the second voltage is at a low level, the first switch module and the second switch module are used as a switching control switch to control the signal conversion module to perform signal conversion, the first switch module and the second switch module are switched on or off according to an input low-voltage logic signal, and then the signal conversion module is controlled to output a first voltage control signal or a second voltage control signal. For example, the first switch module is turned on, the second switch module is turned off, and the signal conversion module outputs a second voltage control signal; the first switch module is switched off, the second switch module is switched on, and the signal conversion module outputs a first voltage control signal. In the first level shift unit 11, the first voltage source connected to the signal conversion module 113 of the first level shift unit 11 is VPPH, and the second voltage source is VPPL, so that the low level output by the upper level shift circuit 10 is VPPL and the high level is VPPH. In the second level shift unit 21, the first voltage source connected to the signal conversion module 213 of the second level shift unit 21 is 0V, the second voltage source is VNN (negative voltage), and then the low level output by the lower level shifter is VNN and the high level is 0. By implementing the embodiment, the upper level shifter circuit 10 and the lower level shifter circuit 20 share the same input terminal, so that the input logic signals of low voltage 0-VDD can be provided with appropriate control signals for the high voltage analog switch by the upper level shifter circuit 10 outputting a low level VPPL and a high level VPPH, and by the lower level shifter outputting a low level VNN and a high level 0.
With reference to fig. 3, in an embodiment, the signal conversion module 113 of the first level shift unit 11 includes a first high voltage-withstanding PMOS transistor HP1, a second high voltage-withstanding PMOS transistor HP2, a third low voltage-withstanding PMOS transistor MP3, and a fourth low voltage-withstanding PMOS transistor MP4; the signal conversion module 113 of the first level shift unit 11 further includes a first diode VD1, a second diode VD2, a third diode VD3, and a fourth diode VD4; the first switch module 111 of the first level shift unit 11 includes a first low withstand voltage NMOS transistor MN1, a first low withstand voltage PMOS transistor MP1, and a first high withstand voltage NMOS transistor HN1, and the second switch module 112 of the first level shift unit 11 includes a second low withstand voltage NMOS transistor MN2, a second low withstand voltage PMOS transistor MP2, and a second high withstand voltage NMOS transistor HN2.
In this embodiment, a drain of the first high voltage-withstanding PMOS transistor HP1 is connected to the first switch module 111, a gate of the first high voltage-withstanding PMOS transistor HP1 is connected to a gate of the second high voltage-withstanding PMOS transistor HP2 and the second voltage power supply, and a source of the first high voltage-withstanding PMOS transistor HP1 is connected to a drain of the third low voltage-withstanding PMOS transistor MP3, a gate of the fourth low voltage-withstanding PMOS transistor MP4, and the first output terminal; the drain of the second high voltage-withstanding PMOS transistor HP2 is connected to the second switch module 112, and the source of the second high voltage-withstanding PMOS transistor HP2 is connected to the drain of the fourth low voltage-withstanding PMOS transistor MP4 and the gate of the third low voltage-withstanding PMOS transistor MP 3; the source electrode of the third low voltage-withstanding PMOS transistor MP3 is connected to the source electrode of the fourth low voltage-withstanding PMOS transistor MP4 and the first voltage power supply.
In this embodiment, the anode of the first diode VD1 is connected to the gate of the first high voltage-withstanding PMOS transistor HP1, and the cathode of the first diode VD1 is connected to the source of the first high voltage-withstanding PMOS transistor HP1 and the anode of the third diode VD 3; the anode of the second diode VD2 is connected to the gate of the second high voltage PMOS transistor HP2, and the cathode of the second diode VD2 is connected to the source of the second high voltage PMOS transistor HP2 and the anode of the fourth diode VD4; the anode of the third diode VD3 is connected to the drain of the third low withstand voltage PMOS transistor MP3, and the cathode of the third diode VD3 is connected to the source of the third low withstand voltage PMOS transistor MP 3; the anode of the fourth diode VD4 is connected to the drain of the fourth low withstand voltage PMOS transistor MP4, and the cathode of the fourth diode VD4 is connected to the source of the fourth low withstand voltage PMOS transistor MP 4.
In this embodiment, the source of the first low withstand voltage NMOS transistor MN1 is grounded, the drain of the first low withstand voltage NMOS transistor MN1 is connected to the drain of the first low withstand voltage PMOS transistor MP1, the gate of the first high withstand voltage NMOS transistor HN1, the gates of the two low withstand voltage NMOS transistors, and the gate of the second low withstand voltage PMOS transistor MP2, and the gate of the first low withstand voltage NMOS transistor MN1 is connected to the gate of the first low withstand voltage PMOS transistor MP1 and the first input terminal; the source electrode of the first low voltage-resistant PMOS pipe MP1 is connected with an external power supply; the source electrode of the first high voltage-resistant NMOS tube HN1 is grounded, and the drain electrode of the first high voltage-resistant NMOS tube HN1 is connected with the drain electrode of the first high voltage-resistant PMOS tube HP 1; the source electrode of the second low withstand voltage NMOS transistor MN2 is grounded, the drain electrode of the second low withstand voltage NMOS transistor MN2 is connected with the drain electrode of the second low withstand voltage PMOS transistor MP2 and the grid electrode of the second high withstand voltage NMOS transistor HN2, and the grid electrode of the second low withstand voltage NMOS transistor MN2 is connected with the grid electrode of the second low withstand voltage NMOS transistor MN 2; the source electrode of the second low voltage-resistant PMOS transistor MP2 is connected with an external power supply; the source of the second high withstand voltage NMOS transistor HN2 is grounded, and the drain of the second high withstand voltage NMOS transistor HN2 is connected to the drain of the second high withstand voltage PMOS transistor HP 2.
Specifically, the first level shift unit 11 includes an NMOS transistor MN1, a PMOS transistor MP1, an NMOS transistor HN1, an NMOS transistor MN2, a PMOS transistor MP2, an NMOS transistor HN2, a PMOS transistor HP1, a PMOS transistor HP2, a diode VD1, a PMOS transistor MP3, a diode VD2, a PMOS transistor MP4, a diode VD3, and a diode VD4. The source electrode of the MN1 is grounded, the drain electrode is connected with the drain electrode of the MP1, the grid electrode of the HN1, the grid electrode of the MN2 and the grid electrode of the MP2, and the grid electrodes are connected with the grid electrode of the MP1 to form an input end; the source electrode of HN1 is grounded, and the drain electrode is connected with the drain electrode of HP 1; the source electrode of the MN2 is grounded, and the drain electrode is connected with the drain electrode of the MP2 and the grid electrode of the HN 2; the source electrode of the MP2 is connected with a power supply VDD; the source electrode of HN2 is grounded, and the drain electrode is connected with the drain electrode of HP 2; the grid electrode of the HP2 is connected with the anode of the VD1, the anode of the VD2 and the grid electrode of the HP1 and is connected to a power supply VPPL, and the source electrode of the HP2 is connected with the cathode of the VD2, the drain electrode of the MP4, the anode of the VD4 and the grid electrode of the MP 3; the source electrode of the MP3 is connected with the source electrode of the MP4, the cathode of the VD3 and the cathode of the VD4 and is connected to a power supply VPPH; the source of the HP1 is connected to the cathode of the VD1, the drain of the MP3, the anode of the VD3, and the gate of the MP4, and is used as the output of the first level shift unit 11; the source of the MP5 is connected to a power supply VPPH, the gate is connected to the gate of the MP6, the gate of the MN3 and the gate of the MN4, and is used as an input of the first output unit 12, and the drain is connected to the source of the MP6 and the source of the MP 7; the source electrode of the MN4 is connected with a power supply VPPL, and the drain electrode of the MN4 is connected with the source electrode of the MN3 and the source electrode of the MN 5; the drain of the MP6 is connected to the drain of the MN3, the gate of the MP7, and the gate of the MN5, and is used as the output of the upper level shift circuit 10.
The HP1 and HP2 gates are connected with VPPL, the HP1 and HP2 source voltages can be limited, the MP3 and MP4 can be protected, and VDS and VGS of the MP3 and MP4 can not exceed device withstand voltage. Zener diodes VD1, VD2, VD3, and VD4 are added to the power up level shift circuit 10 to clamp the source voltages of HP1 and HP2, i.e., the output low level of the power up level shift circuit 10. HP1 with be node A between the MP3, HP2 with be node B between the MP4, VD1, VD2, VD3, VD4, VD5 and VD6 are zener diode, and wherein VD1 and VD3 clamp node A, VD2 and VD4 clamp node B.
With reference to fig. 3, in an embodiment, the signal conversion module 213 of the second level shift unit 21 includes an eighth low withstand voltage NMOS transistor MN8, a ninth low withstand voltage NMOS transistor MN9, a tenth low withstand voltage NMOS transistor MN10, and an eleventh low withstand voltage NMOS transistor MN11; the signal conversion module 213 of the second level shift unit 21 further includes a fifth diode VD5 and a sixth diode VD5; the first switch module 211 of the second level shift unit 21 includes a sixth low withstand voltage NMOS transistor MN6, an eighth low withstand voltage PMOS transistor MP8, and a tenth low withstand voltage PMOS transistor MP10, and the second switch module 212 of the second level shift unit 21 includes a seventh low withstand voltage NMOS transistor MN7, a ninth low withstand voltage PMOS transistor MP9, and an eleventh low withstand voltage PMOS transistor MP11.
In this embodiment, the drain of the eighth low withstand voltage NMOS transistor MN8 is connected to the first switch module 211, the gate of the eighth low withstand voltage NMOS transistor MN8 is connected to the gate of the ninth low withstand voltage NMOS transistor MN9 and the first voltage source, and the source of the eighth low withstand voltage NMOS transistor MN8 is connected to the drain of the tenth low withstand voltage NMOS transistor MN10, the gate of the eleventh low withstand voltage NMOS transistor MN11 and the second output terminal; the drain of the ninth low withstand voltage NMOS transistor MN9 is connected to the second switch module 212, and the source of the ninth low withstand voltage NMOS transistor MN9 is connected to the drain of the eleventh low withstand voltage NMOS transistor MN11 and the gate of the tenth low withstand voltage NMOS transistor MN 10; the source electrode of the tenth low withstand voltage NMOS transistor MN10 is connected to the source electrode of the eleventh low withstand voltage NMOS transistor MN11 and the second voltage supply.
In this embodiment, the anode of the fifth diode VD5 is connected to the gate of the eighth low withstand voltage NMOS transistor MN8, and the cathode of the fifth diode VD5 is connected to the source of the eighth low withstand voltage NMOS transistor MN 8; the anode of the sixth diode VD5 is connected to the gate of the ninth low withstand voltage NMOS transistor MN9, and the cathode of the sixth diode VD5 is connected to the source of the ninth low withstand voltage NMOS transistor MN 9.
In this embodiment, the source of the sixth low withstand voltage NMOS transistor MN6 is grounded, the drain of the sixth low withstand voltage NMOS transistor MN6 is connected to the drain of the eighth low withstand voltage PMOS transistor MP8, the gate of the tenth low withstand voltage PMOS transistor MP10, the gate of the seventh low withstand voltage NMOS transistor MN7, and the gate of the ninth low withstand voltage NMOS transistor MN9, and the gate of the sixth low withstand voltage NMOS transistor MN6 is connected to the gate of the eighth low withstand voltage PMOS transistor MP8 and the second input terminal; the source electrode of the eighth low-voltage-withstanding PMOS transistor MP8 is connected with an external power supply; a source electrode of the tenth low withstand voltage PMOS transistor MP10 is connected to an external power supply, and a drain electrode of the tenth low withstand voltage PMOS transistor MP10 is connected to a drain electrode of the eighth low withstand voltage NMOS transistor MN 8; the source electrode of the seventh low withstand voltage NMOS transistor MN7 is grounded, the drain electrode of the seventh low withstand voltage NMOS transistor MN7 is connected to the drain electrode of the ninth low withstand voltage PMOS and the gate electrode of the eleventh low withstand voltage PMOS transistor MP11, and the gate electrode of the seventh low withstand voltage NMOS transistor MN7 is connected to the gate electrode of the ninth low withstand voltage PMOS transistor MP 9; the source electrode of the ninth low-voltage-withstanding PMOS transistor MP9 is connected with an external power supply; the source electrode of the eleventh low withstand voltage PMOS transistor MP11 is connected to an external power supply, and the drain electrode of the eleventh low withstand voltage PMOS transistor MP11 is connected to the drain electrode of the ninth low withstand voltage NMOS transistor MN 9.
Specifically, the second level shift unit 21 includes a PMOS transistor MP8, an NMOS transistor MN6, a PMOS transistor MP9, a PMOS transistor MP10, an NMOS transistor MN7, a PMOS transistor MP11, an NMOS transistor MN8, an NMOS transistor MN9, a diode VD5, an NMOS transistor MN10, a diode VD6, and an NMOS transistor MN11. The source electrode of the MP8 is connected with a power supply VDD, the drain electrode is connected with the drain electrode of the MN6, the grid electrode of the MP10, the grid electrode of the MP9 and the grid electrode of the MN7, and the grid electrode is connected with the grid electrode of the MN6 to form an input end; the source electrode of the MN6 is grounded; the source electrode of the MP10 is connected with a power supply VDD, and the drain electrode is connected with the drain electrode of the MN 8; the source electrode of the MP9 is connected with a power supply VDD, and the drain electrode is connected with the drain electrode of the MN7 and the grid electrode of the MP 11; the source electrode of the MN7 is grounded; the source electrode of the MP11 is connected with a power supply VDD, and the drain electrode is connected with the drain electrode of the MN 9; the gate of the MN9 is connected to the anode of the VD5, the anode of the VD6, and the gate of the MN8, and is grounded, and the source is connected to the cathode of the VD6, the drain of the MN11, and the gate of the MP 10; the source electrode of the MN10 is connected with the source electrode of the MN11, the cathode of the VD3 and the cathode of the VD4 and is connected to a power supply VNN; the source of the MN8 is connected to the cathode of the VD5, the drain of the MN10, and the gate of the MN11, and is used as the output of the second level shift unit 21; the source of the MP12 is grounded, the gate is connected to the gate of the MP13, the gate of the MN12 and the gate of the MN13, and is used as the input of the first output unit 12, and the drain is connected to the source of the MP13 and the source of the MP 14; the source electrode of the MN13 is connected with a power supply VNN, and the drain electrode of the MN13 is connected with the source electrode of the MN12 and the source electrode of the MN 14; the drain of the MP6 is connected to the drain of the MN3, the gate of the MP7, and the gate of the MN5, and is used as the output of the lower level shift circuit 20.
The gates of the MN8 and the MN9 are grounded, so that the source voltages of the MN8 and the MN9 can be limited, the MMN10 and the MN11 can be protected, and the VDS and the VGS of the MN10 and the MN11 can not exceed the withstand voltage of the device. Zener diodes VD5 and VD6 are added to the lower level shift circuit 20 to clamp the source voltages of MN8 and MN9, i.e., the output high level of the lower level shift circuit 20. A node C is arranged between the MN8 and the MN10, and a node D is arranged between the MN9 and the MN11; VD5 and VD6 clamp node C and node D, respectively.
With continued reference to fig. 3, in one embodiment, the first output unit 12 and/or the second output unit 22 are schmitt triggers. Specifically, the first output unit 12 and the second output unit 22 are both of a schmitt trigger structure, and are configured to ensure stability of an output voltage and improve interference rejection capability of a circuit, the supply voltage of the first output unit 12 is VPPL and VPPH, and a low level output by the up-level shift circuit 10 can be stabilized at VPPL, and a high level is stabilized at VPPH; the second output unit 22 supplies power to VNN and GND, and can stabilize the low level output by the lower level shift circuit 20 at VNN and stabilize the high level at 0.
The first output unit 12 includes a PMOS transistor MP5, a PMOS transistor MP6, a PMOS transistor MP7, an NMOS transistor MN3, an NMOS transistor MN4, and an NMOS transistor MN5. The source of the MP5 is connected to a power supply VPPH, the gate is connected to the gate of the MP6, the gate of the MN3 and the gate of the MN4, and is used as an input of the first output unit 12, and the drain is connected to the source of the MP6 and the source of the MP 7; the source electrode of the MN4 is connected with a power supply VPPL, and the drain electrode of the MN4 is connected with the source electrode of the MN3 and the source electrode of the MN 5; the drain of the MP6 is connected to the drain of the MN3, the gate of the MP7, and the gate of the MN5, and is used as the output of the upper level shift circuit 10.
The second output unit 22 includes a PMOS transistor MP12, a PMOS transistor MP13, a PMOS transistor MP14, an NMOS transistor MN12, an NMOS transistor MN13, and an NMOS transistor MN14. The source of the MP12 is grounded, the gate is connected to the gate of the MP13, the gate of the MN12 and the gate of the MN13, and is used as the input of the first output unit 12, and the drain is connected to the source of the MP13 and the source of the MP 14; the source of the MN13 is connected with a power supply VNN, and the drain is connected with the source of the MN12 and the source of the MN 14; the drain of the MP6 is connected to the drain of the MN3, the gate of the MP7, and the gate of the MN5, and is used as the output of the lower level shift circuit 20.
It should be noted that the PMOS transistors MP3, MP4, MP5, MP6, MP7 and the NMOS transistors MN3, MN4, MN5 are low voltage devices, the VDS withstand voltage and the VGS withstand voltage thereof all satisfy the voltage requirement, the PMOS transistors MP10, MP11, MP12, MP13, MP14 and the NMOS transistors MN8, MN9, MN10, MN11, MN12, MN13, MN14 are low voltage devices, the VDS withstand voltage and the VGS withstand voltage thereof all satisfy the VNN power supply requirement, the NMOS transistors HN1, HN2 and the PMOS transistors HP1, HP2 are high voltage devices, the VDS withstand voltage thereof satisfies the VPPH power supply requirement, and the VGS withstand voltage satisfies the voltage requirement.
In order to ensure that two output signals can realize synchronous control, in a specific embodiment, the upper level shifter circuit and the lower level shifter circuit share the same input terminal, a low level output by the upper level shifter circuit is VPPL, a high level is VPPH, and a low level output by the lower level shifter is VNN, and a high level is 0.
Illustratively, when the input is high and low levels of 0-VDD, the first shift unit has the following working states:
1. when the input is low level 0, HN1 is turned on, HN2 is turned off, node A is pulled down to the vicinity at the moment, MP4 is enabled to be turned on, the voltage of node B is changed to VPPH, MP3 is enabled to be turned off and is in a high-impedance state, the voltage of node A is enabled to continuously drop due to device leakage current and parasitic capacitance charging and discharging, VD1 and VD3 prevent the voltage of node A from dropping and clamp the voltage of node A to the vicinity of VPPL, and the voltage of node A is ensured not to exceed the voltage-resistant range of MP3 and MP4;
2. when the input is high level VDD, HN2 is conducted, HN1 is turned off, node B is pulled down to the vicinity at the moment, MP3 is conducted, the voltage of node A is changed to VPPH, MP4 is turned off and is in a high-impedance state, the voltage of node B continues to drop due to device leakage current and parasitic capacitance charging and discharging, VD1 and VD3 prevent the voltage of node A from dropping and clamp the voltage of node A to the vicinity of VPPL, and the voltage of node B is ensured not to exceed the withstand voltage range of MP3 and MP 4.
The first output unit 12 and the second output unit 22 are both of a schmitt trigger structure, and due to the influence of device leakage current and parasitic capacitance, the first level shift unit 11 and the second level shift unit 21 have large ripples, the supply voltage of the first output unit 12 is VPPL and VPPH, and the low level output by the up-shift level circuit 10 can be stabilized at VPPL, and the high level is stabilized at VPPH.
Similarly, the power supply voltages of the second output unit 22 are VNN and GND, and the low level output by the lower level shift circuit 20 may be stabilized at VNN, and the high level may be stabilized at 0, which is not described herein.
The embodiment of the invention also provides a high-voltage analog switch, which comprises a low-voltage logic circuit, a level shift circuit, a switch driving circuit and an analog switch, wherein the level shift circuit is electrically connected with the low-voltage logic circuit and the switch driving circuit, the switch driving circuit is connected with the analog switch, and the level shift circuit is the level shift circuit in the embodiment. The level shift circuit has been described in detail in the above embodiments, and is not described herein again.
According to the embodiment of the invention, the high-voltage analog switch can convert the logic signal of 0-VDD into the two-way control signal of VPPL-VPPH and VNN-0 for output, the use requirement of the high-voltage analog switch can be met, only four VDS high-voltage resistant devices are needed in the circuit, and the process requirement is low. The whole structure of the invention adopts a cross coupling structure to ensure low power consumption, and the output stage adopts a Schmitt trigger structure to ensure the stability of output signals and simultaneously improve the anti-interference capability of the whole circuit.
In addition, in order to describe the signal control process of the level shift circuit clearly, the embodiment provides an example to illustrate. For illustrative purposes, in the following description, VDD is exemplified by 5V, VPPH is exemplified by 260V, VPPL is exemplified by 255V, and VNN is exemplified by-5V.
The application range of the invention is not limited to the exemplified voltage value, and as long as the used device meets the voltage application range, the method can be realized by the method described in the technical scheme of the invention; PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14 and NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12, MN13, MN14 are all low-voltage devices, and the VDS withstand voltage and the VGS withstand voltage thereof all meet the 5V requirement; the NMOS tubes HN1 and HN2 and the PMOS tubes HP1 and HP2 are high-voltage devices, VDS voltage withstanding of the high-voltage devices meets the requirement of 260V, and VGS voltage withstanding of the high-voltage devices meets the requirement of 5V.
The input signal is a logic signal of 0-5V, the output of the upper level shifter is a control signal of 255V-260V, and the output of the lower level shifter circuit 20 is a control signal of V-0.
The sources of the PMOS tubes MP3 and MP4 are connected with a 260V power supply voltage for determining the output high level of the power level shift circuit 10, and the gates of the PMOS tubes HP1 and HP2 are connected with a 255V power supply voltage for determining the output low level of the power level shift circuit 10, so that the source voltages of the HP1 and HP2 are limited, and the voltages of the terminals of the MP3 and MP4 are protected from exceeding the voltage withstanding range.
The source electrodes of the NMOS tubes MN10 and MN11 are connected with a-5V power supply voltage and used for determining the output low level of the lower level shift circuit 20, and the grid electrodes of the NMOS tubes MN8 and MN9 are grounded and used for determining the output high level of the lower level shift circuit 20, limiting the source electrode voltages of the MN8 and MN9 and protecting the voltage of each end point of the MN10 and the MN11 from exceeding the voltage-resistant range.
In actual operation, due to the effects of leakage current and charging and discharging of parasitic capacitors, the 255V voltage connected to the gates of HP1 and HP2 cannot limit the continuous decrease of the source voltages of HP1 and HP2, and the 0V voltage connected to the gates of MN8 and MN9 cannot limit the increase of the source voltages of MN8 and MN9, so zener diodes VD1, VD2, VD3, and VD4 are added to the upper level shift circuit 10 to clamp the source voltages of HP1 and HP2, i.e., the output low level of the upper level shift circuit 10, and zener diodes VD5 and VD6 are added to the lower level shift circuit 20 to clamp the source voltages of MN8 and MN9, i.e., the output high level of the lower level shift circuit 20;
when the input is high and low levels of 0-5V, the first level shift unit has the following working states:
1. when the input is low level 0, HN1 is conducted, HN2 is turned off, at the moment, the node A is pulled down to be near 255.7V, MP4 is conducted, the voltage of the node B is changed into 260V, MP3 is turned off and is in a high-impedance state, the voltage of the node A continues to drop due to the charge and discharge of device leakage current and parasitic capacitance, VD1 and VD3 prevent the voltage of the node A from dropping and clamp the node A to be near 255V, the voltage of the node A is ensured not to exceed the voltage-resistant range of the MP3 and MP4, at the moment, the grid source voltage of HP1 is equal, and small leakage current is realized;
2. when the input is high level 5V, HN2 is turned on, HN1 is turned off, at this time, node B is pulled down to be near 255.7, so that MP3 is turned on, the voltage of node a becomes 260V, so that MP4 is turned off, and is in a high-impedance state, the voltage of node B continues to drop due to device leakage current and parasitic capacitance charging and discharging, and VD1 and VD3 prevent the voltage of node B from dropping, clamp it to be near 255V, ensure that the voltage of node B does not exceed the withstand voltage range of MP3 and MP4, at this time, the gate-source voltage of HP2 is equal, and small leakage current is realized.
Schmitt trigger structures are added at the output ends of the upper level shift circuit 10 and the lower level shift circuit 20, so that the stability of output voltage is ensured, and the anti-interference capability of the circuits is improved. Due to the influence of device leakage current and parasitic capacitance, the first level shift unit 11 and the second level shift unit 21 have large ripples, the supply voltage of the first output unit 12 is 255V and 260V, and the low level output by the upper level shift circuit 10 can be stabilized at 255V, and the high level can be stabilized at 260V; the supply voltage of the second output unit 22 is-5V and 0V, and the low level output by the lower level shift circuit 20 can be stabilized at-5V and the high level can be stabilized at 0V.
By the scheme, the input 0-5V logic signals can be effectively converted into 255V-260V and-5V-0V voltage signals to be output, the level shift circuit adopts a cross coupling structure to ensure low power consumption, and the output stage adopts a Schmitt trigger structure to stabilize output voltage and improve the anti-interference capability.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A level shifting circuit, comprising:
the up-level shift circuit comprises a first level shift unit and a first output unit, wherein the first level shift unit comprises a first input end and a first output end, the first input end is used for accessing a low-voltage logic signal in a low-voltage domain, the first output end is connected with the first output unit, and the first level shift unit is used for converting the low-voltage logic signal in the low-voltage domain into a high-voltage control signal in a high-voltage domain;
the lower level shift circuit comprises a second level shift unit and a second output unit, the second level shift unit comprises a second input end and a second output end, the second input end is used for accessing a low-voltage logic signal of a low-voltage domain, the second output end is connected with the second output unit, and the second level shift unit is used for converting the low-voltage logic signal of the low-voltage domain into a negative-voltage control signal of a negative-voltage domain;
wherein the first input terminal is common to the second input terminal.
2. The level shift circuit of claim 1, wherein the first level shift unit and the second level shift unit each comprise a first switch module, a second switch module, and a signal conversion module, the first switch module is connected to the second switch module, the first switch module and the second switch module are connected to the signal conversion module, and the signal conversion module is further connected to a first voltage power supply and a second voltage power supply;
the on-off of the first switch module and the second switch module controls the signal conversion module to output a first voltage control signal or a second voltage control signal, and the first voltage is greater than the second voltage.
3. The level shift circuit according to claim 2, wherein the signal conversion module of the first level shift unit comprises a first high voltage-withstanding PMOS transistor, a second high voltage-withstanding PMOS transistor, a third low voltage-withstanding PMOS transistor, and a fourth low voltage-withstanding PMOS transistor;
the drain electrode of the first high voltage-resistant PMOS tube is connected with the first switch module, the grid electrode of the first high voltage-resistant PMOS tube is connected with the grid electrode of the second high voltage-resistant PMOS tube and the second voltage power supply, and the source electrode of the first high voltage-resistant PMOS tube is connected with the drain electrode of the third low voltage-resistant PMOS tube, the grid electrode of the fourth low voltage-resistant PMOS tube and the first output end; the drain electrode of the second high voltage-resistant PMOS tube is connected with the second switch module, and the source electrode of the second high voltage-resistant PMOS tube is connected with the drain electrode of the fourth low voltage-resistant PMOS tube and the grid electrode of the third low voltage-resistant PMOS tube; and the source electrode of the third low voltage-withstanding PMOS tube is connected with the source electrode of the fourth low voltage-withstanding PMOS tube and the first voltage power supply.
4. The level shift circuit of claim 3, wherein the signal conversion module of the first level shift unit further comprises a first diode, a second diode, a third diode, and a fourth diode;
the anode of the first diode is connected with the grid electrode of the first high voltage-resistant PMOS tube, and the cathode of the first diode is connected with the source electrode of the first high voltage-resistant PMOS tube and the anode of the third diode; the anode of the second diode is connected with the grid electrode of the second high voltage-resistant PMOS tube, and the cathode of the second diode is connected with the source electrode of the second high voltage-resistant PMOS tube and the anode of the fourth diode; the anode of the third diode is connected with the drain electrode of the third low voltage-withstanding PMOS tube, and the cathode of the third diode is connected with the source electrode of the third low voltage-withstanding PMOS tube; and the anode of the fourth diode is connected with the drain electrode of the fourth low voltage-withstanding PMOS tube, and the cathode of the fourth diode is connected with the source electrode of the fourth low voltage-withstanding PMOS tube.
5. The level shift circuit according to claim 4, wherein the first switch module of the first level shift unit comprises a first low withstand voltage NMOS transistor, a first low withstand voltage PMOS transistor and a first high withstand voltage NMOS transistor, and the second switch module of the first level shift unit comprises a second low withstand voltage NMOS transistor, a second low withstand voltage PMOS transistor and a second high withstand voltage NMOS transistor;
the source electrode of the first low withstand voltage NMOS tube is grounded, the drain electrode of the first low withstand voltage NMOS tube is connected with the drain electrode of the first low withstand voltage PMOS tube, the grid electrode of the first high withstand voltage NMOS tube, the grid electrodes of the two low withstand voltage NMOS tubes and the grid electrode of the second low withstand voltage PMOS tube, and the grid electrode of the first low withstand voltage NMOS tube is connected with the grid electrode of the first low withstand voltage PMOS tube and the first input end; the source electrode of the first low voltage-resistant PMOS tube is connected with an external power supply; the source electrode of the first high voltage-resistant NMOS tube is grounded, and the drain electrode of the first high voltage-resistant NMOS tube is connected with the drain electrode of the first high voltage-resistant PMOS tube;
the source electrode of the second low withstand voltage NMOS tube is grounded, the drain electrode of the second low withstand voltage NMOS tube is connected with the drain electrode of the second low withstand voltage PMOS tube and the grid electrode of the second high withstand voltage NMOS tube, and the grid electrode of the second low withstand voltage NMOS tube is connected with the grid electrode of the second low withstand voltage NMOS tube; the source electrode of the second low voltage-resistant PMOS tube is connected with an external power supply; and the source electrode of the second high voltage-resistant NMOS tube is grounded, and the drain electrode of the second high voltage-resistant NMOS tube is connected with the drain electrode of the second high voltage-resistant PMOS tube.
6. The level shift circuit of claim 2, wherein the signal conversion module of the second level shift unit comprises an eighth low withstand voltage NMOS transistor, a ninth low withstand voltage NMOS transistor, a tenth low withstand voltage NMOS transistor, and an eleventh low withstand voltage NMOS transistor;
a drain electrode of the eighth low withstand voltage NMOS transistor is connected to the first switch module, a gate electrode of the eighth low withstand voltage NMOS transistor is connected to a gate electrode of the ninth low withstand voltage NMOS transistor and the first voltage power supply, and a source electrode of the eighth low withstand voltage NMOS transistor is connected to a drain electrode of the tenth low withstand voltage NMOS transistor, a gate electrode of the eleventh low withstand voltage NMOS transistor, and the second output terminal; the drain electrode of the ninth low withstand voltage NMOS tube is connected with the second switch module, and the source electrode of the ninth low withstand voltage NMOS tube is connected with the drain electrode of the eleventh low withstand voltage NMOS tube and the grid electrode of the tenth low withstand voltage NMOS tube; and the source electrode of the tenth low withstand voltage NMOS tube is connected with the source electrode of the eleventh low withstand voltage NMOS tube and the second voltage power supply.
7. The level shift circuit of claim 6, wherein the signal conversion module of the second level shift unit further comprises a fifth diode and a sixth diode; the anode of the fifth diode is connected with the grid electrode of the eighth low withstand voltage NMOS tube, and the cathode of the fifth diode is connected with the source electrode of the eighth low withstand voltage NMOS tube; the anode of the sixth diode is connected with the grid electrode of the ninth low withstand voltage NMOS tube, and the cathode of the sixth diode is connected with the source electrode of the ninth low withstand voltage NMOS tube.
8. The level shift circuit according to claim 7, wherein the first switch module of the second level shift unit comprises a sixth low withstand voltage NMOS transistor, an eighth low withstand voltage PMOS transistor, and a tenth low withstand voltage PMOS transistor, and the second switch module of the second level shift unit comprises a seventh low withstand voltage NMOS transistor, a ninth low withstand voltage PMOS transistor, and an eleventh low withstand voltage PMOS transistor;
the source electrode of the sixth low withstand voltage NMOS tube is grounded, the drain electrode of the sixth low withstand voltage NMOS tube is connected with the drain electrode of the eighth low withstand voltage PMOS tube, the grid electrode of the tenth low withstand voltage PMOS tube, the grid electrode of the seventh low withstand voltage NMOS tube and the grid electrode of the ninth low withstand voltage NMOS tube, and the grid electrode of the sixth low withstand voltage NMOS tube is connected with the grid electrode of the eighth low withstand voltage PMOS tube and the second input end; the source electrode of the eighth low-voltage-withstanding PMOS tube is connected with an external power supply; a source electrode of the tenth low withstand voltage PMOS tube is connected with an external power supply, and a drain electrode of the tenth low withstand voltage PMOS tube is connected with a drain electrode of the eighth low withstand voltage NMOS tube;
the source electrode of the seventh low withstand voltage NMOS tube is grounded, the drain electrode of the seventh low withstand voltage NMOS tube is connected with the drain electrode of the ninth low withstand voltage PMOS and the grid electrode of the eleventh low withstand voltage PMOS tube, and the grid electrode of the seventh low withstand voltage NMOS tube is connected with the grid electrode of the ninth low withstand voltage PMOS tube; the source electrode of the ninth low-voltage-withstanding PMOS tube is connected with an external power supply; and the source electrode of the eleventh low withstand voltage PMOS tube is connected with an external power supply, and the drain electrode of the eleventh low withstand voltage PMOS tube is connected with the drain electrode of the ninth low withstand voltage NMOS tube.
9. The level shift circuit of claim 1, wherein the first output unit and/or the second output unit is a Schmitt trigger.
10. A high voltage analog switch, comprising a low voltage logic circuit, a level shift circuit, a switch driving circuit and an analog switch, wherein the level shift circuit electrically connects the low voltage logic circuit and the switch driving circuit, the switch driving circuit connects the analog switch, and the level shift circuit is the level shift circuit according to any one of claims 1 to 9.
CN202211367082.4A 2022-11-03 2022-11-03 Level shift circuit and high-voltage analog switch Withdrawn CN115567049A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116131828A (en) * 2023-02-02 2023-05-16 南京沁恒微电子股份有限公司 High-voltage floating gate driving circuit and driving chip thereof
CN116366051A (en) * 2023-03-21 2023-06-30 辰芯半导体（深圳）有限公司 Level shift circuit and level shifter
CN117318697A (en) * 2023-09-15 2023-12-29 辰芯半导体（深圳）有限公司 Level shift circuit and power supply device
CN117713788A (en) * 2024-02-05 2024-03-15 江苏润石科技有限公司 Control circuit of high-voltage switch based on thin gate oxide layer process

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116131828A (en) * 2023-02-02 2023-05-16 南京沁恒微电子股份有限公司 High-voltage floating gate driving circuit and driving chip thereof
CN116366051A (en) * 2023-03-21 2023-06-30 辰芯半导体（深圳）有限公司 Level shift circuit and level shifter
CN116366051B (en) * 2023-03-21 2024-02-13 辰芯半导体（深圳）有限公司 Level shift circuit and level shifter
CN117318697A (en) * 2023-09-15 2023-12-29 辰芯半导体（深圳）有限公司 Level shift circuit and power supply device
CN117713788A (en) * 2024-02-05 2024-03-15 江苏润石科技有限公司 Control circuit of high-voltage switch based on thin gate oxide layer process
CN117713788B (en) * 2024-02-05 2024-04-23 江苏润石科技有限公司 Control circuit of high-voltage switch based on thin gate oxide layer process

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