CN117713788A - Control circuit of high-voltage switch based on thin gate oxide layer process - Google Patents
Control circuit of high-voltage switch based on thin gate oxide layer process Download PDFInfo
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Abstract
The embodiment of the application provides a control circuit of a high-voltage switch based on a thin gate oxide process, wherein the high-voltage switch circuit comprises a thin gate oxide high-voltage NMOS (N-channel metal oxide semiconductor) tube and a thin gate oxide high-voltage PMOS tube, and the control circuit comprises a first control circuit and a second control circuit; the first control circuit controls the voltage difference between the grid voltage and the source voltage of the thin gate oxide layer high-voltage NMOS tube to enable the thin gate oxide layer high-voltage NMOS tube to be safely opened, the second control circuit controls the voltage difference between the grid voltage and the source voltage of the thin gate oxide layer high-voltage PMOS tube to enable the thin gate oxide layer high-voltage PMOS tube to be safely opened, and the first control circuit and the second control circuit are arranged to safely open the NMOS tube and the PMOS tube in the high-voltage switch circuit, so that the problem that in the prior art, the thin gate oxide high-voltage device is easy to break down due to poor device voltage resistance and then used as a high-voltage switch is effectively solved.
Description
Technical Field
The application relates to the technical field of microelectronics, in particular to a control circuit of a high-voltage switch based on a thin gate oxide layer process.
Background
In recent years, high voltage analog switches are widely used in communication systems and medical devices, which are commonly used to select and switch signals. The use of high voltage analog switches can greatly reduce the cost, power and equipment volume of the overall solution.
Conventional high voltage analog switches are designed based on a thick gate oxide process. The structure is similar to a low voltage analog switch, because the gate and source, gate and drain of a thick gate oxide high voltage device can withstand high voltages, so that the risk of breakdown of the device by high voltages does not occur. But the threshold voltage of thick gate oxide high voltage devices will typically be relatively large. For a switch with the same on-resistance, the larger the threshold value is, the larger the size is, so the threshold voltage of the thick gate oxide high voltage device directly affects the size of the device, and thus the chip cost.
However, only the gate and the drain of the thin gate oxide high voltage device can withstand high voltage, and the gate and the source and the gate and the substrate cannot withstand high voltage, so that the problem of withstand voltage of the device is easy to occur, and the thin gate oxide high voltage device is easy to break down when used as a high voltage switch.
Aiming at the problems that in the prior art, a thin gate oxide high-voltage device is easy to break down when being used as a high-voltage switch due to poor voltage resistance of the device, no effective solution exists yet.
Disclosure of Invention
The embodiment of the application provides a control circuit of a high-voltage switch based on a thin gate oxide layer process, which aims to solve the problem that a thin gate oxide high-voltage device in the related art is easy to break down when being used as a high-voltage switch due to poor voltage resistance of the device.
In one embodiment of the application, a control circuit of a high-voltage switch based on a thin gate oxide process is provided, wherein the high-voltage switch circuit comprises a thin gate oxide high-voltage NMOS tube and a thin gate oxide high-voltage PMOS tube, and the control circuit comprises a first control circuit and a second control circuit; the first control circuit controls the voltage difference between the grid voltage and the source voltage of the thin-gate oxide high-voltage NMOS transistor to enable the thin-gate oxide high-voltage NMOS transistor to be safely started, and the second control circuit controls the voltage difference between the grid voltage and the source voltage of the thin-gate oxide high-voltage PMOS transistor to enable the thin-gate oxide high-voltage PMOS transistor to be safely started; the high-voltage switch circuit comprises a first thin gate oxide high-voltage PMOS tube HVPM1, a second thin gate oxide high-voltage PMOS tube HVPM2, a first thin gate oxide high-voltage NMOS tube HVNM1, a second thin gate oxide high-voltage NMOS tube HVNM2, a first zener diode ZD1 and a second zener diode ZD2, wherein the grid electrode of the first thin gate oxide high-voltage PMOS tube HVPM1 is connected with a second grid voltage VPG, the drain electrode is connected with an input voltage VIN, the source electrode is connected with a second source voltage VPS, the cathode of the second zener diode ZD2 and the source electrode of the second thin gate oxide high-voltage PMOS tube HVPM2, the grid electrode of the second thin gate oxide high-voltage PMOS tube HVPM2 is connected with the anode of the second grid voltage VPG and the second zener diode ZD2, the drain electrode is connected with an output voltage VOUT, the grid electrode of the first thin gate oxide high-voltage NMOS tube HVNM1 is connected with the input voltage VPG, the drain electrode is connected with the input voltage VNS, the grid electrode of the second thin gate oxide high-voltage VN 2 is connected with the cathode of the second zener diode ZD2, and the drain electrode of the second zener diode ZD2 is connected with the anode of the second zener diode ZD 2; the first zener diode ZD1 and the second zener diode ZD2 are used to clamp a voltage difference between the gate and the source of the thin gate oxide high voltage tube to avoid breakdown of the thin gate oxide high voltage tube.
In an embodiment, when the source-to-gate voltage difference VPS-VPG > |vthp| of the first thin gate oxide high voltage PMOS transistor HVPM1 and the second thin gate oxide high voltage PMOS transistor HVPM2 and the source-to-gate voltage difference does not exceed the withstand voltage, the first thin gate oxide high voltage PMOS transistor HVPM1 and the second thin gate oxide high voltage PMOS transistor HVPM2 are turned on; wherein Vthp is the threshold voltage of the thin gate oxide high voltage PMOS transistor;
when the voltage difference VNG-VNS > Vthn between the gate and the source of the first thin gate oxide layer high-voltage NMOS transistor HVNM1 and the second thin gate oxide layer high-voltage NMOS transistor HVNM2, and the voltage difference between the source and the gate does not exceed the withstand voltage, the first thin gate oxide layer high-voltage NMOS transistor HVNM1 and the second thin gate oxide layer high-voltage NMOS transistor HVNM2 are turned on, and at this time, the high-voltage switch is in an on state; wherein Vthn is the threshold voltage of the thin gate oxide high voltage NMOS;
when vps=vpg, the first thin gate oxide layer high voltage PMOS transistor HVPM1 and the second thin gate oxide layer high voltage PMOS transistor HVPM2 are turned off; when vng=vns, the first thin gate oxide high voltage NMOS transistor HVNM1 and the second thin gate oxide high voltage NMOS transistor HVNM2 are turned off, and at this time, the high voltage switch is in a turned-off state.
In an embodiment, the first control circuit includes: the first PMOS tube PM1, the second PMOS tube PM2, the first NMOS tube NM1, the second NMOS tube NM2, the third thin gate oxide layer high-voltage PMOS tube HVPM3, the fourth thin gate oxide layer high-voltage PMOS tube HVPM4, the fifth thin gate oxide layer high-voltage PMOS tube HVPM5, the third thin gate oxide layer high-voltage NMOS tube HVNM3, the fourth thin gate oxide layer high-voltage NMOS tube HVNM4, the fifth thin gate oxide layer high-voltage NMOS tube HVNM5 and the sixth thin gate oxide layer high-voltage NMOS tube HVNM6;
the source electrode of the first PMOS tube PM1 is connected with a power supply voltage VCC, the grid electrode of the first PMOS tube PM2 is connected with the grid electrode of the second PMOS tube PM2 and the drain electrode of the second PMOS tube PM2, and the drain electrode of the second PMOS tube PM2 is connected with the source electrode of the fourth thin gate oxide layer high-voltage PMOS tube HVPM 4; the source electrode of the second PMOS tube PM2 is connected with a power supply voltage VCC, and the drain electrode of the second PMOS tube PM2 is connected with the grid electrode of the second PMOS tube PM and the source electrode of the fifth thin-gate oxide layer high-voltage PMOS tube HVPM 5; the grid electrode of the fourth thin gate oxide layer high-voltage PMOS tube HVPM4 is connected with the grid electrode and the drain electrode of the fifth thin gate oxide layer high-voltage PMOS tube HVPM5, and the drain electrode is connected with the grid electrode and the drain electrode of the first NMOS tube NM1 and the first grid voltage VNG; the drain electrode of the fifth thin gate oxide layer high-voltage PMOS tube HVPM5 is connected with the grid electrode of the fifth thin gate oxide layer high-voltage NMOS tube HVNM5 and the drain electrode of the sixth thin gate oxide layer high-voltage NMOS tube HVNM6; the gate of the first NMOS tube NM1 is connected with the drain of the first NMOS tube NM1 and the first gate voltage VNG, and the source is connected with the gate and the drain of the second NMOS tube NM 2; the source electrode of the second NMOS tube NM2 is connected with the source electrode of the third thin gate oxide layer high-voltage PMOS tube HVPM 3; the grid electrode of the third thin gate oxide layer high-voltage PMOS tube HVPM3 is connected with the drain electrode of the third thin gate oxide layer high-voltage NMOS tube HVNM3 and the first source voltage VNS, and the drain electrode is grounded; the grid electrode of the third thin gate oxide layer high-voltage NMOS tube HVNM3 is connected with the grid electrode of the fourth thin gate oxide layer high-voltage NMOS tube HVNM4 and the second control signal VSW2, and the source electrode is grounded; the grid electrode of the fourth thin gate oxide layer high-voltage NMOS tube HVNM4 is connected with the second control signal VSW2, the drain electrode is connected with the first grid voltage VNG, and the source electrode is grounded; the grid electrode of the fifth thin gate oxide layer high-voltage NMOS tube HVNM5 is connected with a forward pulse signal VPL, and the source electrode is grounded; the gate of the sixth thin gate oxide high voltage NMOS transistor HVNM6 is connected to the first control signal VSW1, and the source is connected to the first current mirror I1.
In an embodiment, by adjusting the sizes of the first NMOS transistor NM1, the second NMOS transistor NM2, and the third thin gate oxide high voltage PMOS transistor HVPM3 and the current of the first current mirror I1, the voltage difference between the VNG and the VNS is within the voltage-resistant range of the first thin gate oxide high voltage NMOS transistor HVNM1 and the second thin gate oxide high voltage NMOS transistor HVNM2, so as to keep the first thin gate oxide high voltage NMOS transistor HVNM1 and the second thin gate oxide high voltage NMOS transistor HVNM2 safely open.
In an embodiment, the second control circuit includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a sixth thin gate oxide high voltage PMOS transistor HVPM6, a seventh thin gate oxide high voltage PMOS transistor HVPM7, an eighth thin gate oxide high voltage PMOS transistor HVPM8, a ninth thin gate oxide high voltage PMOS transistor HVPM9, a seventh thin gate oxide high voltage NMOS transistor HVNM7, an eighth thin gate oxide high voltage NMOS transistor HVNM8, a ninth thin gate oxide high voltage NMOS transistor HVNM9, a tenth thin gate oxide high voltage NMOS transistor HVNM10, and an eleventh thin gate oxide high voltage NMOS transistor HVNM11;
the grid electrode of the third PMOS tube PM3 is connected with the drain electrode of the third PMOS tube PM3 and the grid electrode of the fourth PMOS tube PM4, the source electrode of the third PMOS tube PM3 is connected with the power supply voltage VCC, and the drain electrode of the third PMOS tube PM3 is connected with the source electrode of the sixth thin gate oxide layer high-voltage PMOS tube HVPM 6; the source electrode of the fourth PMOS tube PM4 is connected with a power supply voltage VCC, and the drain electrode of the fourth PMOS tube PM4 is connected with the source electrode of the seventh thin gate oxide layer high-voltage PMOS tube HVPM 7; the grid electrode of the sixth thin gate oxide layer high-voltage PMOS tube HVPM6 is connected with the drain electrode of the sixth thin gate oxide layer high-voltage PMOS tube HVPM7 and the grid electrode of the seventh thin gate oxide layer high-voltage PMOS tube HVPM7, and the drain electrode of the seventh thin gate oxide layer high-voltage NMOS tube HVNM7 and the drain electrode of the eighth thin gate oxide layer high-voltage NMOS tube HVNM 8; the grid electrode of the seventh thin gate oxide layer high-voltage NMOS tube HVNM7 is connected with a first control signal VSW1, and the source electrode is connected with a second current mirror I2; the grid electrode of the eighth thin gate oxide layer high-voltage NMOS tube HVNM8 is connected with a forward pulse signal VPL, and the source electrode is grounded; the grid electrode of the ninth thin gate oxide layer high-voltage NMOS tube HVNM9 is connected with the drain electrode of the ninth thin gate oxide layer high-voltage NMOS tube HVNM10 and the grid electrode of the tenth thin gate oxide layer high-voltage NMOS tube HVNM10, and the source electrode of the ninth thin gate oxide layer high-voltage NMOS tube HVNM9 is connected with the drain electrode of the third NMOS tube NM 3; the source electrode of the tenth thin gate oxide high-voltage NMOS tube HVNM10 is connected with the drain electrode of the fourth NMOS tube NM4, and the drain electrode is connected with the second gate voltage VPG; the grid electrodes of the third NMOS tube NM3 and the fourth NMOS tube NM4 are connected with each other, and the source electrodes are grounded; the gate of the eighth thin gate oxide high voltage PMOS transistor HVPM8 and the gate of the ninth thin gate oxide high voltage PMOS transistor HVPM9 are both connected to a third control signal VSW3, the source of the eighth thin gate oxide high voltage PMOS transistor HVPM8 and the source of the ninth thin gate oxide high voltage PMOS transistor HVPM9 are both connected to a power supply voltage VCC, the drain of the eighth thin gate oxide high voltage PMOS transistor HVPM8 is connected to the gate of the eleventh thin gate oxide high voltage NMOS transistor HVNM11 and the second source voltage VPS, and the drain of the ninth thin gate oxide high voltage PMOS transistor HVPM9 is connected to the gate of the fifth PMOS transistor PM5 and the second gate voltage VPG; the grid electrode of the sixth PMOS tube PM6 is connected with the drain electrode of the sixth PMOS tube PM5 and the source electrode of the fifth PMOS tube PM5, and the source electrode of the eleventh thin gate oxide layer high-voltage NMOS tube HVNM11; the grid electrode of the fifth PMOS tube PM5 is connected with the drain electrode of the fifth PMOS tube PM5 and the second grid voltage VPG; the drain electrode of the eleventh thin gate oxide high-voltage NMOS transistor HVNM11 is connected to the power supply voltage VCC.
In an embodiment, by adjusting the sizes of the fifth PMOS PM5, the sixth PMOS PM6 and the eleventh thin gate oxide high voltage NMOS HVNM11 and the current of the second current mirror I2, the voltage difference between VPS and VPG is in the voltage-resistant range of the first thin gate oxide high voltage PMOS HVPM1 and the second thin gate oxide high voltage PMOS HVPM2, so as to keep the first thin gate oxide high voltage NMOS HVNM1 and the second thin gate oxide high voltage PMOS HVPM2 safely open.
Through the control circuit of the high-voltage switch based on the thin gate oxide layer process, which is provided by the embodiment of the application, the high-voltage switch circuit comprises a thin gate oxide layer high-voltage NMOS tube and a thin gate oxide layer high-voltage PMOS tube, and the control circuit comprises a first control circuit and a second control circuit; the first control circuit controls the voltage difference between the grid voltage and the source voltage of the thin gate oxide layer high-voltage NMOS tube to enable the thin gate oxide layer high-voltage NMOS tube to be safely opened, the second control circuit controls the voltage difference between the grid voltage and the source voltage of the thin gate oxide layer high-voltage PMOS tube to enable the thin gate oxide layer high-voltage PMOS tube to be safely opened, and the first control circuit and the second control circuit are arranged to safely open the NMOS tube and the PMOS tube in the high-voltage switch circuit, so that the problem that in the prior art, the thin gate oxide high-voltage device is easy to break down due to poor device voltage resistance and then used as a high-voltage switch is effectively solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a schematic diagram of a conventional high-voltage switch circuit in the prior art;
FIG. 2 is a schematic diagram of a control circuit configuration of an alternative thin gate oxide process-based high voltage switch according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an alternative thin gate oxide process based high voltage switching circuit in accordance with an embodiment of the present application;
FIG. 4 is an alternative first control circuit schematic according to an embodiment of the present application;
FIG. 5 is an alternative second control circuit schematic according to an embodiment of the present application;
FIG. 6 is a schematic diagram of the variation of the control signal of the high voltage switch in the related art when turned on;
fig. 7 is a schematic diagram of an alternative high voltage switch control signal change when turned on according to an embodiment of the present application.
Detailed Description
The present application will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
Conventional high voltage analog switches are designed based on a thick gate oxide process. The structure is similar to a low voltage analog switch, because the gate and source, gate and drain of a thick gate oxide high voltage device can withstand high voltages, so that the risk of breakdown of the device by high voltages does not occur. As shown in fig. 1, P1 and N1 are thick gate oxide high voltage devices, each end of which can withstand high voltages.
Conventional high voltage analog switches, while simple in structure, may suffer from poor characteristics, such as a relatively large threshold voltage for thick gate oxide high voltage devices. The larger the threshold, the larger the size for a switch with the same on-resistance. The threshold voltage parameter is important and directly affects the device size and thus the chip cost. While the threshold voltage of the high voltage devices of the thin gate oxide process is generally smaller, it is important to be able to design the high voltage switch based on the thin gate oxide process for downsizing and saving cost.
An embodiment of the present application proposes a control circuit of a high-voltage switch based on a thin gate oxide process, and fig. 2 is a schematic structural diagram of an alternative control circuit of a high-voltage switch based on a thin gate oxide process according to an embodiment of the present application, as shown in fig. 2, including: a first control circuit and a second control circuit; the first control circuit controls the voltage difference between the grid voltage and the source voltage of the thin-gate oxide high-voltage NMOS tube to enable the thin-gate oxide high-voltage NMOS tube to be safely started, and the second control circuit controls the voltage difference between the grid voltage and the source voltage of the thin-gate oxide high-voltage PMOS tube to enable the thin-gate oxide high-voltage PMOS tube to be safely started.
Fig. 3 is a schematic structural diagram of an alternative high-voltage switching circuit based on a thin gate oxide process according to an embodiment of the present application, and as shown in fig. 3, the high-voltage switching circuit includes: the high-voltage MOS transistor comprises a first thin gate oxide high-voltage PMOS tube HVPM1, a second thin gate oxide high-voltage PMOS tube HVPM2, a first thin gate oxide high-voltage NMOS tube HVNM1, a second thin gate oxide high-voltage NMOS tube HVNM2, a first Zener diode ZD1 and a second Zener diode ZD2, wherein the grid electrode of the first thin gate oxide high-voltage PMOS tube HVPM1 is connected with a first grid voltage VPG, the drain electrode is connected with an input voltage VIN, the source electrode is connected with a first source voltage VPS, the cathode of the second Zener diode ZD2 and the source electrode of the second thin gate oxide high-voltage PMOS tube HVPM2, the grid electrode of the second thin gate oxide high-voltage PMOS tube HVPM2 is connected with the anode of the first gate voltage VPG and the second Zener diode ZD2, the drain electrode is connected with an output voltage VOUT, the grid electrode of the first thin gate oxide high-voltage NMOS tube HVNM1 is connected with the second grid voltage VNG, the drain electrode is connected with the input voltage VNS, the source electrode is connected with the second grid voltage VNS 2 and the drain electrode of the second Zener diode ZD 2; the first zener diode ZD1 and the second zener diode ZD2 are used for clamping a voltage difference between the gate and the source of the thin gate oxide high-voltage tube to avoid breakdown of the thin gate oxide high-voltage tube.
When the source-to-gate voltage differences VPS-VPG > |vthp| of HVPM1 and HVPM2, and the source-to-gate voltage differences do not exceed the withstand voltage, HVPM1 and HVPM2 are turned on; when the gate-to-source voltage difference VNG-VNS > Vthn of HVNM1 and HVNM2, and the source-to-gate voltage difference does not exceed the withstand voltage, HVNM1 and HVNM2 are turned on. At this time, the high-voltage switch is in an on state.
When vps=vpg, HVPM1 and HVPM2 are off; when vng=vns, HVNM1 and HVNM2 are turned off. At this time, the high-voltage switch is in an off state.
Fig. 4 is a schematic diagram of an alternative first control circuit according to an embodiment of the present application, as shown in fig. 4, a control circuit of a first thin gate oxide high voltage NMOS transistor HVNM1 and a second thin gate oxide high voltage NMOS transistor HVNM2 includes:
the first PMOS tube PM1, the second PMOS tube PM2, the first NMOS tube NM1, the second NMOS tube NM2, the third thin gate oxide layer high-voltage PMOS tube HVPM3, the fourth thin gate oxide layer high-voltage PMOS tube HVPM4, the fifth thin gate oxide layer high-voltage PMOS tube HVPM5, the third thin gate oxide layer high-voltage NMOS tube HVNM3, the fourth thin gate oxide layer high-voltage NMOS tube HVNM4, the fifth thin gate oxide layer high-voltage NMOS tube HVNM5 and the sixth thin gate oxide layer high-voltage NMOS tube HVNM6;
the source electrode of the first PMOS tube PM1 is connected with a power supply voltage VCC, the grid electrode of the first PMOS tube PM2 is connected with the grid electrode of the second PMOS tube PM2 and the drain electrode of the second PMOS tube PM2, and the drain electrode of the second PMOS tube PM2 is connected with the source electrode of the fourth thin gate oxide layer high-voltage PMOS tube HVPM 4; the source electrode of the second PMOS tube PM2 is connected with a power supply voltage VCC, and the drain electrode of the second PMOS tube PM2 is connected with the grid electrode of the second PMOS tube PM and the source electrode of the fifth thin-gate oxide layer high-voltage PMOS tube HVPM 5; the grid electrode of the fourth thin gate oxide layer high-voltage PMOS tube HVPM4 is connected with the grid electrode and the drain electrode of the fifth thin gate oxide layer high-voltage PMOS tube HVPM5, and the drain electrode is connected with the grid electrode and the drain electrode of the first NMOS tube NM1 and the second grid voltage VNG; the drain electrode of the fifth thin gate oxide layer high-voltage PMOS tube HVPM5 is connected with the grid electrode of the fifth thin gate oxide layer high-voltage NMOS tube HVNM5 and the drain electrode of the sixth thin gate oxide layer high-voltage NMOS tube HVNM6; the gate of the first NMOS tube NM1 is connected with the drain electrode of the first NMOS tube NM1 and the second gate voltage VNG, and the source electrode of the first NMOS tube NM2 is connected with the gate electrode and the drain electrode of the second NMOS tube NM 2; the source electrode of the second NMOS tube NM2 is connected with the source electrode of the third thin gate oxide layer high-voltage PMOS tube HVPM 3; the grid electrode of the third thin gate oxide layer high-voltage PMOS tube HVPM3 is connected with the drain electrode of the third thin gate oxide layer high-voltage NMOS tube HVNM3 and the first source voltage VNS, and the drain electrode is grounded; the grid electrode of the third thin gate oxide layer high-voltage NMOS tube HVNM3 is connected with the grid electrode of the fourth thin gate oxide layer high-voltage NMOS tube HVNM4 and the second control signal VSW2, and the source electrode is grounded; the grid electrode of the fourth thin gate oxide layer high-voltage NMOS tube HVNM4 is connected with the second control signal VSW2, the drain electrode is connected with the first grid voltage VNG, and the source electrode is grounded; the grid electrode of the fifth thin gate oxide layer high-voltage NMOS tube HVNM5 is connected with a forward pulse signal VPL, and the source electrode is grounded; the gate of the sixth thin gate oxide high voltage NMOS transistor HVNM6 is connected to the first control signal VSW1, and the source is connected to the first current mirror I1.
I1 is the current mirror current. The first control signal VSW1 and the second control signal VSW2 are control signals with opposite logic, VPL is a forward pulse signal, power sources of VSW1, VSW2 and VPL and ground are VDD and GND, respectively, VDD is a low power source with respect to GND.
When the high voltage switch is off, VSW1 is logic low and VSW2 is logic high. At this time, HVNM3 and HVNM4 are on, HVNM5 and HVNM6 are off at all times, current mirror I1 is off, and the current after off is 0. At this time, the gate potential VNG and the source potential VNS of the switching high voltages HVNM1 and HVNM2 are both GND. At this time, HVNM1 and HVNM2 are in the off state.
When the high voltage switch goes from off to on, VSW1 goes to logic high, VSW2 goes to logic low, and a VPL forward pulse is generated. HVNM3 and HVNM4 are off, and HVNM6 is on. During the generation of the forward pulse VPL, HVNM5 is on.
During HVNM5 on, current mirrors PM2 and HVPM5 will replicate more current to PM1 and HVPM4 branches so that VCC will charge VNG quickly through PM1 and HVPM4, which can speed up switching transistor turn on. At that time, HVNM1 and HVNM2 are on. At this point VIN will pass to VNS. If the size of the transmission gate is large enough, the on-resistance and thus the voltage drop is small, then VNS is approximately equal to VIN.
After the end of the VPL pulse, HVNM5 is turned off. The current mirror I1 mirrors the PM1 and HVPM4 branches through PM2 and HVPM5, and current flows through NM1, NM2, and HVPM3, creating a voltage drop.
By adjusting the dimensions of NM1, NM2 and HVPM3 and the current mirror current, the voltage difference between VNG and VNS can be made within the withstand voltage range of HVNM1 and HVNM2, thereby keeping HVNM1 and HVNM2 safely on.
Fig. 5 is an optional second control circuit schematic diagram according to an embodiment of the present application, as shown in fig. 5, a control circuit of the first thin gate oxide high voltage PMOS transistor HVPM1 and the second thin gate oxide high voltage PMOS transistor HVPM2 includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a sixth thin gate oxide high voltage PMOS transistor HVPM6, a seventh thin gate oxide high voltage PMOS transistor HVPM7, an eighth thin gate oxide high voltage PMOS transistor HVPM8, a ninth thin gate oxide high voltage PMOS transistor HVPM9, a seventh thin gate oxide high voltage NMOS transistor HVNM7, an eighth thin gate oxide high voltage NMOS transistor HVNM8, a ninth thin gate oxide high voltage NMOS transistor HVNM9, a tenth thin gate oxide high voltage NMOS transistor HVNM10, and an eleventh thin gate oxide high voltage NMOS transistor HVNM11;
the grid electrode of the third PMOS tube PM3 is connected with the drain electrode of the third PMOS tube PM3 and the grid electrode of the fourth PMOS tube PM4, the source electrode of the third PMOS tube PM3 is connected with the power supply voltage VCC, and the drain electrode of the third PMOS tube PM3 is connected with the source electrode of the sixth thin gate oxide layer high-voltage PMOS tube HVPM 6; the source electrode of the fourth PMOS tube PM4 is connected with a power supply voltage VCC, and the drain electrode of the fourth PMOS tube PM4 is connected with the source electrode of the seventh thin gate oxide layer high-voltage PMOS tube HVPM 7; the grid electrode of the sixth thin gate oxide layer high-voltage PMOS tube HVPM6 is connected with the drain electrode of the sixth thin gate oxide layer high-voltage PMOS tube HVPM7 and the grid electrode of the seventh thin gate oxide layer high-voltage PMOS tube HVPM7, and the drain electrode of the seventh thin gate oxide layer high-voltage NMOS tube HVNM7 and the drain electrode of the eighth thin gate oxide layer high-voltage NMOS tube HVNM 8; the grid electrode of the seventh thin gate oxide layer high-voltage NMOS tube HVNM7 is connected with a first control signal VSW1, and the source electrode is connected with a second current mirror I2; the grid electrode of the eighth thin gate oxide layer high-voltage NMOS tube HVNM8 is connected with a forward pulse signal VPL, and the source electrode is grounded; the grid electrode of the ninth thin gate oxide layer high-voltage NMOS tube HVNM9 is connected with the drain electrode of the ninth thin gate oxide layer high-voltage NMOS tube HVNM10 and the grid electrode of the tenth thin gate oxide layer high-voltage NMOS tube HVNM10, and the source electrode of the ninth thin gate oxide layer high-voltage NMOS tube HVNM9 is connected with the drain electrode of the third NMOS tube NM 3; the source electrode of the tenth thin gate oxide high-voltage NMOS tube HVNM10 is connected with the drain electrode of the fourth NMOS tube NM4, and the drain electrode is connected with the second gate voltage VPG; the grid electrodes of the third NMOS tube NM3 and the fourth NMOS tube NM4 are connected with each other, and the source electrodes are grounded; the gate of the eighth thin gate oxide high voltage NMOS transistor HVNM8 and the gate of the ninth thin gate oxide high voltage NMOS transistor HVNM9 are both connected to a third control signal VSW3, the gate of the eighth thin gate oxide high voltage PMOS transistor HVPM8 and the gate of the ninth thin gate oxide high voltage PMOS transistor HVPM9 are both connected to a third control signal VSW3, the source of the eighth thin gate oxide high voltage PMOS transistor HVPM8 and the source of the ninth thin gate oxide high voltage PMOS transistor HVPM9 are both connected to a power supply voltage VCC, the drain of the eighth thin gate oxide high voltage PMOS transistor HVPM8 is connected to the gate of the eleventh thin gate oxide high voltage NMOS transistor HVNM11 and the second source voltage VPS, and the drain of the ninth thin gate oxide high voltage PMOS transistor HVPM9 is connected to the gate of the fifth PMOS transistor PM5 and the second gate voltage VPG; the grid electrode of the sixth PMOS tube PM6 is connected with the drain electrode of the sixth PMOS tube PM5 and the source electrode of the fifth PMOS tube PM5, and the source electrode of the eleventh thin gate oxide layer high-voltage NMOS tube HVNM11; the grid electrode of the fifth PMOS tube PM5 is connected with the drain electrode of the fifth PMOS tube PM5 and the second grid voltage VPG; the drain electrode of the eleventh thin gate oxide high-voltage NMOS tube HNPM11 is connected to the power supply voltage VCC.
I2 is the current mirror current. VSW1 and VSW3 are control signals having the same logic, VPL is a forward pulse signal, power supplies of VSW1 and VPL and ground are VDD and GND, respectively, and VDD is a low-voltage power supply with respect to GND; when the input signal VSW1 goes from logic low to logic high, a positive going pulse signal VPL is generated.
When the high voltage switch is off, VSW1 is logic low and VSW3 is logic low. At this time, HVPM8 and HVPM9 are on, HVNM7 and HVNM8 are always off, and current mirror I2 is off. At this time, the gate potential VPG and the source potential VPS of the high-voltage switches HVPM1 and HVPM2 are both VCC. At this time, HVPM1 and HVPM2 are in the off state.
When the high voltage switch goes from off to on, VSW1 goes to logic high, VSW3 goes to logic high, and a VPL forward pulse is generated. HVPM8 and HVPM9 are off, HVNM7 is on. During the generation of the forward pulse VPL, HVNM8 is on.
During the turn-on period of HVNM8, the current mirrors PM3 and HVPM6 will copy more current to the PM4 and HVPM7 branches, NM3 and HVNM9 copy current to the NM4 and HVNM10 branches, so that VPG is rapidly discharged through NM4 and HVNM10, which can accelerate the turn-on of the switching tube. At that time, HVNM1 and HVNM2 are on. At this point VIN will pass to the VPS. If the size of the transmission gate is large enough, the on-resistance and thus the voltage drop is small, VPS is approximately equal to VIN.
After the end of the VPL pulse, HVNM8 is turned off. The current mirror I2 is replicated to the PM4 and HVPM7 branches through the current mirrors PM3 and HVPM6, and then the NM3 and HVNM9 replicate currents to the NM4 and HVNM10 branches, the replicated currents flowing through PM5, PM6 and HVNM11, creating a voltage drop.
By adjusting the dimensions of PM5, PM6 and HVNM11 and the current mirror current, the voltage difference between VPS and VPG can be made within the withstand voltage range of HVPM1 and HVPM2, thereby keeping HVPM1 and HVPM2 safely on.
It should be noted that, the high-voltage switch in the embodiment of the present application may transmit a signal from 0 to VCC, or may transmit a signal from a negative power supply VEE to a positive power supply VCC, which may be selected according to practical applications, which is not limited in the embodiment of the present application.
In the related art, in the process of starting the high-voltage switch, the control end of the high-voltage switch needs to be charged and discharged. The potential of the control end node is generally changed more, and the parasitic capacitance of the high-voltage switch exists, so that the potential change of the control end node is slower, and the switch opening speed is slow. FIG. 6 is a schematic diagram of the variation of the control signal of the high voltage switch in the related art when turned on; fig. 7 is a schematic diagram of a change of an optional high-voltage switch control terminal signal when turned on according to an embodiment of the present application, and as shown in fig. 6 and fig. 7, a control circuit adopted in the embodiment of the present application may obviously accelerate the turning on of the high-voltage switch. Mainly, during the on period of HVNM8, the current mirrors PM3 and HVPM6 will copy more current to the branches PM4 and HVPM7, and NM3 and HVNM9 copy current to the branches NM4 and HVNM10, so that VPG is rapidly discharged through NM4 and HVNM10, and the on of the switching tube can be accelerated. Similarly, during HVNM5 on, current mirrors PM2 and HVPM5 will replicate more current to PM1 and HVPM4 branches, so that VCC will charge VNG quickly through PM1 and HVPM4, which can speed up switching transistor turn on.
Through the control circuit of the high-voltage switch based on the thin gate oxide layer process, which is provided by the embodiment of the application, the high-voltage switch circuit comprises a thin gate oxide layer high-voltage NMOS tube and a thin gate oxide layer high-voltage PMOS tube, and the control circuit comprises a first control circuit and a second control circuit; the first control circuit controls the voltage difference between the grid voltage and the source voltage of the thin gate oxide layer high-voltage NMOS tube to enable the thin gate oxide layer high-voltage NMOS tube to be safely opened, the second control circuit controls the voltage difference between the grid voltage and the source voltage of the thin gate oxide layer high-voltage PMOS tube to enable the thin gate oxide layer high-voltage PMOS tube to be safely opened, and the first control circuit and the second control circuit are arranged to safely open the NMOS tube and the PMOS tube in the high-voltage switch circuit, so that the problem that in the prior art, the thin gate oxide high-voltage device is easy to break down due to poor device voltage resistance and then used as a high-voltage switch is effectively solved.
The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.
In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application and are intended to be comprehended within the scope of the present application.
Claims (6)
1. The control circuit of the high-voltage switch based on the thin gate oxide process is characterized by comprising a thin gate oxide high-voltage NMOS tube and a thin gate oxide high-voltage PMOS tube, wherein the control circuit comprises a first control circuit and a second control circuit; the first control circuit controls the voltage difference between the grid voltage and the source voltage of the thin-gate oxide high-voltage NMOS transistor to enable the thin-gate oxide high-voltage NMOS transistor to be safely started, and the second control circuit controls the voltage difference between the grid voltage and the source voltage of the thin-gate oxide high-voltage PMOS transistor to enable the thin-gate oxide high-voltage PMOS transistor to be safely started; the high-voltage switch circuit comprises a first thin gate oxide high-voltage PMOS tube (HVPM 1), a second thin gate oxide high-voltage PMOS tube (HVPM 2), a first thin gate oxide high-voltage NMOS tube (HVNM 1), a second thin gate oxide high-voltage NMOS tube (HVNM 2), a first zener diode (ZD 1) and a second zener diode (ZD 2), wherein the grid electrode of the first thin gate oxide high-voltage PMOS tube (HVPM 1) is connected with a second grid Voltage (VPG), the drain electrode is connected with an input Voltage (VIN), the source electrode is connected with a second source Voltage (VPS), the negative electrode of the second zener diode (ZD 2) and the source electrode of the second thin gate oxide high-voltage PMOS tube (HVPM 2), the grid electrode of the second thin gate oxide high-voltage PMOS tube (HVPM 2) is connected with the positive electrode of the second zener diode (ZD 2), the drain electrode is connected with an output voltage (ZD 2), the first thin gate oxide high-voltage (HVMOS tube (HVPM 1) is connected with the positive electrode of the second zener diode (HVPM 2), the source electrode is connected with the first drain electrode of the second zener diode (HVPM 2), and the drain electrode of the first thin gate oxide high-voltage PMOS tube (HVPM 1) is connected with the positive electrode of the second zener diode (HVPM 2);
the first zener diode (ZD 1) and the second zener diode (ZD 2) are used for clamping a voltage difference between a gate and a source of the thin gate oxide high voltage tube to avoid breakdown of the thin gate oxide high voltage tube.
2. The control circuit for a high voltage switch based on a thin gate oxide process of claim 1, wherein,
when the source-to-gate voltage difference VPS-VPG > |Vthp| of the first thin gate oxide layer high-voltage PMOS tube (HVPM 1) and the second thin gate oxide layer high-voltage PMOS tube (HVPM 2) and the source-to-gate voltage difference does not exceed the withstand voltage, the first thin gate oxide layer high-voltage PMOS tube (HVPM 1) and the second thin gate oxide layer high-voltage PMOS tube (HVPM 2) are opened; wherein Vthp is the threshold voltage of the thin gate oxide high voltage PMOS transistor;
when the voltage difference VNG-VNS > Vthn between the grid electrode and the source electrode of the first thin gate oxide layer high-voltage NMOS tube (HVNM 1) and the second thin gate oxide layer high-voltage NMOS tube (HVNM 2) does not exceed the voltage withstand voltage, the first thin gate oxide layer high-voltage NMOS tube (HVNM 1) and the second thin gate oxide layer high-voltage NMOS tube (HVNM 2) are opened, and at the moment, the high-voltage switch is in an opened state; wherein Vthn is the threshold voltage of the thin gate oxide high voltage NMOS;
when vps=vpg, the first thin gate oxide high voltage PMOS (HVPM 1) and the second thin gate oxide high voltage PMOS (HVPM 2) are turned off; when vng=vns, the first thin gate oxide high voltage NMOS (HVNM 1) and the second thin gate oxide high voltage NMOS (HVNM 2) are turned off, and at this time, the high voltage switch is in an off state.
3. The control circuit of a thin gate oxide process-based high voltage switch of claim 1, wherein the first control circuit comprises:
a first PMOS tube (PM 1), a second PMOS tube (PM 2), a first NMOS tube (NM 1), a second NMOS tube (NM 2), a third thin gate oxide high voltage PMOS tube (HVPM 3), a fourth thin gate oxide high voltage PMOS tube (HVPM 4), a fifth thin gate oxide high voltage PMOS tube (HVPM 5), a third thin gate oxide high voltage NMOS tube (HVNM 3), a fourth thin gate oxide high voltage NMOS tube (HVNM 4), a fifth thin gate oxide high voltage NMOS tube (HVNM 5) and a sixth thin gate oxide high voltage NMOS tube (HVNM 6);
the source electrode of the first PMOS tube (PM 1) is connected with a power supply voltage VCC, the grid electrode of the second PMOS tube (PM 2) is connected with the grid electrode of the second PMOS tube (PM 2) and the drain electrode of the second PMOS tube (PM 2), and the drain electrode of the fourth thin gate oxide layer high-voltage PMOS tube (HVPM 4) is connected with the source electrode; the source electrode of the second PMOS tube (PM 2) is connected with a power supply Voltage (VCC), and the drain electrode of the second PMOS tube is connected with the grid electrode of the second PMOS tube and the source electrode of the fifth thin-gate oxide layer high-voltage PMOS tube (HVPM 5); the grid electrode of the fourth thin gate oxide layer high-voltage PMOS tube (HVPM 4) is connected with the grid electrode and the drain electrode of the fifth thin gate oxide layer high-voltage PMOS tube (HVPM 5), and the drain electrode is connected with the grid electrode and the drain electrode of the first NMOS tube (NM 1) and the first grid Voltage (VNG); the drain electrode of the fifth thin gate oxide high-voltage PMOS tube (HVPM 5) is connected with the drain electrode of the fifth thin gate oxide high-voltage NMOS tube (HVNM 5) and the drain electrode of the sixth thin gate oxide high-voltage NMOS tube (HVNM 6); the grid electrode of the first NMOS tube (NM 1) is connected with the drain electrode of the first NMOS tube and the first grid Voltage (VNG), and the source electrode of the first NMOS tube (NM 2) is connected with the grid electrode and the drain electrode; the source electrode of the second NMOS tube (NM 2) is connected with the source electrode of the third thin gate oxide high-voltage PMOS tube (HVPM 3); the grid electrode of the third thin gate oxide layer high-voltage PMOS tube (HVPM 3) is connected with the drain electrode of the third thin gate oxide layer high-voltage NMOS tube (HVNM 3) and the first source electrode Voltage (VNS), and the drain electrode is grounded; the grid electrode of the third thin gate oxide layer high-voltage NMOS tube (HVNM 3) is connected with the grid electrode of the fourth thin gate oxide layer high-voltage NMOS tube (HVNM 4) and a second control signal (VSW 2), and the source electrode is grounded; the grid electrode of the fourth thin gate oxide layer high-voltage NMOS tube (HVNM 4) is connected with the second control signal (VSW 2), the drain electrode is connected with the first grid Voltage (VNG), and the source electrode is grounded; the grid electrode of the fifth thin gate oxide layer high-voltage NMOS tube (HVNM 5) is connected with a forward pulse signal (VPL), and the source electrode is grounded; and the grid electrode of the sixth thin gate oxide layer high-voltage NMOS tube (HVNM 6) is connected with a first control signal (VSW 1), and the source electrode of the sixth thin gate oxide layer high-voltage NMOS tube is connected with a first current mirror (I1).
4. The control circuit for a high voltage switch based on a thin gate oxide process as claimed in claim 3, wherein,
by adjusting the sizes of the first NMOS tube (NM 1), the second NMOS tube (NM 2) and the third thin gate oxide layer high-voltage PMOS tube (HVPM 3) and the current of the first current mirror (I1), the voltage difference between the VNG and the VNS is in the voltage-resistant range of the first thin gate oxide layer high-voltage NMOS tube (HVNM 1) and the second thin gate oxide layer high-voltage NMOS tube (HVNM 2), so that the first thin gate oxide layer high-voltage NMOS tube (HVNM 1) and the second thin gate oxide layer high-voltage NMOS tube (HVNM 2) are kept safely opened.
5. The control circuit of a thin gate oxide process-based high voltage switch of claim 1, wherein the second control circuit comprises:
a third PMOS transistor (PM 3), a fourth PMOS transistor (PM 4), a fifth PMOS transistor (PM 5), a sixth PMOS transistor (PM 6), a third NMOS transistor (NM 3), a fourth NMOS transistor (NM 4), a sixth thin gate oxide high voltage PMOS transistor (HVPM 6), a seventh thin gate oxide high voltage PMOS transistor (HVPM 7), an eighth thin gate oxide high voltage PMOS transistor (HVPM 8), a ninth thin gate oxide high voltage PMOS transistor (HVPM 9), a seventh thin gate oxide high voltage NMOS transistor (HVNM 7), an eighth thin gate oxide high voltage NMOS transistor (HVNM 8), a ninth thin gate oxide high voltage NMOS transistor (HVNM 9), a tenth thin gate oxide high voltage NMOS transistor (HVNM 10), and an eleventh thin gate oxide high voltage NMOS transistor (HVNM 11);
the grid electrode of the third PMOS tube (PM 3) is connected with the drain electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube (PM 4), the source electrode of the third PMOS tube is connected with the power supply Voltage (VCC), and the drain electrode of the third PMOS tube is connected with the source electrode of the sixth thin gate oxide high-voltage PMOS tube (HVPM 6); the source electrode of the fourth PMOS tube (PM 4) is connected with a power supply Voltage (VCC), and the drain electrode of the fourth PMOS tube (PM 7) is connected with the source electrode of the seventh thin gate oxide layer high-voltage PMOS tube (HVPM 7); the grid electrode of the sixth thin gate oxide layer high-voltage PMOS tube (HVPM 6) is connected with the drain electrode of the sixth thin gate oxide layer high-voltage PMOS tube (HVPM 7) and the grid electrode of the seventh thin gate oxide layer high-voltage PMOS tube (HVPM 7), and the drain electrode of the seventh thin gate oxide layer high-voltage NMOS tube (HVNM 7) and the drain electrode of the eighth thin gate oxide layer high-voltage NMOS tube (HVNM 8); the grid electrode of the seventh thin gate oxide layer high-voltage NMOS tube (HVNM 7) is connected with a first control signal (VSW 1), and the source electrode of the seventh thin gate oxide layer high-voltage NMOS tube is connected with a second current mirror (I2); the grid electrode of the eighth thin gate oxide layer high-voltage NMOS tube (HVNM 8) is connected with a forward pulse signal (VPL), and the source electrode is grounded; the grid electrode of the ninth thin gate oxide layer high-voltage NMOS tube (HVNM 9) is connected with the drain electrode of the ninth thin gate oxide layer high-voltage NMOS tube (HVNM 10) and the grid electrode of the tenth thin gate oxide layer high-voltage NMOS tube (HVNM 10), and the source electrode of the ninth thin gate oxide layer high-voltage NMOS tube is connected with the drain electrode of the third NMOS tube (NM 3); the source electrode of the tenth thin gate oxide high-voltage NMOS tube (HVNM 10) is connected with the drain electrode of the fourth NMOS tube (NM 4), and the drain electrode is connected with the second grid Voltage (VPG); the grid electrodes of the third NMOS tube (NM 3) and the fourth NMOS tube (NM 4) are connected with each other, and the source electrodes are grounded; the grid electrode of the eighth thin gate oxide high-voltage PMOS tube (HVPM 8) and the grid electrode of the ninth thin gate oxide high-voltage PMOS tube (HVPM 9) are both connected with a third control signal (VSW 3), the source electrode of the eighth thin gate oxide high-voltage PMOS tube (HVPM 8) and the source electrode of the ninth thin gate oxide high-voltage PMOS tube (HVPM 9) are both connected with a power supply Voltage (VCC), the drain electrode of the eighth thin gate oxide high-voltage PMOS tube (HVPM 8) is connected with the grid electrode of the eleventh thin gate oxide high-voltage NMOS tube (HVNM 11) and the second source Voltage (VPS), and the drain electrode of the ninth thin gate oxide high-voltage PMOS tube (HVPM 9) is connected with the grid electrode of the fifth PMOS tube (PM 5) and the second gate Voltage (VPG); the grid electrode of the sixth PMOS tube (PM 6) is connected with the drain electrode of the sixth PMOS tube and the source electrode of the fifth PMOS tube (PM 5), and the source electrode of the eleventh thin gate oxide layer high-voltage NMOS tube (HVNM 11) is connected with the source electrode; the grid electrode of the fifth PMOS tube (PM 5) is connected with the drain electrode of the fifth PMOS tube and the second grid Voltage (VPG); the drain electrode of the eleventh thin gate oxide high-voltage NMOS tube (HVNM 11) is connected with a power supply Voltage (VCC).
6. The control circuit for a high voltage switch based on a thin gate oxide process of claim 5, wherein,
by adjusting the sizes of the fifth PMOS tube (PM 5), the sixth PMOS tube (PM 6) and the eleventh thin gate oxide layer high-voltage NMOS tube (HVNM 11) and the current magnitude of the second current mirror (I2), the pressure difference between VPS and VPG is in the pressure resistant range of the first thin gate oxide layer high-voltage PMOS tube (HVPM 1) and the second thin gate oxide layer high-voltage PMOS tube (HVPM 2), so that the first thin gate oxide layer high-voltage PMOS tube (HVPM 1) and the second thin gate oxide layer high-voltage PMOS tube (HVPM 2) are kept to be safely opened.
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