CN110086455B - Novel switch circuit structure - Google Patents
Novel switch circuit structure Download PDFInfo
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- CN110086455B CN110086455B CN201910276924.7A CN201910276924A CN110086455B CN 110086455 B CN110086455 B CN 110086455B CN 201910276924 A CN201910276924 A CN 201910276924A CN 110086455 B CN110086455 B CN 110086455B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08116—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in composite switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
Abstract
The invention discloses a novel switch circuit structure, which comprises a signal input end, a signal output end, a control signal input end, a main switch circuit, a voltage division circuit and n switch control circuits, wherein the signal input end is connected with the signal output end; the main switch circuit comprises n field effect transistors which are sequentially connected in series, the switch circuit is provided with n-1 series nodes, and a connecting node between two field effect transistors which are connected in series is a series node of the switch circuit; the voltage division circuit is provided with n-1 output ends, the input end of the voltage division circuit is connected with the signal input end, and the n-1 output ends of the voltage division circuit are respectively connected with n-1 series nodes of the switch circuit; the input end of each switch control circuit is connected with the signal input end, the output end of each switch control circuit is respectively connected with the grid electrode of each field effect tube, the control end of each switch control circuit is connected with the control signal input end, and each switch control circuit is controlled by the control signal input end. The invention has the advantages of simple structure and high voltage withstanding value.
Description
Technical Field
The present invention relates to the field of electronic circuits, and more particularly, to a novel switch circuit structure.
Background
There are two main types of switch circuits commonly used at present.
As shown in fig. 1, the existing first switch circuit mainly includes a signal input end VIN ', a signal output end OUT', a field-effect tube Q1', a switch control circuit, and a control signal input end CTRL', wherein a first end of the field-effect tube Q1 'is connected to the signal input end VIN', a second end of the field-effect tube Q1 'is connected to the signal output end OUT', a control end of the field-effect tube Q1 'is connected to an output end of the switch control circuit, an input end of the switch control circuit is connected to the control signal input end CTRL', and the switch control circuit controls on/off of the field-effect tube Q1 'according to a control signal input by the control signal input end CTRL'; in the first conventional switching circuit, the field-effect transistor Q1' has a parasitic diode D1', and the positive and negative electrodes of the parasitic diode D1' are respectively connected to the second end and the first end of the field-effect transistor Q1', so that when the field-effect transistor Q1' is turned off, the reverse voltage borne by the parasitic diode D1' of the field-effect transistor Q1' is the input voltage input by the signal input terminal VIN ', and thus the maximum withstand voltage value of the first conventional switching circuit is the reverse breakdown voltage of the parasitic diode D1', and thus the reverse breakdown voltage of the parasitic diode D1' limits the input voltage range of the signal input terminal VIN '.
As shown in fig. 2, the conventional second switch circuit mainly includes a signal input terminal VIN ', a signal output terminal OUT ', a field-effect tube Q2', a field-effect tube Q3', a switch control circuit, and a control signal input terminal CTRL ', wherein a first end of the field-effect tube Q2' is connected to the signal input terminal VIN ', a second end of the field-effect tube Q2' is connected to the first end of the field-effect tube Q3', a second end of the field-effect tube Q3' is connected to the signal output terminal OUT ', positive and negative poles of a parasitic diode D2' of the field-effect tube Q2' are respectively connected to the first end and the second end of the field-effect tube Q2', positive and negative poles of a parasitic diode D3' of the field-effect tube Q3' are respectively connected to the second end and the first end of the field-effect tube Q3', a control terminal of the field-effect tube Q2' and a control terminal of the field-effect tube Q3' are connected to an output terminal of the switch control circuit, an input terminal of the switch control signal input terminal CTRL ' of the switch control circuit, and the switch control circuit simultaneously controls the on and off of the field-effect tube Q2' and the field-effect tube Q3' according to a control signal input from the control signal input terminal CTRL '; in the second conventional switching circuit, when the fet Q2 'and the fet Q3' are turned off simultaneously, the voltage at the first end of the fet Q3 'is the input voltage of the signal input terminal VIN' minus the on-state voltage of the parasitic diode D2', and the reverse voltage borne by the parasitic diode D3' of the fet Q3 'is the voltage at the first end of the fet Q3', so the maximum breakdown voltage of the second conventional switching circuit is the reverse breakdown voltage of the parasitic diode D3 'plus the on-state voltage of the parasitic diode D2', and the on-state voltage of the parasitic diode D2 'is negligible and small, so the maximum breakdown voltage of the second conventional switching circuit can be regarded as the reverse breakdown voltage of the parasitic diode D3', and thus the reverse breakdown voltage of the parasitic diode D3 'limits the input voltage range of the signal input terminal VIN'.
Disclosure of Invention
The invention aims to provide a novel switch circuit structure which has the advantages of simple structure and high voltage withstanding value.
In order to achieve the above purpose, the solution of the invention is:
a novel switch circuit structure comprises a signal input end, a signal output end, a control signal input end, a main switch circuit, a voltage division circuit and n switch control circuits, wherein n is a positive integer greater than or equal to 2; the main switch circuit comprises n field effect transistors which are sequentially connected in series, and the switch circuit is provided with n-1 series nodes; the field effect transistors are respectively provided with a parasitic diode, and the anode and the cathode of the parasitic diode of each field effect transistor are respectively connected with the drain electrode and the source electrode of the field effect transistor; the source electrode of the first field effect transistor is the input end of the switch circuit, the input end of the switch circuit is connected with the signal input end, the drain electrode of the nth field effect transistor is the output end of the switch circuit, the output end of the switch circuit is connected with the signal output end, and the connection node between the two field effect transistors which are connected in series is a series connection node of the switch circuit; the voltage division circuit is provided with n-1 output ends, the input end of the voltage division circuit is connected with the signal input end, and the n-1 output ends of the voltage division circuit are respectively connected with n-1 series nodes of the switch circuit; the input end of each switch control circuit is connected with the signal input end, the output end of each switch control circuit is respectively connected with the grid electrode of each field effect tube, the control end of each switch control circuit is connected with the control signal input end, and each switch control circuit is controlled by the control signal input end; when the control signal input by the control signal input end is enabled, each switch control circuit controls the field effect transistor connected with the switch control circuit to be conducted, and simultaneously, each switch control circuit controls the absolute value of the voltage difference between the grid electrode and the source electrode of the field effect transistor connected with the switch control circuit to be smaller than the grid-source breakdown voltage of the field effect transistor connected with the switch control circuit; when the control signal input by the control signal input end is not enabled, each switch control circuit controls the field effect transistor connected with the switch control circuit to be turned off, and simultaneously, each switch control circuit controls the absolute value of the voltage difference between the grid electrode and the source electrode of the field effect transistor connected with the switch control circuit to be smaller than the grid-source breakdown voltage of the field effect transistor connected with the switch control circuit; meanwhile, the voltage division circuit controls the voltage of each series node of the switch circuit so that the absolute value of the voltage difference between the source electrode and the drain electrode of each field effect tube is smaller than or equal to the reverse breakdown voltage of a parasitic diode of the field effect tube.
The model parameters of the field effect transistors are the same.
The voltage division circuit comprises n voltage division resistors which are sequentially connected in series, wherein the input end of the first voltage division resistor is the input end of the voltage division circuit, and the output end of the nth voltage division resistor is grounded; and a connecting node between the two series-connected voltage-dividing resistors is an output end of the voltage-dividing circuit.
The voltage division circuit comprises n voltage division diodes which are sequentially connected in series, wherein the anode of the first voltage division diode is the input end of the voltage division circuit, and the cathode of the nth voltage division diode is grounded; and a connecting node between the two voltage division diodes connected in series is an output end of the voltage division circuit.
Each switch control circuit comprises an LDO voltage stabilizing circuit, a secondary switch circuit, a first resistor, a second resistor, a third resistor, a fourth resistor, a first MOS (metal oxide semiconductor) tube and a second MOS tube; the input end of the LDO voltage stabilizing circuit is connected with one end of the first resistor and one end of the third resistor, the output end of the LDO voltage stabilizing circuit is connected with the input end of the secondary switching circuit, and the output end of the secondary switching circuit is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube; the other end of the first resistor is connected with one end of a second resistor, the other end of the second resistor is connected with the source electrode of the first MOS tube, the other end of the third resistor is connected with one end of a fourth resistor, the drain electrode of the first MOS tube and the source electrode of the second MOS tube, and the other end of the fourth resistor is connected with the drain electrode of the second MOS tube and is grounded;
the common node of the LDO voltage stabilizing circuit, the first resistor and the third resistor is the input end of the switch control circuit, the control end of the secondary switch circuit is the control end of the switch control circuit, and the common node of the first resistor and the second resistor is the output end of the switch control circuit.
After the scheme is adopted, the novel switch circuit structure has few devices and simple structure, and the withstand voltage value of the novel switch circuit structure is the sum of reverse breakdown voltages of parasitic diodes of field effect transistors, so that the novel switch circuit structure has high withstand voltage value.
Drawings
FIG. 1 is a schematic circuit diagram of a first prior art switching circuit;
FIG. 2 is a circuit diagram of a second conventional switch circuit;
FIG. 3 is an overall circuit schematic of the present invention;
FIG. 4 is a circuit diagram of the switch control circuit of the present invention;
fig. 5 is a circuit diagram of an embodiment of the present invention (n is 2).
Detailed Description
In order to further explain the technical solution of the present invention, the present invention is explained in detail by the following specific examples.
As shown in fig. 3, the present invention discloses a novel switch circuit structure, which includes a signal input terminal VIN, a signal output terminal OUT, a control signal input terminal CTRL, a switch circuit 1, a voltage divider circuit 2, and n switch control circuits 31, 32 … … n, where n is a positive integer greater than or equal to 2.
The main switch circuit 1 comprises n field effect transistors Q1 and Q2 … … Qn which are sequentially connected in series, and the switch circuit 1 is provided with n-1 series nodes A1 and A2 … … An-1; each field effect tube Q1 and Q2 … … Qn is respectively provided with a parasitic diode D1 and D2 … … Dn, and the anode and the cathode of the parasitic diode of each field effect tube are respectively connected with the drain electrode and the source electrode of the field effect tube; the source electrode of the first field effect transistor Q1 is the input end of the switch circuit 1, the input end of the switch circuit 1 is connected with the signal input end VIN, the drain electrode of the nth field effect transistor Qn is the output end of the switch circuit 1, the output end of the switch circuit 1 is connected with the signal output end OUT, and the connection node between the two field effect transistors in series connection is a series connection node of the switch circuit. Wherein the model parameters of each field effect tube are the same; as shown in fig. 3, each fet is a PMOS transistor.
The voltage division circuit 2 is used for controlling the voltage of each series node A1 and A2 … … An-1 of the switch circuit 1, and further controlling the absolute value of the voltage difference between the source and the drain of each field effect transistor Q1 and Q2 … … Qn; the voltage division circuit 2 is provided with n-1 output ends, the input end of the voltage division circuit 2 is connected with the signal input end VIN, and the n-1 output ends of the voltage division circuit 2 are respectively connected with n-1 series nodes A1 and A2 … … An-1 of the switch circuit 1. As shown in fig. 3, the voltage divider circuit 2 may be a resistive voltage divider circuit, specifically, the voltage divider circuit 2 includes n voltage divider resistors R1 and R2 … … Rn connected in series in sequence, where an input terminal of the first voltage divider resistor R1 is an input terminal of the voltage divider circuit 2, and an output terminal of the nth voltage divider resistor Rn is grounded; the connection node between the two series-connected voltage-dividing resistors is an output end of the voltage-dividing circuit 2. The voltage dividing circuit 2 is not limited to a resistance type voltage dividing circuit, and may also be a diode voltage dividing circuit, specifically, the voltage dividing circuit includes n voltage dividing diodes connected in series in sequence, wherein the anode of the first voltage dividing diode is the input end of the voltage dividing circuit, and the cathode of the nth voltage dividing diode is grounded; and a connecting node between the two voltage division diodes connected in series is an output end of the voltage division circuit.
Each of the switch control circuits 31 and 32 … … n is used for respectively controlling the on-off of each field effect transistor Q1 and Q2 … … Qn; the input end of each switch control circuit 31, 32 … … n is connected to the signal input end VIN, the output end of each switch control circuit 31, 32 … … n is connected to the gate of each field effect transistor Q1, Q2 … … Qn, the control end of each switch control circuit 31, 32 … … n is connected to the control signal input end CTRL, and each switch control circuit 31, 32 … … n is controlled by the control signal input end CTRL. As shown in fig. 4, each switch control circuit includes an LDO voltage regulator circuit 301, a secondary switch circuit 301, a first resistor r1, a second resistor r2, a third resistor r3, a fourth resistor r4, a first MOS transistor M1, and a second MOS transistor M2; the input end of the LDO voltage stabilizing circuit 301 is connected with one end of the first resistor r1 and one end of the third resistor r3, the output end of the LDO voltage stabilizing circuit 301 is connected with the input end of the secondary switching circuit 302, and the output end of the secondary switching circuit 302 is connected with the grid electrode of the first MOS transistor M1 and the grid electrode of the second MOS transistor M2; the other end of the first resistor r1 is connected with one end of a second resistor r2, the other end of the second resistor r2 is connected with the source electrode of the first MOS transistor M1, the other end of the third resistor r3 is connected with one end of a fourth resistor r4, the drain electrode of the first MOS transistor M1 and the source electrode of the second MOS transistor M2, and the other end of the fourth resistor r4 is connected with the drain electrode of the second MOS transistor M2 and is grounded; the common node of the LDO voltage stabilizing circuit 301, the first resistor r1, and the third resistor r3 is an input terminal of the switch control circuit, the control terminal of the secondary switch circuit 302 is a control signal input terminal of the switch control circuit, and the common node of the first resistor r1 and the second resistor r2 is an output terminal of the switch control circuit. The secondary switch circuit 302 may adopt a triode switch circuit or a MOS transistor switch circuit, and the secondary switch circuit 302 is turned on and off by a control signal input from the control signal input terminal CTRL; the turn-on and turn-off of the secondary switch circuit 302 can enable the output end of the switch control circuit to output different voltages, and further enable each switch control circuit to control the turn-on and turn-off of the field effect transistor connected with the switch control circuit.
When a control signal input by a control signal input end CTRL is enabled, each switch control circuit controls the field-effect tube connected with the switch control circuit to be conducted, and simultaneously, each switch control circuit controls the absolute value of the voltage difference between the grid electrode and the source electrode of the field-effect tube connected with the switch control circuit to be smaller than the grid-source breakdown voltage of the field-effect tube connected with the switch control circuit, so that the field-effect tube is protected. When a control signal input by a control signal input end CTRL is not enabled, each switch control circuit controls a field-effect tube connected with the switch control circuit to be turned off, and simultaneously, each switch control circuit controls the absolute value of the voltage difference between a grid electrode and a source electrode of the field-effect tube connected with the switch control circuit to be smaller than the grid-source breakdown voltage of the field-effect tube connected with the switch control circuit so as to protect the field-effect tube; meanwhile, the voltage divider circuit controls the voltage of each series node of the switch circuit to enable the absolute value of the voltage difference between the source electrode and the drain electrode of each field-effect tube to be less than or equal to the reverse breakdown voltage of the parasitic diode of the field-effect tube, so that the parasitic diode of each field-effect tube is protected from being broken down, and the withstand voltage value of the novel switch circuit structure is the sum of the reverse breakdown voltages of the parasitic diodes of the field-effect tubes. The voltage division ratio of the voltage division circuit 2 is set according to the reverse breakdown voltage of the parasitic diode of each field effect transistor and the input voltage of the signal input end VIN, so that when each field effect transistor is turned off, the absolute value of the voltage difference between the drain electrode and the source electrode of each field effect transistor is less than or equal to the reverse breakdown voltage of the parasitic diode of the field effect transistor; in addition, according to the input voltage of the signal input end VIN, the conduction voltage drop of each field effect tube and the voltage division ratio of the voltage division circuit 2, the source voltage when each field effect tube is conducted and the source voltage when each field effect tube is turned off can be obtained, so that according to the input voltage of the signal input end VIN, the source voltage when each field effect tube is conducted, the source voltage when each field effect tube is turned off and the conduction voltage of each field effect tube, the resistance values of the first resistor r1, the second resistor r2, the third resistor r3 and the fourth resistor r4 of each switch control circuit can be set, when a control signal input by the control signal input end CTRL is enabled, the voltage output by the output end of each switch control circuit can control the field effect tube connected with the switch control circuit to be conducted and can control the voltage difference between the gate and the source of the field effect tube connected with the switch control circuit to be smaller than the gate-source breakdown voltage of the field effect tube connected with the switch control circuit, and when the control signal input by the control signal input end CTRL is disabled, the voltage output by each switch control circuit can control the voltage connected with the gate-source breakdown voltage of the field effect tube connected with the switch control circuit to be smaller than the gate-source breakdown voltage of the gate-source control circuit.
As shown in fig. 5, when n is equal to 2, the first field-effect transistor Q1 and the second field-effect transistor Q2 are both PMOS transistors, the gate-source breakdown voltages of the first field-effect transistor Q1 and the second field-effect transistor Q2 are both 3V, the turn-on voltages of the first field-effect transistor Q1 and the second field-effect transistor Q2 are both 0V, and the reverse breakdown voltage of the parasitic diode D1 and the reverse breakdown voltage of the parasitic diode D2 are both 3V, the voltage drop when the first field-effect transistor Q1 and the second field-effect transistor Q2 are turned on is ignored, and the influence of the output voltage of the voltage divider circuit 2 on the series node A1 when the first field-effect transistor Q1 and the second field-effect transistor Q2 are turned on is ignored, so that the withstand voltage value of the novel switch circuit structure of the present invention is 6V, that is, the maximum, of the input voltage of the signal input terminal VIN, is 6V; when the input voltage of the signal input end VIN is 6V, if the control signal input by the control signal input end CTRL is enabled, the first switch control circuit 31 controls the gate voltage of the first field-effect tube Q1 to be 3V, so that the first field-effect tube Q1 is turned on, the second switch control circuit 32 controls the gate voltage of the second field-effect tube Q2 to be 3V, so that the second field-effect tube Q2 is turned on, at this time, the voltage of the series node A1 is 6V, the voltage of the signal output end OUT is also 6V, the absolute value of the voltage difference between the gate and the source of the first field-effect tube Q1 and the absolute value of the voltage difference between the gate and the source of the second field-effect tube Q2 are both 3V, and the first field-effect tube Q1 and the second field-effect tube Q2 are not broken down; when the input voltage of the signal input end VIN is 6V, if the control signal input by the control signal input end CTRL is not enabled, the first switch control circuit 31 controls the gate voltage of the first field-effect transistor Q1 to be 6V, so that the field-effect transistor Q1 is turned off, the ratio of the voltage-dividing resistor R1 and the voltage-dividing resistor R2 of the voltage-dividing circuit 2 is one to two, so that the voltage of the series node A1 is 3V, the second switch control circuit 32 controls the gate voltage of the second field-effect transistor Q2 to be 4V, so that the second field-effect transistor Q2 is turned off, at this time, the voltage of the signal output end OUT is 0V, the absolute value of the voltage difference between the gate and the source of the first field-effect transistor Q1 and the absolute value of the voltage difference between the gate and the source of the second field-effect transistor Q2 are both less than 3V, the first field-effect transistor Q1 and the second field-effect transistor Q2 cannot be broken down, the reverse voltage borne by the parasitic diode D1 of the first field-effect transistor Q1 and the parasitic diode D2 are both 3V, and the parasitic diode D1 and the parasitic diode cannot be broken down.
The above embodiments and drawings are not intended to limit the form and style of the present invention, and any suitable changes or modifications thereof by those skilled in the art should be considered as not departing from the scope of the present invention.
Claims (5)
1. A novel switch circuit structure is characterized in that: the circuit comprises a signal input end, a signal output end, a control signal input end, a main switch circuit, a voltage division circuit and n switch control circuits, wherein n is a positive integer greater than or equal to 2;
the main switching circuit comprises n field effect transistors which are sequentially connected in series, and the switching circuit is provided with n-1 series nodes; the field effect transistors are respectively provided with a parasitic diode, and the anode and the cathode of the parasitic diode of each field effect transistor are respectively connected with the drain electrode and the source electrode of the field effect transistor; the source electrode of the first field effect transistor is the input end of the switch circuit, the input end of the switch circuit is connected with the signal input end, the drain electrode of the nth field effect transistor is the output end of the switch circuit, the output end of the switch circuit is connected with the signal output end, and the connection node between the two field effect transistors which are connected in series is a series node of the switch circuit;
the voltage division circuit is provided with n-1 output ends, the input end of the voltage division circuit is connected with the signal input end, and the n-1 output ends of the voltage division circuit are respectively connected with n-1 series nodes of the switch circuit;
the input end of each switch control circuit is connected with the signal input end, the output end of each switch control circuit is respectively connected with the grid of each field effect transistor, the control end of each switch control circuit is connected with the control signal input end, and each switch control circuit is controlled by a control signal input by the control signal input end;
when the control signal input by the control signal input end is enabled, each switch control circuit controls the field effect transistor connected with the switch control circuit to be conducted, and simultaneously, each switch control circuit controls the absolute value of the voltage difference between the grid electrode and the source electrode of the field effect transistor connected with the switch control circuit to be smaller than the grid-source breakdown voltage of the field effect transistor connected with the switch control circuit;
when the control signal input by the control signal input end is not enabled, each switch control circuit controls the field effect transistor connected with the switch control circuit to be turned off, and simultaneously, each switch control circuit controls the absolute value of the voltage difference between the grid electrode and the source electrode of the field effect transistor connected with the switch control circuit to be smaller than the grid-source breakdown voltage of the field effect transistor connected with the switch control circuit; meanwhile, the voltage division circuit controls the voltage of each series node of the switch circuit so that the absolute value of the voltage difference between the source electrode and the drain electrode of each field effect tube is smaller than or equal to the reverse breakdown voltage of a parasitic diode of the field effect tube.
2. A novel switching circuit arrangement, as claimed in claim 1, characterized in that: the model parameters of the field effect transistors are the same.
3. A novel switching circuit arrangement as claimed in claim 1 or 2, characterized in that: the voltage division circuit comprises n voltage division resistors which are sequentially connected in series, wherein the input end of the first voltage division resistor is the input end of the voltage division circuit, and the output end of the nth voltage division resistor is grounded; and a connecting node between the two series-connected voltage-dividing resistors is an output end of the voltage-dividing circuit.
4. A novel switching circuit arrangement as claimed in claim 1 or 2, characterized in that: the voltage division circuit comprises n voltage division diodes which are sequentially connected in series, wherein the anode of the first voltage division diode is the input end of the voltage division circuit, and the cathode of the nth voltage division diode is grounded; and a connecting node between the two voltage division diodes connected in series is an output end of the voltage division circuit.
5. A novel switching circuit arrangement, as claimed in claim 1, characterized in that: each switch control circuit comprises an LDO voltage stabilizing circuit, a secondary switch circuit, a first resistor, a second resistor, a third resistor, a fourth resistor, a first MOS (metal oxide semiconductor) tube and a second MOS tube;
the input end of the LDO voltage stabilizing circuit is connected with one end of the first resistor and one end of the third resistor, the output end of the LDO voltage stabilizing circuit is connected with the input end of the secondary switching circuit, and the output end of the secondary switching circuit is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube; the other end of the first resistor is connected with one end of a second resistor, the other end of the second resistor is connected with the source electrode of the first MOS tube, the other end of the third resistor is connected with one end of a fourth resistor, the drain electrode of the first MOS tube and the source electrode of the second MOS tube, and the other end of the fourth resistor is connected with the drain electrode of the second MOS tube and is grounded;
the common node of the LDO voltage stabilizing circuit, the first resistor and the third resistor is the input end of the switch control circuit, the control end of the secondary switch circuit is the control end of the switch control circuit, and the common node of the first resistor and the second resistor is the output end of the switch control circuit.
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| CN110861646A (en) * | 2019-11-11 | 2020-03-06 | 北京长城华冠汽车科技股份有限公司 | Gear shifting system and gear shifting method of electric automobile |
| CN112383296B (en) * | 2020-11-13 | 2024-03-29 | 奇普电源(常州)有限公司 | Bidirectional combined switch |
| CN112653430B (en) * | 2020-11-24 | 2022-09-06 | 国创移动能源创新中心(江苏)有限公司 | Charging pile and negative pressure driving circuit of power switch tube thereof |
| CN117389370B (en) * | 2023-12-11 | 2024-03-01 | 辰芯半导体（深圳）有限公司 | Voltage output circuit and chip |
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| JP3037224B2 (en) * | 1997-09-30 | 2000-04-24 | 山形日本電気株式会社 | Tri-level input buffer circuit |
| JP2008263523A (en) * | 2007-04-13 | 2008-10-30 | Renesas Technology Corp | High frequency switch circuit |
| CN202475386U (en) * | 2012-02-09 | 2012-10-03 | 赵恩海 | Self-adaptive bidirectional analog switch circuit |
| CN103312309B (en) * | 2013-05-14 | 2016-01-13 | 无锡华润矽科微电子有限公司 | Analog switch control circuit structure |
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