CN110289848A - Voltage level converting - Google Patents
Voltage level converting Download PDFInfo
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- CN110289848A CN110289848A CN201910476088.7A CN201910476088A CN110289848A CN 110289848 A CN110289848 A CN 110289848A CN 201910476088 A CN201910476088 A CN 201910476088A CN 110289848 A CN110289848 A CN 110289848A
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- 230000005611 electricity Effects 0.000 claims abstract description 14
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses a kind of voltage level convertings, comprising: the pull-up circuit and pull-down circuit being connected between the first supply voltage and ground；The link position of the low pressure, input end connection low voltage input signal of pull-down circuit, pull-up circuit and pull-down circuit is high-voltage output end and output High voltage output signal, the first supply voltage are higher than the second source voltage；When second source voltage is lower than predetermined voltage, voltage level converting does not work and High voltage output signal is fixedly attached to ground or the first supply voltage；It include switching tube in pull-down circuit, switching tube is connected when second source voltage is more than or equal to predetermined voltage, and the guiding path formed between the first supply voltage and ground to avoid upper pull-down circuit is disconnected when second source voltage is lower than predetermined voltage.The present invention can prevent from generating high voltage power supply during economize on electricity to the conductive path between ground, realize good energy-saving effect.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit (IC), more particularly to a kind of voltage level converting.
Background technique
With the development of integrated circuit, the Typical operating voltages inside IC are about 1V or so, outside IC chip, power supply electricity
Pressure still can be 1.8V, 2.5V or 3.3V, to adapt to various application scenarios, need to use level voltage conversion circuit by IC
Internal low-voltage signal is converted to corresponding IC external high pressure signal, and the high-voltage signal outside IC is converted to corresponding low inside IC
Press signal.
As shown in Figure 1, being the circuit diagram of existing voltage level converting, existing level voltage converter includes:
A pair of of high voltage PMOS pipe P1, P2, a pair of of low voltage nmos transistor N1, N2 and a pair of of high pressure NMOS pipe N5 and N6 are high
The Native NMOS tube for pressing NMOS tube N5 and N6 that threshold voltage is all used to tend to 0V；PMOS tube P1 and NMOS tube N1 and N5 are the
One supply voltage, that is, connect between high pressure VH and ground VSS, PMOS tube P2 and NMOS tube N2 and N6 go here and there between high pressure VH and ground VSS
Connection, the grid of PMOS tube P1 are connected with the drain electrode of NMOS tube N6 and the drain electrode of PMOS tube P2, the grid and NMOS tube of PMOS tube P2
N5 is connected with the drain electrode of PMOS tube P1, is connected to second source voltage by PMOS tube P5 and NMOS tube the N8 phase inverter formed of connecting
That is between low pressure VL and ground VSS, input signal IN_PL be connected to NMOS tube N1 and N5 grid and phase inverter input terminal i.e.
The grid of PMOS tube P5 and the grid of NMOS tube N8, the drain electrode of the output end, that is, PMOS tube P5 and NMOS tube N8 of phase inverter are as anti-
Input signal IN_NL after phase is connected to the grid of NMOS tube N2 and N6, and the drain electrode of NMOS tube N6 and the drain electrode of PMOS tube P2 connect
It is connected together and the output end as output signal OUTP, output signal OUTP is also connected with the drain electrode of NMOS tube N7, NMOS tube
The grid of N7 is connected to high voltage control signal POC_PH, the source electrode ground connection of NMOS tube N7.The drain electrode of NMOS tube N5 and PMOS tube P1
Drain electrode output end of the connecting pin as output signal OUTN.Output signal OUTN and OUTP are a pair of of inversion signal.
When using energy-saving mode inside IC, the size of low pressure VL, which is reduced to, can only maintain data in IC internal storage
Current potential, reducing supply voltage, that is, low pressure VL can achieve the purpose that reduce IC internal power consumption.The output end of level translator in Fig. 1
OUT is connected to ground VSS, the high voltage control signal that the grid of NMOS tube N7 is generated by power sense circuit by the NMOS tube N7 of high pressure
POC_PH is controlled, and when low pressure VL is lower than predetermined voltage, high voltage control signal POC_PH is logically high, NMOS tube N7 unlatching,
Output signal OUT is pulled to ground VSS current potential, and PMOS tube P1 is opened at this time, and output signal IN remains high pressure VH；Due to internal electricity
Road does not work, and the voltage of input signal IN_PL floats, and there is the case where opening NMOS tube N1 and N5, namely the input letter to float
Number IN_PL is there is a possibility that NMOS tube N1 and N5 are opened, and at this moment, the tandem paths being made of PMOS tube P1, NMOS tube N1 and N5 is complete
Portion's conducting, thus will appear by PMOS tube P1, NMOS tube N1 and N5 form slave high pressure VH to the electric leakage of ground VSS, namely saving
During electricity, it is undesirable to electric current may circulate PMOS tube P1 and NMOS tube N1, N5, violated energy-efficient purpose.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of voltage level converting, can prevent from producing during economize on electricity
Raw high voltage power supply realizes good energy-saving effect to the conductive path between ground.
In order to solve the above technical problems, voltage level converting provided by the invention includes:
The pull-up circuit and pull-down circuit being connected between the first supply voltage and ground.
The low pressure, input end connection low voltage input signal of the pull-down circuit, the pull-up circuit and the pull-down circuit
Link position is high-voltage output end and output High voltage output signal, the size of the low voltage input signal are located at second source voltage
Between ground, the size of the High voltage output signal is between first supply voltage and ground；First supply voltage
Higher than the second source voltage.
When the second source voltage is lower than predetermined voltage, voltage level converting does not work and the High voltage output
Signal is fixedly attached to ground or first supply voltage.
It include switching tube in the pull-down circuit, the switching tube is more than or equal to described in the second source voltage
It is connected when predetermined voltage, the switching tube is disconnected when the second source voltage is lower than predetermined voltage to avoid the pull-up electricity
The guiding path that road and the pull-down circuit are formed between first supply voltage and ground.
A further improvement is that the level shifting circuit provides level conversion for the signal in integrated circuit.
A further improvement is that the predetermined voltage is the IC chip when being energy-saving mode corresponding voltage,
In the energy-saving mode, the second source voltage drop is as low as the electricity for guaranteeing to maintain the data in the IC chip
Position, the predetermined voltage are more than or equal to the current potential for maintaining the data in the IC chip.
A further improvement is that the external operating voltage of the IC chip is greater than internal operating voltages.
A further improvement is that the pull-up circuit includes the first PMOS tube.
A further improvement is that the pull-down circuit includes the first NMOS tube.
A further improvement is that the pull-up circuit and the pull-down circuit are all differential configuration.
A further improvement is that the pull-up circuit further includes the second PMOS tube, the pull-down circuit further includes second
NMOS tube.
The source electrode of first PMOS tube and the source electrode of second PMOS tube all connect first supply voltage.
The drain electrode of first PMOS tube and the drain electrode of first NMOS tube are all connected to the first high-voltage output end, described
First high-voltage output end exports the first High voltage output signal.
The drain electrode of second PMOS tube and the drain electrode of second NMOS tube are all connected to the second high-voltage output end, described
Second high-voltage output end exports the second High voltage output signal.
The grid of second PMOS tube connects the first High voltage output signal, the grid connection of first PMOS tube
The second High voltage output signal；The first High voltage output signal and the second High voltage output signal inversion.
A further improvement is that the source electrode of first NMOS tube and the source electrode of second NMOS tube are all connected to ground.
The grid of first NMOS tube connects the first low voltage input signal, the grid connection second of second NMOS tube
Low voltage input signal, first low voltage input signal and the second low voltage input signal reverse phase.
A further improvement is that the switching tube includes two, respectively third NMOS tube and the 4th NMOS tube.
The drain electrode of first NMOS tube is connected to first high-voltage output end by the third NMOS tube, and described
The source electrode of three NMOS tubes connects the drain electrode of first NMOS tube, and the drain electrode of the third NMOS tube is connected to first high pressure
Output end.
The drain electrode of second NMOS tube is connected to second high-voltage output end by the 4th NMOS tube, and described
The source electrode of four NMOS tubes connects the drain electrode of second NMOS tube, and the drain electrode of the 4th NMOS tube is connected to second high pressure
Output end.
The grid of the third NMOS tube and the grid of the 4th NMOS tube are all connected to the first control voltage, and described
One control voltage is the detection voltage of the second source voltage, when the second source voltage is lower than predetermined voltage when institute
State the first control voltage be low level, when the second source voltage be more than or equal to the predetermined voltage when described in first control electricity
Pressure is high level.
A further improvement is that the pull-down circuit further includes the 5th NMOS tube and the 6th NMOS tube.
The drain electrode of the third NMOS tube is connected to first high-voltage output end by the 5th NMOS tube, and described
The drain electrode of four NMOS tubes is connected to second high-voltage output end by the 6th NMOS tube.
The source electrode of 5th NMOS tube connects the drain electrode of the third NMOS tube, the drain electrode connection of the 5th NMOS tube
To first high-voltage output end.
The source electrode of 6th NMOS tube connects the drain electrode of the 4th NMOS tube, the drain electrode connection of the 6th NMOS tube
To second high-voltage output end.
The grid of 5th NMOS tube connects first low voltage input signal；The grid of 6th NMOS tube connects
Second low voltage input signal.
5th NMOS tube and the 6th NMOS tube are all Native NMOS tube.
A further improvement is that the pull-up circuit further includes third PMOS tube and the 4th PMOS tube；3rd PMOS
Pipe and the 4th PMOS tube are used to balance the electric current of the pull-up circuit with the pull-down circuit for being in series with the switching tube
Ability.
The drain electrode of first PMOS tube is connected to first high-voltage output end by the third PMOS tube, and described
The source electrode of three PMOS tube connects the drain electrode of first PMOS tube, and the drain electrode of the third PMOS tube is connected to first high pressure
Output end.
The drain electrode of second PMOS tube is connected to second high-voltage output end by the 4th PMOS tube, and described
The source electrode of four PMOS tube connects the drain electrode of second PMOS tube, and the drain electrode of the 4th PMOS tube is connected to second high pressure
Output end.
A further improvement is that the voltage level converting further includes the 7th NMOS tube, the 7th NMOS tube
Drain electrode connects second high-voltage output end, the source electrode ground connection of the 7th NMOS tube, the grid connection of the 7th NMOS tube
Second control voltage, the second control voltage and the first control voltage inversion.
The second control voltage is high level described in when the second source voltage is lower than the predetermined voltage, makes described the
Two High voltage output signals are fixedly attached to ground and the first High voltage output signal are made to be fixedly attached to first supply voltage.
7th NMOS tube described in when the second source voltage is more than or equal to the predetermined voltage disconnects.
A further improvement is that the voltage level converting further includes being connected by the 5th PMOS tube with the 8th NMOS tube
The source electrode of the phase inverter of formation, the 5th PMOS tube connects the second source voltage, and the source electrode of the 8th NMOS tube connects
Ground, the grid of the 5th PMOS tube and the grid of the 8th NMOS tube all connect first low voltage input signal, described
The drain electrode of 5th PMOS tube and the drain electrode of the 8th NMOS tube link together and export second low voltage input signal.
A further improvement is that first PMOS tube, second PMOS tube, the third PMOS tube, the described 4th
PMOS tube, the 5th NMOS tube, the 6th NMOS tube, the operating voltage of the 7th NMOS tube are all first power supply
Voltage.
First NMOS tube, second NMOS tube, the third NMOS tube, the 4th NMOS tube, the described 5th
The operating voltage of PMOS tube and the 8th NMOS tube is all the second source voltage.
The size of the first control voltage is between second source voltage and ground, the size of the second control voltage
Between first supply voltage and ground.
Voltage level converting of the present invention increases switching tube in pull-down circuit, and switching tube can be in the i.e. second electricity of low pressure
Source voltage disconnects when being lower than predetermined voltage, so as to prevent from generating high voltage power supply during economize on electricity to the conductive path between ground,
Realize good energy-saving effect；Switching tube of the invention can be held on when low pressure is more than or equal to predetermined voltage, therefore will not be right
The operation of circuit during normal operation has an adverse effect.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the circuit diagram of existing voltage level converting；
Fig. 2 is the circuit diagram of voltage level converting of the embodiment of the present invention.
Specific embodiment
As shown in Fig. 2, being the circuit diagram of voltage level converting of the embodiment of the present invention；Voltage level of the embodiment of the present invention
Conversion circuit includes:
The pull-up circuit 1 and pull-down circuit 2 being connected between the first supply voltage i.e. high pressure VH and ground VSS.
The low pressure, input end of the pull-down circuit 2 connects low voltage input signal, the pull-up circuit 1 and the pull-down circuit
2 link position is high-voltage output end and output High voltage output signal, the size of the low voltage input signal are located at second source
Voltage, that is, between low pressure VL and ground VSS, the size of the High voltage output signal be located at the first supply voltage VH and ground VSS it
Between；The first supply voltage VH is higher than the second source voltage VL.
When the second source voltage VL is lower than predetermined voltage, voltage level converting does not work and the high pressure is defeated
Signal is fixedly attached to ground first supply voltage of VSS or described VH out.
It include switching tube in the pull-down circuit 2, the switching tube is more than or equal in the second source voltage VL
It is connected when the predetermined voltage, the switching tube is disconnected when the second source voltage VL is lower than predetermined voltage to avoid described
The guiding path that pull-up circuit 1 and the pull-down circuit 2 are formed between the first supply voltage VH and ground VSS.
In the embodiment of the present invention, the level shifting circuit provides level conversion for the signal in integrated circuit.
The predetermined voltage is the IC chip corresponding voltage when being energy-saving mode, in the energy-saving mode
When, the second source voltage VL is reduced to the current potential for guaranteeing to maintain the data in the IC chip, described predetermined
Voltage is more than or equal to the current potential for maintaining the data in the IC chip.
The external operating voltage of the IC chip is greater than internal operating voltages.In the embodiment of the present invention, described
One supply voltage VH is the external operating voltage of the IC chip, and the second source voltage VL is the integrated circuit
The internal operating voltages of chip.
The pull-up circuit 1 includes the first PMOS tube P1.
The pull-down circuit 2 includes the first NMOS tube N1.
The pull-up circuit 1 and the pull-down circuit 2 are all differential configuration.The pull-up circuit 1 further includes the 2nd PMOS
Pipe P2, the pull-down circuit 2 further include the second NMOS tube N2.
The source electrode of the source electrode of the first PMOS tube P1 and the second PMOS tube P2 all connect first supply voltage
VH。
The drain electrode of the first PMOS tube P1 and the drain electrode of the first NMOS tube N1 are all connected to the first high-voltage output end,
First high-voltage output end exports the first High voltage output signal OUTN.
The drain electrode of the second PMOS tube P2 and the drain electrode of the second NMOS tube N2 are all connected to the second high-voltage output end,
Second high-voltage output end exports the second High voltage output signal OUTP.
The grid of the second PMOS tube P2 connects the first High voltage output signal OUTN, the first PMOS tube P1's
Grid connects the second High voltage output signal OUTP；The first High voltage output signal OUTN and second High voltage output letter
Number OUTP reverse phase.
The source electrode of the source electrode of the first NMOS tube N1 and the second NMOS tube N2 are all connected to ground VSS.
The grid of the first NMOS tube N1 connects the first low voltage input signal IN_PL, the grid of the second NMOS tube N2
Pole connects the second low voltage input signal IN_NL, the first low voltage input signal IN_PL and second low voltage input signal
IN_NL reverse phase.
The switching tube includes two, respectively third NMOS tube N3 and the 4th NMOS tube N4.
The drain electrode of the first NMOS tube N1 is connected to first high-voltage output end, institute by the third NMOS tube N3
The source electrode for stating third NMOS tube N3 connects the drain electrode of the first NMOS tube N1, and the drain electrode of the third NMOS tube N3 is connected to institute
State the first high-voltage output end.
The drain electrode of the second NMOS tube N2 is connected to second high-voltage output end, institute by the 4th NMOS tube N4
The source electrode for stating the 4th NMOS tube N4 connects the drain electrode of the second NMOS tube N2, and the drain electrode of the 4th NMOS tube N4 is connected to institute
State the second high-voltage output end.
The grid of the third NMOS tube N3 and the grid of the 4th NMOS tube N4 are all connected to the first control voltage
POC_NL, the detection voltage that the first control voltage POC_NL is the second source voltage VL is i.e. by second electricity
Source voltage VL carries out the testing result of detection formation, and detection generallys use power sense circuit realization；When the second source electricity
The first control voltage POC_NL is low level described in when VL being pressed to be lower than the predetermined voltage, when the second source voltage VL is greater than
The first control voltage POC_NL is high level described in when equal to the predetermined voltage.
It is preferably selected as, the pull-down circuit 2 further includes the 5th NMOS tube N5 and the 6th NMOS tube N6.
The drain electrode of the third NMOS tube N3 is connected to first high-voltage output end, institute by the 5th NMOS tube N5
The drain electrode for stating the 4th NMOS tube N4 is connected to second high-voltage output end by the 6th NMOS tube N6.
The source electrode of the 5th NMOS tube N5 connects the drain electrode of the third NMOS tube N3, the leakage of the 5th NMOS tube N5
Pole is connected to first high-voltage output end.
The source electrode of the 6th NMOS tube N6 connects the drain electrode of the 4th NMOS tube N4, the leakage of the 6th NMOS tube N6
Pole is connected to second high-voltage output end.
The grid of the 5th NMOS tube N5 connects the first low voltage input signal IN_PL；The 6th NMOS tube N6
Grid connect the second low voltage input signal IN_NL.
The 5th NMOS tube N5 and the 6th NMOS tube N6 is Native NMOS tube.In this field,
NativeNMOS pipe is usually the NMOS tube that threshold voltage tends to 0V.
The pull-up circuit 1 further includes third PMOS tube P3 and the 4th PMOS tube P4；The third PMOS tube P3 and described
4th PMOS tube P4 is used to balance the current capacity of the pull-up circuit 1 and the pull-down circuit 2 for being in series with the switching tube.
The drain electrode of the first PMOS tube P1 is connected to first high-voltage output end, institute by the third PMOS tube P3
The source electrode for stating third PMOS tube P3 connects the drain electrode of the first PMOS tube P1, and the drain electrode of the third PMOS tube P3 is connected to institute
State the first high-voltage output end.
The drain electrode of the second PMOS tube P2 is connected to second high-voltage output end, institute by the 4th PMOS tube P4
The source electrode for stating the 4th PMOS tube P4 connects the drain electrode of the second PMOS tube P2, and the drain electrode of the 4th PMOS tube P4 is connected to institute
State the second high-voltage output end.
The voltage level converting further includes the 7th NMOS tube N7, described in the drain electrode connection of the 7th NMOS tube N7
Second high-voltage output end, the source electrode of the 7th NMOS tube N7 are grounded VSS, the second control of grid connection of the 7th NMOS tube N7
Voltage POC_PH processed, the second control voltage POC_PH and the first control voltage POC_NL reverse phase.
The second control voltage POC_PH is high level described in when the second source voltage VL is lower than the predetermined voltage,
So that the second High voltage output signal OUTP is fixedly attached to ground VSS and is fixedly connected with the first High voltage output signal OUTN
To the first supply voltage VH.
7th NMOS tube N7 described in when the second source voltage VL is more than or equal to the predetermined voltage is disconnected.
The voltage level converting further includes connecting the reverse phase formed by the 5th PMOS tube P5 and the 8th NMOS tube N8
Device 3, the source electrode of the 5th PMOS tube P5 connect the second source voltage VL, the source electrode ground connection of the 8th NMOS tube N8
VSS, the grid of the 5th PMOS tube P5 and the grid of the 8th NMOS tube N8 all connect first low voltage input signal
The drain electrode of IN_PL, the 5th PMOS tube P5 and the drain electrode of the 8th NMOS tube N8 link together and export described second
Low voltage input signal IN_NL.
The first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the 4th PMOS tube P4,
The 5th NMOS tube N5, the 6th NMOS tube N6, the 7th NMOS tube N7 operating voltage be all first power supply
Voltage VH.
The first NMOS tube N1, the second NMOS tube N2, the third NMOS tube N3, the 4th NMOS tube N4,
The operating voltage of the 5th PMOS tube P5 and the 8th NMOS tube N8 is all the second source voltage VL.
The size of the first control voltage POC_NL is between second source voltage VL and ground VSS, second control
The size of voltage POC_PH processed is between the first supply voltage VH and ground VSS.
Voltage level converting of the embodiment of the present invention increases switching tube in pull-down circuit 2, and switching tube can be in low pressure
That is second source voltage VL be lower than predetermined voltage when disconnect, so as to prevent during economize on electricity generate high voltage power supply to VSS it
Between conductive path, realize good energy-saving effect；The switching tube of the embodiment of the present invention can be more than or equal to predetermined voltage in low pressure
When be held on, therefore will not have an adverse effect to the operation of circuit during normal operation.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of voltage level converting characterized by comprising
The pull-up circuit and pull-down circuit being connected between the first supply voltage and ground；
The low pressure, input end of the pull-down circuit connects low voltage input signal, the connection of the pull-up circuit and the pull-down circuit
Position is high-voltage output end and output High voltage output signal, the size of the low voltage input signal are located at second source voltage and ground
Between, the size of the High voltage output signal is between first supply voltage and ground；First supply voltage is higher than
The second source voltage；
When the second source voltage is lower than predetermined voltage, voltage level converting does not work and the High voltage output signal
It is fixedly attached to ground or first supply voltage；
It include switching tube in the pull-down circuit, the switching tube is more than or equal to described predetermined in the second source voltage
Be connected when voltage, the switching tube disconnect when the second source voltage is lower than predetermined voltage to avoid the pull-up circuit and
The guiding path that the pull-down circuit is formed between first supply voltage and ground.
2. voltage level converting as described in claim 1, it is characterised in that: the level shifting circuit is integrated circuit
In signal provide level conversion.
3. voltage level converting as claimed in claim 2, it is characterised in that: the predetermined voltage is the integrated circuit
Corresponding voltage when chip is energy-saving mode, in the energy-saving mode, the second source voltage drop is as low as guaranteeing to maintain
The current potential of data in the IC chip, the predetermined voltage are more than or equal to the number maintained in the IC chip
According to current potential.
4. voltage level converting as claimed in claim 2, it is characterised in that: the external work of the IC chip
Voltage is greater than internal operating voltages.
5. voltage level converting as described in claim 1, it is characterised in that: the pull-up circuit includes the first PMOS
Pipe.
6. voltage level converting as claimed in claim 5, it is characterised in that: the pull-down circuit includes the first NMOS
Pipe.
7. voltage level converting as claimed in claim 6, it is characterised in that: the pull-up circuit and the pull-down circuit
It is all differential configuration.
8. voltage level converting as claimed in claim 7, it is characterised in that: the pull-up circuit further includes the 2nd PMOS
Pipe, the pull-down circuit further includes the second NMOS tube；
The source electrode of first PMOS tube and the source electrode of second PMOS tube all connect first supply voltage；
The drain electrode of first PMOS tube and the drain electrode of first NMOS tube are all connected to the first high-voltage output end, and described first
High-voltage output end exports the first High voltage output signal；
The drain electrode of second PMOS tube and the drain electrode of second NMOS tube are all connected to the second high-voltage output end, and described second
High-voltage output end exports the second High voltage output signal；
The grid of second PMOS tube connects the first High voltage output signal, described in the grid connection of first PMOS tube
Second High voltage output signal；The first High voltage output signal and the second High voltage output signal inversion.
9. voltage level converting as claimed in claim 8, it is characterised in that:
The source electrode of first NMOS tube and the source electrode of second NMOS tube are all connected to ground；
The grid of first NMOS tube connects the first low voltage input signal, and the grid of second NMOS tube connects the second low pressure
Input signal, first low voltage input signal and the second low voltage input signal reverse phase.
10. voltage level converting as claimed in claim 9, it is characterised in that: the switching tube includes two, respectively
Third NMOS tube and the 4th NMOS tube；
The drain electrode of first NMOS tube is connected to first high-voltage output end, the third by the third NMOS tube
The source electrode of NMOS tube connects the drain electrode of first NMOS tube, and it is defeated that the drain electrode of the third NMOS tube is connected to first high pressure
Outlet；
The drain electrode of second NMOS tube is connected to second high-voltage output end by the 4th NMOS tube, and the described 4th
The source electrode of NMOS tube connects the drain electrode of second NMOS tube, and it is defeated that the drain electrode of the 4th NMOS tube is connected to second high pressure
Outlet；
The grid of the third NMOS tube and the grid of the 4th NMOS tube are all connected to the first control voltage, first control
Voltage processed is the detection voltage of the second source voltage, when the second source voltage is lower than the predetermined voltage described in the
One control voltage be low level, when the second source voltage be more than or equal to the predetermined voltage when described in first control voltage be
High level.
11. voltage level converting as claimed in claim 10, it is characterised in that: the pull-down circuit further includes the 5th
NMOS tube and the 6th NMOS tube；
The drain electrode of the third NMOS tube is connected to first high-voltage output end by the 5th NMOS tube, and the described 4th
The drain electrode of NMOS tube is connected to second high-voltage output end by the 6th NMOS tube；
The source electrode of 5th NMOS tube connects the drain electrode of the third NMOS tube, and the drain electrode of the 5th NMOS tube is connected to institute
State the first high-voltage output end；
The source electrode of 6th NMOS tube connects the drain electrode of the 4th NMOS tube, and the drain electrode of the 6th NMOS tube is connected to institute
State the second high-voltage output end；
The grid of 5th NMOS tube connects first low voltage input signal；Described in the grid connection of 6th NMOS tube
Second low voltage input signal；
5th NMOS tube and the 6th NMOS tube are all Native NMOS tube.
12. voltage level converting as claimed in claim 11, it is characterised in that: the pull-up circuit further includes third
PMOS tube and the 4th PMOS tube；The third PMOS tube and the 4th PMOS tube are for balancing the pull-up circuit and being in series with
The current capacity of the pull-down circuit of the switching tube；
The drain electrode of first PMOS tube is connected to first high-voltage output end, the third by the third PMOS tube
The source electrode of PMOS tube connects the drain electrode of first PMOS tube, and it is defeated that the drain electrode of the third PMOS tube is connected to first high pressure
Outlet；
The drain electrode of second PMOS tube is connected to second high-voltage output end by the 4th PMOS tube, and the described 4th
The source electrode of PMOS tube connects the drain electrode of second PMOS tube, and it is defeated that the drain electrode of the 4th PMOS tube is connected to second high pressure
Outlet.
13. voltage level converting as claimed in claim 12, it is characterised in that: the voltage level converting also wraps
The 7th NMOS tube is included, the drain electrode of the 7th NMOS tube connects second high-voltage output end, the source electrode of the 7th NMOS tube
Ground connection, grid connection the second control voltage of the 7th NMOS tube, the second control voltage and the first control voltage
Reverse phase；
The second control voltage is high level described in when the second source voltage is lower than the predetermined voltage, is made described second high
Pressure output signal is fixedly attached to ground and the first High voltage output signal is made to be fixedly attached to first supply voltage；
7th NMOS tube described in when the second source voltage is more than or equal to the predetermined voltage disconnects.
14. voltage level converting as claimed in claim 13, it is characterised in that: the voltage level converting also wraps
It includes and connects the phase inverter formed, the source electrode connection of the 5th PMOS tube second electricity with the 8th NMOS tube by the 5th PMOS tube
The grid of source voltage, the source electrode ground connection of the 8th NMOS tube, the grid of the 5th PMOS tube and the 8th NMOS tube is all
First low voltage input signal is connected, the drain electrode of the 5th PMOS tube and the drain electrode of the 8th NMOS tube link together
And output second low voltage input signal.
15. voltage level converting as claimed in claim 14, it is characterised in that: first PMOS tube, described second
PMOS tube, the third PMOS tube, the 4th PMOS tube, the 5th NMOS tube, the 6th NMOS tube, the described 7th
The operating voltage of NMOS tube is all first supply voltage；
First NMOS tube, second NMOS tube, the third NMOS tube, the 4th NMOS tube, the 5th PMOS
The operating voltage of pipe and the 8th NMOS tube is all the second source voltage；
Between second source voltage and ground, the size of the second control voltage is located at the size of the first control voltage
Between first supply voltage and ground.
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|---|---|---|---|
| CN201910476088.7A CN110289848A (en) | 2019-06-03 | 2019-06-03 | Voltage level converting |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910476088.7A CN110289848A (en) | 2019-06-03 | 2019-06-03 | Voltage level converting |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110535459A (en) * | 2019-09-30 | 2019-12-03 | 安凯(广州)微电子技术有限公司 | A kind of digital level conversion circuit based on low voltage CMOS process |
| CN111049513A (en) * | 2019-11-29 | 2020-04-21 | 北京时代民芯科技有限公司 | Rail-to-rail bus holding circuit with cold backup function |
| WO2022095503A1 (en) * | 2020-11-06 | 2022-05-12 | 北京奕斯伟计算技术有限公司 | Level shift circuit and integrated circuit |
| CN116232011A (en) * | 2023-03-07 | 2023-06-06 | 禹创半导体(深圳)有限公司 | Voltage conversion device with energy recovery mechanism and power supply chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101686048A (en) * | 2008-07-10 | 2010-03-31 | 台湾积体电路制造股份有限公司 | Low leakage voltage level shifting circuit |
| KR20100133610A (en) * | 2009-06-12 | 2010-12-22 | 주식회사 하이닉스반도체 | Voltage level shifter |
| CN107947784A (en) * | 2017-10-20 | 2018-04-20 | 上海华力微电子有限公司 | A kind of high-performance output driving circuit |
| CN109347473A (en) * | 2018-09-04 | 2019-02-15 | 上海东软载波微电子有限公司 | Level shift circuit |
-
2019
- 2019-06-03 CN CN201910476088.7A patent/CN110289848A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101686048A (en) * | 2008-07-10 | 2010-03-31 | 台湾积体电路制造股份有限公司 | Low leakage voltage level shifting circuit |
| KR20100133610A (en) * | 2009-06-12 | 2010-12-22 | 주식회사 하이닉스반도체 | Voltage level shifter |
| CN107947784A (en) * | 2017-10-20 | 2018-04-20 | 上海华力微电子有限公司 | A kind of high-performance output driving circuit |
| CN109347473A (en) * | 2018-09-04 | 2019-02-15 | 上海东软载波微电子有限公司 | Level shift circuit |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110535459A (en) * | 2019-09-30 | 2019-12-03 | 安凯(广州)微电子技术有限公司 | A kind of digital level conversion circuit based on low voltage CMOS process |
| CN111049513A (en) * | 2019-11-29 | 2020-04-21 | 北京时代民芯科技有限公司 | Rail-to-rail bus holding circuit with cold backup function |
| CN111049513B (en) * | 2019-11-29 | 2023-08-08 | 北京时代民芯科技有限公司 | Rail-to-rail bus holding circuit with cold backup function |
| WO2022095503A1 (en) * | 2020-11-06 | 2022-05-12 | 北京奕斯伟计算技术有限公司 | Level shift circuit and integrated circuit |
| CN116232011A (en) * | 2023-03-07 | 2023-06-06 | 禹创半导体(深圳)有限公司 | Voltage conversion device with energy recovery mechanism and power supply chip |
| CN116232011B (en) * | 2023-03-07 | 2024-01-26 | 禹创半导体(深圳)有限公司 | Voltage conversion device with energy recovery mechanism and power supply chip |
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Application publication date: 20190927 |