CN108123708B

CN108123708B - Pull-up circuit for IO circuit

Info

Publication number: CN108123708B
Application number: CN201611073847.8A
Authority: CN
Inventors: 耿彦; 陈捷; 马晓媛
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-11-29
Filing date: 2016-11-29
Publication date: 2021-06-08
Anticipated expiration: 2036-11-29
Also published as: CN108123708A

Abstract

A pull-up circuit for an IO circuit, comprising: the access control module and the pull-up module are connected in series between the IO port and the IO power supply; the switch module generates an access control signal according to the IO port signal and the first interface signal, when the IO port is input or floated, the voltage value of the IO port signal is equal to the first interface signal, and the access control signal is larger than or equal to the difference value between the IO port signal and the preset threshold voltage; the access control module is switched off or switched on under the control of the access control signal and a second interface signal, and the voltage value of the second interface signal is equal to the larger one of the voltage value of the IO power supply and the voltage value of the IO port signal. According to the technical scheme, when the voltage value of the IO port signal is larger than the voltage value of the IO power supply, the current can be effectively prevented from flowing backwards from the IO port to the IO power supply; when the IO port is floated, the requirement that the potential at the IO port can be pulled up to the minimum value which is always larger than the high voltage of the IO logic output is more easily met.

Description

Pull-up circuit for IO circuit

Technical Field

The invention relates to the field of integrated circuits, in particular to a pull-up circuit for an IO circuit.

Background

Pull-up applications, which are common characteristics of Input/Output (IO) circuits, have been increasingly applied to IO circuits to provide an IO circuit Input/Output high level value. In a typical IO circuit, the IO Port (PAD) voltage is typically less than the voltage value of the IO power supply (VDDIO), and a pull-up circuit is typically connected on the input side of the IO port PAD to pull up the voltage value of the IO port signal to be equal to the voltage value of the IO power supply of the IO circuit. In practical application, if the input voltage of the PAD at the IO port is greater than the voltage value of the IO power supply, or the voltage of the IO power supply is suddenly turned off and the PAD at the IO port still has a potential, the PAD from the IO port to the IO power supply is easily generatedThe reverse current of (1); on the other hand, even if the IO power supply of the IO circuit is in a normal power supply state, if the IO port PAD is in a floating (floating) state, the voltage at the IO port PAD will be pulled up due to the presence of the pull-up circuit, but based on the existing pull-up circuit structure, it is very likely that the pull-up voltage of the IO port PAD is less than the logic output high voltage (V)_OH) The minimum value of (3) imposes a limit on the output voltage value of the IO circuit.

The existing IO circuit usually employs the circuit structure shown in fig. 1 to implement the pull-up application, when the voltage at the PAD of the IO port is greater than the voltage value VDDIO of the IO power supply, the voltage of the node net1 needs to be smaller than the voltage value VDDIO of the IO power supply by at least the threshold voltage V of the MOS transistor M1_thM1The MOS transistor M1 can be turned on, and no matter the interface control signal REN is at a high level or a low level, no current flows from the IO port PAD to the IO power supply, i.e., no reverse current from the IO port PAD to the IO power supply is generated. However, this circuit configuration is such that when the IO port PAD is in a floating state and the interface control signal REN is low to make the pull-up active, the pull-up voltage at the IO port PAD is smaller than the voltage value VDDIO of the IO power supply (about the threshold voltage V of the small MOS transistor M1)_thM1Of) a high voltage, under some conditions, it is likely to result in a situation where the pull-up voltage at the IO port PAD is less than the minimum value of the IO logic output high voltage.

In the present stage, the IO circuit is mostly implemented by the circuit structure shown in fig. 1, or other modified structure similar to fig. 1 to realize the pull-up application. However, such a circuit design is very likely to cause the situation that the pull-up voltage at the PAD of the IO port is smaller than the minimum value specified by the high voltage of the IO logic output under some conditions, and the normal output of the IO circuit is affected.

Disclosure of Invention

The technical problem solved by the invention is that the problem that the pull-up voltage at the IO port is smaller than the minimum value specified by the IO logic output high voltage can occur under some conditions in the existing circuit structure of the pull-up circuit for the IO circuit based on failure protection application or the IO port voltage is higher than the IO power supply voltage input application under normal working, and the normal output of the IO circuit is influenced.

To solve the above technical problem, an embodiment of the present invention provides a pull-up circuit for an IO circuit, including: the access control module and the pull-up module are connected in series between the IO port and the IO power supply; the switch module is used for generating an access control signal according to an IO port signal and a received first interface signal, when the IO port is in an input or floating state, the voltage value of the IO port signal is equal to the first interface signal, the access control signal is larger than or equal to the difference value between the IO port signal and a preset threshold voltage, and the IO port signal is a signal on the IO port; wherein the on-off state of the pull-up module is controlled by the received pull-up control signal; when the IO port is in an input or floating state, the access control module is turned off or turned on under the control of the access control signal and a received second interface signal, and the voltage value of the second interface signal is equal to the larger one of the voltage value of the IO power supply and the voltage value of the IO port signal.

Optionally, the access control module includes: the grid electrode of the first PMOS tube is coupled with the switch module, the substrate of the first PMOS tube is used for receiving the second interface signal, the source electrode of the first PMOS tube is directly or indirectly coupled with the IO power supply, and the drain electrode of the first PMOS tube is directly or indirectly coupled with the IO port.

Optionally, the upward-pulling module includes: the grid electrode of the second PMOS tube is used for receiving the pull-up control signal, the source electrode of the second PMOS tube is directly or indirectly coupled with the IO power supply, and the drain electrode of the second PMOS tube is directly or indirectly coupled with the IO port.

Optionally, the switch module includes: the gate of each NMOS transistor is coupled to the IO port, wherein the source of the first NMOS transistor is used for receiving the first interface control signal, the source of the next NMOS transistor is coupled to the drain of the previous NMOS transistor, and the drain of the last NMOS transistor is coupled to the access control module.

Optionally, the number of the NMOS transistors included in the switch module is determined by a compromise of a pull-up voltage of the IO port signal when the IO port floats and a leakage current flowing from the IO port to the IO power supply when the voltage value of the IO port signal is higher than the voltage value of the IO power supply.

Optionally, the pull-up circuit for an IO circuit further includes: and the signal generating module is used for generating the first interface signal and the second interface signal.

Optionally, the signal generating module includes: and the tolerance signal generating unit is used for generating the first interface signal and the second interface signal when the IO power supply is normally powered and the voltage value of the IO port signal is higher than that of the IO power supply.

Optionally, the tolerance signal generating unit includes: third PMOS pipe, fourth PMOS pipe, fifth PMOS pipe, third NMOS pipe and fourth NMOS pipe, wherein: the source electrode of the third PMOS tube and the gate electrode of the fourth PMOS tube are connected and coupled with the IO power supply, the drain electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the gate electrode of the third PMOS tube are connected and coupled with the IO port, and the drain electrode and the substrate of the third PMOS tube are coupled with the source electrode and the substrate of the fourth PMOS tube and the substrate of the fifth PMOS tube, so that the second interface signal is determined according to the higher one of the voltage value of the IO port signal and the voltage value of the IO power supply; the grid electrode of the third NMOS tube is coupled with the IO power supply, and the drain electrode of the fifth PMOS tube is coupled with the drain electrode of the third NMOS tube and is used for generating the first interface signal; the source electrode of the third NMOS tube is coupled with the drain electrode of the fourth NMOS tube, and the substrate of the third NMOS tube is connected with the source electrode of the fourth NMOS tube and is grounded; and the grid electrode of the fourth NMOS tube is used for receiving a first IO control signal.

Optionally, the tolerance signal generating unit further includes: the phase inverter is coupled between the IO power supply and the core power supply, wherein the input end of the phase inverter is used for receiving a second IO control signal, and the output end of the phase inverter is coupled to the grid electrode of the fifth PMOS tube.

Optionally, the signal generating module includes: and the failure protection signal generation unit is used for generating the first interface signal and the second interface signal when the voltage value of the IO power supply is low level and the voltage value of the IO port signal is less than or equal to the voltage value of the IO power supply.

Optionally, the fail-safe signal generating unit includes: sixth PMOS pipe, seventh PMOS pipe, eighth PMOS pipe, fifth NMOS pipe and sixth NMOS pipe, wherein: a source electrode of the sixth PMOS transistor and a gate electrode of the seventh PMOS transistor are connected and coupled with the IO power supply, a drain electrode of the seventh PMOS transistor, a source electrode of the eighth PMOS transistor and a gate electrode of the sixth PMOS transistor are connected and coupled with the IO port, and a substrate and a drain electrode of the sixth PMOS transistor are coupled with a source electrode and a substrate of the seventh PMOS transistor and a substrate of the eighth PMOS transistor, so as to determine the second interface signal according to a higher one of a voltage value of the IO port signal and a voltage value of the IO power supply; a grid electrode of the eighth PMOS transistor is connected with a grid electrode of the sixth NMOS transistor and receives the first IO control signal, and a drain electrode of the eighth PMOS transistor is coupled with a drain electrode of the fifth NMOS transistor and is used for generating the first interface signal; the grid electrode of the fifth NMOS tube is coupled with the IO power supply, the source electrode of the fifth NMOS tube is coupled with the drain electrode of the sixth NMOS tube, and the substrate of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube and is grounded.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

and generating an access control signal based on the switch module, wherein when an IO port is in an input or floating state, the voltage value of the IO port signal is equal to that of the first interface signal, and the access control signal is greater than or equal to the difference value between the IO port signal and a preset threshold voltage. When the IO port is in an input state, the access control module is cut off under the control of the access control signal and the second interface signal, so that when the voltage value of the IO port signal is larger than the voltage value of the IO power supply, even if the pull-up module is opened, the backward flow of current from the IO port to the IO power supply can not occur. Further, when the IO port is in a floating state and the pull-up module is opened, the access control module is turned on under the control of the access control signal to pull up the voltage value of the IO port signal to a higher voltage value, so as to meet the requirement of a minimum value larger than the IO logic output high voltage.

Compared with the prior art shown in fig. 1, the pull-up voltage at the IO port signal obtained according to the embodiment of the present invention, that is, the voltage value of the IO port signal is higher than the voltage value of the IO port signal obtained according to the embodiment of the present invention by about one preset threshold voltage value, when the IO power supply suddenly fails and the IO port is in the failure protection mode of the logic high voltage, and the input voltage of the IO port is higher than the IO power supply voltage under normal operation, the reverse flow of current from the IO port to the IO power supply can be effectively prevented, meanwhile, when the IO port is in a floating state, the voltage value of the IO port signal is more easily pulled up to the requirement that the voltage value is always higher than the minimum value of the IO logic output high voltage, and the pull-up circuit is favorable for generating stable output voltage.

Further, the first interface signal and the second interface signal are generated by different signal generation modules, and when the pull-up voltage at the IO port is increased by the technical scheme of the embodiment of the invention, no backward current is generated under the condition that the failure protection application or the IO port voltage is higher than the IO power supply voltage input application under normal operation, that is, the condition that current is transmitted from the IO port to the IO power supply cannot occur.

Drawings

FIG. 1 is a schematic diagram of a pull-up circuit for an IO circuit;

fig. 2 is a schematic circuit diagram of a conventional signal generating module in a case of an IO power supply voltage input application based on an IO port voltage higher than that in a normal operation;

fig. 3 is a block diagram of a pull-up circuit for an IO circuit according to a first embodiment of the present invention;

fig. 4 is a schematic circuit diagram of a pull-up circuit for an IO circuit according to a first embodiment of the present invention;

fig. 5 is a schematic circuit diagram of another pull-up circuit for an IO circuit according to the first embodiment of the present invention;

fig. 6 is a schematic circuit diagram of a signal generating module in a pull-up circuit for an IO circuit according to a second embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a signal generating module in a pull-up circuit for an IO circuit according to a third embodiment of the present invention;

FIG. 8 is a schematic diagram of a leakage current simulation result using an embodiment of the present invention; and

fig. 9 is a schematic diagram of another simulation result of leakage current according to an embodiment of the present invention.

Detailed Description

Those skilled in the art will appreciate that the pull-up circuit for IO circuits in the prior art generally employs the circuit configuration shown in fig. 1. In the circuit structure shown in fig. 1, M1 is an NMOS transistor, M2 is a PMOS transistor, REN is a pull-up control signal, and net1 is a node 1 for connecting the source of the NMOS transistor M1 and the drain of the PMOS transistor M2. According to the circuit configuration shown in fig. 1, when in a fail-safe mode (for example, the voltage value VDDIO of the IO power supply is suddenly powered down, and the voltage value of the IO port signal is logic high), or the voltage value of the input signal of the IO port is higher than the voltage value VDDIO of the IO power supply under normal operation, even if the NMOS transistor M1 is turned on, the voltage value of the net1 is still lower than the IO power supply voltage by at least the threshold voltage of M1, which ensures that no backward current from the IO port PAD to the IO power supply occurs. However, if the IO port PAD is in floating (floating) state and the pull-up control signal REN is low to enable the pull-up, the voltage value of the IO port signal is smaller than the voltage value VDDIO of the IO power supply (smaller by about one threshold voltage of the NMOS transistor M1), which may cause the voltage value of the IO port signal to be smaller than the minimum value specified by the high voltage of the IO logic output under some conditions, and thus affect the normal output of the IO circuit.

In order to solve the technical problem, according to the technical scheme provided by the invention, the voltage value of the IO port signal is more easily pulled up and meets the design requirement of the minimum value higher than the IO logic output high voltage based on the access control signal generated by the switch module, so that the pull-up circuit can generate stable output voltage.

In a preferred embodiment of the present invention, the switch module generates an access control signal according to an IO port signal and the first interface signal by receiving the first interface signal and the second interface signal generated by the signal generation module, where the first interface signal is a voltage value of an IO power supply when the IO port is in an input or floating state, and the access control signal is greater than or equal to a difference between the IO port signal and a preset threshold voltage when the voltage value of the IO port signal is equal to the first interface signal. When the IO port is in an input state, the access control module is stopped under the control of the access control signal and the second interface signal, so that when the voltage value of the IO port signal is greater than the voltage value of the IO power supply, even if the pull-up module is opened, the backward flow of current from the IO port to the IO power supply can not occur. Further, when the IO port is in a floating state and the pull-up module is opened, the access control module is turned on under the control of the access control signal to pull up the voltage value of the IO port signal to a higher voltage value, so as to meet the requirement of a minimum value larger than the IO logic output high voltage. Because the pull-up module and the access control module are connected in series between the IO port and the IO power supply, when the pull-up module and the access control module are both PMOS tubes, the voltage value of the IO port signal is higher than the voltage value of the IO port signal obtained in the technical scheme based on FIG. 1 by about one value of the preset threshold voltage, so that the pull-up module is easier to pull up and meets the requirement that the voltage value of the IO port signal is higher than the minimum value of the IO logic output high voltage.

When the voltage value of the input signal of the IO port is higher than the voltage value of the IO power supply under normal operation, when the voltage value of the IO port signal is higher than the voltage value of the IO power supply by a threshold voltage value of the PMOS transistor M3, under the control of the first IO control signal OEH at IO logic low level, the PMOS transistor M3 is turned on, the voltage value of the first interface signal TG is pulled to the voltage value of the IO port signal, and the voltage value of the second interface signal NWELL is equal to the larger one of the voltage value of the IO power supply and the voltage value of the IO port signal.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

It is understood by those skilled in the art that the expressions "same", "equal", etc. in the embodiments of the present invention may not be limited to exact equivalence in the numerical sense, but may include equivalence within an acceptable error range.

Fig. 3 is a pull-up circuit for an IO circuit according to a first embodiment of the present invention. Specifically, in the present embodiment, the pull-up circuit for the IO circuit includes an access control module 11 and a pull-up module 12, which are connected in series between an IO port PAD and an IO power supply; the switch module 13 is used for generating an access control signal according to an IO port signal and a received first interface signal TG, when the IO port is in an input or floating state, the voltage value of the IO port signal is equal to the first interface signal TG, the access control signal is larger than or equal to the difference value of the IO port signal and a preset threshold voltage, and the IO port signal is a signal on an IO port PAD. Preferably, the switching state of the pull-up module 12 is controlled by the received pull-up control signal REN. Preferably, in a state where the IO port is in an input state and the pull-up module 12 is open, the access control module 11 is turned on under the control of the access control signal and the received second interface signal NWELL, the voltage value of the IO port signal can be pulled up to a higher voltage value based on the pull-up action of the pull-up module 12, wherein the voltage value of the second interface signal NWELL is equal to the larger one of the voltage value VDDIO of the IO power supply and the voltage value of the IO port signal.

Preferably, the switch module 13 is configured to generate a series effect on the access control module 11, change a port voltage value of the access control module through the access control signal, and implement, in combination with the second interface signal NWELL, that when the IO port PAD is in a floating state, the access control module 11 can be controlled to be in a conducting state; when the pull-up circuit is in a failure protection mode (i.e., the voltage value VDDIO of the IO power supply is suddenly powered off, and the input voltage of the IO port is a logic high level), or the voltage value of the input signal of the IO port is higher than the voltage value of the IO power supply under normal operation, even when the pull-up module 12 is in an open state, the access control module 11 can be controlled to be in an off state.

Preferably, when the pull-up control signal REN is at a low level, the pull-up module 12 is turned on, so as to generate a pull-up effect; when the pull-up control signal REN is high, the pull-up module 12 is turned off.

Preferably, the access control module 11 is configured to prevent a backward current effect flowing from the IO port PAD to the IO power supply, and meanwhile, when the pull-up module 12 is turned on, the access control module 11 may also be configured to assist the pull-up module 12 to achieve the pull-up effect.

In a preferred application scenario, when the pull-up circuit is in the fail-safe state (that is, the IO power supply is suddenly powered off, and the input voltage of the IO port is at a logic high level), or the voltage value of the input signal of the IO port is higher than the voltage value of the IO power supply under normal operation, the voltage value of the IO port signal is equal to the first interface signal TG, the switch module 13 controls the access control module 11 to be also in the off state, and therefore no matter whether the pull-up control signal REN is at a high level or a low level, that is, no matter whether the pull-up module 12 is in the on or off state, no backward current flowing from the IO port PAD to the IO power supply is generated.

Further, when the IO port PAD is in a floating state, and the pull-up module 12 and the access control module 11 are both PMOS transistors, the switch module 13 generates an access control signal greater than or equal to a difference between the IO port signal and the preset threshold voltage, and the switch module 13 controls the access control module 11 to be turned on, and when the pull-up control signal REN is at a low level, the pull-up module 12 is turned on, and then a difference between a voltage value VDDIO of the IO power supply and a voltage value of the access control signal must be at least smaller than the threshold voltage of the access control module 11 to ensure that the access control module 11 is in a conducting state, and because the access control signal is greater than or equal to the difference between the IO port signal and the preset threshold voltage, the access control module 11 remains in the conducting state until the voltage value of the IO port signal is pulled up to be greater than or equal to the voltage value IO of the VDDIO power supply minus the voltage value IO of the access control module 11 The threshold voltage of the control signal is added with the voltage value of the preset threshold voltage.

Further, the pull-up circuit for the IO circuit further includes a signal generating module (not shown in the figure) for generating the first interface signal TG and the second interface signal NWELL.

In this regard, with the solution of the first embodiment, the voltage value of the IO port signal may be finally pulled up to a higher voltage value (for example, the voltage value of the IO port signal may be pulled up to a value which is lower than the voltage value VDDIO of the IO power supply by about the threshold voltage of the access control module 11 minus the preset threshold voltage), compared with the prior art which can only pull up the voltage value of the IO port signal to a value which is lower than the voltage value VDDIO of the IO power supply by about the threshold voltage of the access control module 11 (similar to the NMOS transistor M1 shown in fig. 1), the voltage value of the IO port signal may be pulled up further by the preset threshold voltage corresponding to the switch module 13, and it is easier to meet the circuit design requirement that the voltage value of the IO port signal is higher than the minimum value of the IO logic output high voltage.

Fig. 4 and 5 are schematic structural diagrams of a pull-up circuit for an IO circuit according to an embodiment of the present invention. The access control module 11 includes a first PMOS transistor M1, a gate of the first PMOS transistor M1 is coupled to the switch module 13, a substrate of the first PMOS transistor M1 is configured to receive the second interface signal NWELL, a source of the first PMOS transistor M1 is directly or indirectly coupled to an IO power source, and a drain of the first PMOS transistor M1 is directly or indirectly coupled to the IO port PAD.

Further, the pull-up module 12 includes a second PMOS transistor M2, a gate of the second PMOS transistor M2 is configured to receive the pull-up control signal REN, a source of the second PMOS transistor M2 is directly or indirectly coupled to the IO power supply, and a drain of the second PMOS transistor M2 is directly or indirectly coupled to the IO port PAD.

Further, the switch module 13 includes at least one NMOS transistor connected in series, a gate of each NMOS transistor is coupled to the IO port PAD, a source of a first NMOS transistor is configured to receive the first interface control signal TG, a source of a next NMOS transistor is coupled to a drain of a previous NMOS transistor, and a drain of a last NMOS transistor is coupled to the access control module 11. In a preferred embodiment, the number of the NMOS transistors included in the switch module 13 is determined by a tradeoff between a pull-up voltage of the IO port PAD when the IO port PAD is floated and a leakage current flowing from the IO port PAD to the IO power supply when the voltage value of the IO port signal is higher than the voltage value VDDIO of the IO power supply. Those skilled in the art will appreciate that the trade-off decision may be understood to be that the gate-source voltage V of the second PMOS transistor M2 is pulled up_GSThe voltage is as close as possible to the preset threshold voltage to be used as a conduction starting point; when the reverse current is likely to occur, the gate-source voltage V of the second PMOS pipe M2_GSThe threshold voltage is less than or equal to the preset threshold voltage and is used as a cut-off starting point.

In a typical application scenario shown in fig. 4, the source of the first PMOS transistor M1 is directly coupled to the IO power supply, the drain of the first PMOS transistor M1 is coupled to the source of the second PMOS transistor M2, and the drain of the second PMOS transistor M2 is coupled to the IO port PAD, such that the access control module 11 and the pull-up module 12 are connected in series between the IO port PAD and the IO power supply.

Further, the switch module 13 is formed by connecting two NMOS transistors in series, where the two NMOS transistors are a first NMOS transistor M4 and a second NMOS transistor M3, respectively, gates of the first NMOS transistor M4 and the second NMOS transistor M3 are both coupled to the IO port PAD, a source of the first NMOS transistor M4 is configured to receive the first interface control signal TG, a source of the second NMOS transistor M4 is coupled to a drain of the first NMOS transistor, and a drain of the second NMOS transistor is coupled to a gate of a first PMOS transistor M1 included in the access control signal 11.

On the basis of the circuit connection structure in this application scenario, when the voltage value of the IO port signal is equal to the voltage value of the first interface signal TG and is at a high level, the first NMOS transistor M4 is in an off state, and due to the completely symmetrical characteristic of the MOS transistor, in order to ensure that the first NMOS transistor M4 is always in an off state, the drain voltage V of the first NMOS transistor M4 is the drain voltage V_net1The voltage value of the IO port signal is required to be more than or equal to a value obtained by subtracting the threshold voltage of the first NMOS transistor M4, namely V_net1≥V_PAD-V_thM4(wherein, V_PADIs the voltage value, V, of the IO port signal_thM4The threshold voltage of the first NMOS transistor M4), the second NMOS transistor M3 is in the cut-off state, so that V is_net2≈V_net1(wherein, V_net2Is the voltage value at the node net2, and can also be understood as the drain voltage of the second NMOS transistor M3). When the pull-up control signal REN is at a low level, the second PMOS transistor M2 is turned on, and the node net3 is pulled up to the IO port voltage, so that even if a failure protection mode occurs when the IO power supply is suddenly powered off or the input voltage of the IO port is greater than the voltage value of the IO power supply during normal operation, the voltage V is greater than the voltage value of the IO power supply during normal operation_net3≈V_PAD，V_thM4≈V_thM1,V_net1≈V_net2Can realize V_net3≤V_thM1+V_net2So that the first PMOS transistor M1 is turned off, and therefore no reverse current from the IO port to the IO power supply occurs. When the voltage value of the IO port and the voltage value of the first interface signal TG are both in a floating state, the first NMOS transistor M4 and the second NMOS transistor M3 are cut off, and V is set to be in a floating state_PAD≤V_thM4+V_net2When the pull-up control signal REN is low, i.e. the second PMOS transistor M2 is turned on, the first PMOS transistor M1 can be pulled up to the off, i.e. V_DDIO-V_net2≤V_thM1Can realize V_PAD≥V_DDIO-V_thM1+V_thM4. Enabling the voltage value of the IO port signal to be pulled up to VDDIO-V_thM1+V_thM4Compared with the prior artThe voltage value of the IO port signal can only be pulled up to VDDIO-V at most_thM1The technical scheme of the numerical value can meet the requirement that the voltage value of the IO port signal is higher than the minimum value of the IO logic output high voltage more easily.

In another exemplary application scenario shown in fig. 5, the switch module 13 also includes two NMOS transistors M3 and M4 connected in series, and those skilled in the art may refer to the application scenario in the circuit structure shown in fig. 4, which is not described herein again. Further, the circuit structure shown in fig. 5 is mainly different from the circuit structure shown in fig. 4 in that the source of the second PMOS transistor M2 is directly coupled to the IO power supply, the drain of the second PMOS transistor M2 is coupled to the source of the first PMOS transistor M1, and the drain of the first PMOS transistor M1 is coupled to the IO port PAD. Those skilled in the art understand that, compared with the connection method in the circuit structure shown in fig. 4, in the application scenario, the connection manner of the first PMOS transistor and the second PMOS transistor may also enable the access control module 11 and the pull-up module 12 to be connected in series between the IO port PAD and the IO power supply, so as to perform a pull-up function.

From the above, with the technical solution of fig. 4 or 5, by using the threshold voltage of the first NMOS transistor M4 as the preset threshold voltage, the voltage value of the IO port signal can be effectively pulled up to a higher voltage value, and even under some limit conditions, the voltage value of the IO port signal can still meet the circuit design requirement greater than the minimum value of the IO logic output high voltage.

Table 1 lists simulation voltage values of the IO port signal in a floating and pulled-up state when the circuit structure according to the embodiment of the present invention and the circuit structure shown in fig. 1 are used under different conditions; and the corresponding relation between the output voltage and the minimum value of the IO logic output high voltage. When a simulation test is performed, a resistor of 10 mega ohms may be connected between the IO port PAD and the ground to serve as an impedance of the test probe.

TABLE 1

In table 1, TT, FF, and SS represent different process angles, respectively.

As can be seen from table 1, when the prior art represented by the circuit configuration shown in fig. 1 is used as the pull-up circuit for the IO circuit, the simulated voltage value of the IO port signal obtained under each condition is almost close to the minimum value (V) of the IO logic output high voltage_OHmin) Even under certain conditions (for example, TT — 25 ℃, VDDIO of the voltage value of the IO power supply is 1.8V), the simulated voltage value of the IO port signal obtained by using the circuit structure of fig. 1 is lower than the minimum value of the corresponding IO logic output high voltage, so that the pull-up requirement is not met. If the circuit structure shown in fig. 4 or 5 according to the embodiment of the present invention is used as the pull-up circuit for the IO circuit, it is clear from the simulation test result in table 1 that the voltage value of the IO port signal can be effectively pulled up to a higher value, and the value is significantly higher than the minimum value of the IO logic output high voltage under the corresponding limit condition, so as to effectively ensure the working stability of the interface circuit for the IO circuit.

Fig. 6 is a schematic circuit diagram of a signal generating module in a pull-up circuit for an IO circuit according to a second embodiment of the present invention. Specifically, in this embodiment, the signal generating module includes a tolerance signal generating unit, configured to generate the first interface signal TG and the second interface signal NWELL when the IO power supply is normally powered and the voltage value of the IO port signal is higher than the voltage value VDDIO of the IO power supply.

In a typical application scenario, the tolerance signal generating unit includes a third PMOS transistor M1, a fourth PMOS transistor M2, a fifth PMOS transistor M3, a third NMOS transistor M4, and a fourth NMOS transistor M5. Wherein the source of the third PMOS transistor M1 and the gate of the fourth PMOS transistor M2 are connected and coupled to the IO power supply, the drain of the fourth PMOS transistor M2, the source of the fifth PMOS transistor M3 and the gate of the third PMOS transistor M1 are connected and coupled to the IO port PAD, and the drain and the substrate of the third PMOS transistor M1 are coupled to the source and the substrate of the fourth PMOS transistor M2 and the substrate of the fifth PMOS transistor M3, so as to determine the second interface signal NWELL according to the higher one of the voltage value of the IO port signal and the voltage value VDDIO of the IO power supply.

For example, when VDDIO of the IO power source is low and the voltage of the IO port signal is high, the fourth PMOS transistor M2 is turned on, and the voltage of the second interface signal NWELL is approximately equal to the voltage of the IO port signal. For another example, when VDDIO of the IO power supply is high and VDDIO of the IO port signal is low, the third PMOS transistor M1 is turned on, and the NWELL of the second interface signal is approximately equal to VDDIO of the IO power supply. Those skilled in the art understand that, in the present embodiment, the series of PMOS transistors formed by the third PMOS transistor M1 and the fourth PMOS transistor M2 is used to implement that the higher voltage value of the IO power source or the IO port signal is used as the voltage value of the second interface signal NWELL.

Further, a gate of the fifth PMOS transistor M3 is coupled to an output terminal of the inverter 61, a gate of the third NMOS transistor M4 is coupled to the IO power supply, a substrate of the fifth PMOS transistor M3 is coupled to a drain of the third PMOS transistor M1, and a drain of the fifth PMOS transistor M3 is coupled to a drain of the third NMOS transistor M4 and is used for generating the first interface signal TG.

Further, the source of the third NMOS transistor M4 is coupled to the drain of the fourth NMOS transistor M5, and the substrate of the third NMOS transistor M4 is connected to the source of the fourth NMOS transistor M5 and grounded.

Further, the gate of the fourth NMOS transistor M5 is configured to receive the first IO control signal OEH. Preferably, the first IO control signal OEH is at a logic high level when the IO port is in an output state and at a logic low level when the IO port is in an input state or a floating state.

Further, the inverter 61 is coupled between the IO power supply and the core power supply VDD, wherein an input terminal of the inverter 61 is configured to receive the second IO control signal OEL, and an output terminal of the inverter 61 is coupled to the gate of the fifth PMOS transistor M3. In the exemplary application scenario shown in fig. 6, the inverter 61 includes a ninth PMOS transistor M6 and a seventh NMOS transistor M7, wherein a source of the ninth PMOS transistor M6 is coupled to the IO power supply, a drain of the ninth PMOS transistor M6 is connected to a drain of the seventh NMOS transistor M7 and to a gate of the fifth PMOS transistor M3, a source of the seventh NMOS transistor M7 is coupled to the core power supply VDD, and a gate of the ninth PMOS transistor M6 and a gate of the seventh NMOS transistor M7 are connected to receive the second IO control signal OEL. Preferably, the second IO control signal OEL is at a logic low level when the IO port is in an output state, and is at a logic high level when the IO port is in an input state or a floating state.

In another exemplary application scenario, the tolerance signal generating unit may also utilize the existing circuit structure shown in fig. 2 to generate the first interface signal TG and the second interface signal NWELL. For example, in the circuit structure shown in fig. 2, the connection manner of the third PMOS transistor M1, the fourth PMOS transistor M2 and the fifth PMOS transistor M3, and the connection manner of the third NMOS transistor M4 and the fourth NMOS transistor M5 may refer to the connection manner shown in fig. 6, which is not described herein again.

Those skilled in the art will understand that the circuit structure shown in fig. 2 is compared with the circuit structure shown in fig. 6, and the inverter is omitted, and the gate of the fifth PMOS transistor M3 is directly connected to the gate of the third NMOS transistor M4 and is coupled to the IO power supply; the circuit structure shown in fig. 2 has the advantage that the circuit structure is relatively simple, and the chip size can be effectively reduced; the circuit configuration shown in fig. 6 described above has the advantage that the ac response of the circuit can be improved by the inverter.

For example, when the circuit shown in fig. 2 is in the transmission mode, the voltage value of the first IO control signal OEH is at a high level, and both the fourth NMOS transistor M5 and the third NMOS transistor M4 are in the on state, so that the voltage value of the generated first interface signal TG is at a low level. On the other hand, the voltage value of the second interface signal NWELL is approximately equal to the voltage value VDDIO of the IO power supply by the third PMOS transistor M1 and the fourth PMOS transistor M2.

When the circuit shown in fig. 2 is in the receiving mode, the voltage value of the first IO control signal OEH is low, the fourth NMOS transistor M5 is in the off state, no current flows between the fourth NMOS transistor M5, the third NMOS transistor M4, and the fifth PMOS transistor M3, and if the voltage value V of the IO port signal is low, no current flows between the fourth NMOS transistor M5, the third NMOS transistor M4, and the fifth PMOS transistor M3_PADThe voltage value VDDIO of the IO power supply is larger than the threshold voltage value of the fifth PMOS transistor M3, so that the fifth PMOS transistor M3 is turned on, and the voltage value of the generated first interface signal TG is approximately equal to the voltage value V of the IO port signal_PAD. On the other hand, the voltage value of the second interface signal NWELL is also approximately equal to the voltage value of the IO port signal under the action of the third PMOS transistor M1 and the fourth PMOS transistor M2.

For another example, when the circuit shown in fig. 6 is in the transmitting mode, the voltage value of the second IO control signal OEL is low level and the voltage value of the first IO control signal OEH is high level, the ninth PMOS transistor M6 is turned on and the seventh NMOS transistor M7 is turned off, and at this time, the gate voltage of the fifth PMOS transistor M3 is approximately equal to the voltage value VDDIO of the IO power supply, which may be substantially equivalent to the circuit structure shown in fig. 2.

When the circuit shown in fig. 6 is in the receiving mode, the voltage value of the second IO control signal OEL is high and the voltage value of the first IO control signal OEH is low, the ninth PMOS transistor M6 is turned off and the seventh NMOS transistor M7 is turned on, such that the gate voltage of the fifth PMOS transistor M3 is approximately equal to the voltage value of the core power VDD, and the voltage value V of the IO port signal is set to be V_PADAs long as the voltage value of the core power supply VDD is greater than the threshold voltage value of the fifth PMOS transistor M3, the fifth PMOS transistor M3 may be turned on, so that the voltage value of the generated first interface signal TG is approximately equal to the voltage value V of the IO port signal_PAD. Generally, the voltage value of the core power supply VDD may be smaller than the voltage value VDDIO of the IO power supply, and the fifth PMOS transistor M3 may be more easily turned on by using the circuit shown in fig. 6. Further, even at this time, the voltage value V of the IO port signal_PADThe voltage value of the IO port signal TG is greater than the voltage value VDDIO of the IO power supply by at least the threshold voltage value of the fifth PMOS transistor M3, and the voltage value of the IO port signal TG is smaller than the voltage value VDDIO of the IO power supply initially, so that the voltage of the IO port signal is enabled to preferentially transmit charges to the port where the second interface signal TG is located, and it is ensured that no backward flow current from the IO port PAD to the IO power supply is generated.

Those skilled in the art can select from the circuit structures shown in fig. 2 or fig. 6 according to actual needs in practical applications, or improve on the circuit structures shown in fig. 2 or fig. 6, which does not affect the technical content of the present invention.

In this way, with the solution of the second embodiment, when the pull-up circuit for the IO circuit is in the high voltage tolerance input state, that is, when the IO power supply is normally powered and the voltage value of the IO port signal is higher than the voltage value VDDIO of the IO power supply, the generated first interface signal TG and the second interface signal NWELL may be transmitted to the circuit described in the first embodiment. Those skilled in the art understand that, in practical applications, the signal output terminal of the first interface signal TG generated in the circuit shown in fig. 2 or fig. 6 may be connected to the signal input terminal of the first interface signal TG in the circuit described in the first embodiment; the signal output of the second interface signal NWELL generated in the circuit of fig. 2 or fig. 6 is connected to the signal input of the second interface signal NWELL in the circuit of the first embodiment described above. For example, the signal output ends of the first interface signal TG and the second interface signal NWELL in the circuit shown in fig. 6 are respectively connected to the signal input ends of the first interface signal TG and the second interface signal NWELL in the circuit shown in fig. 4, and a complete pull-up circuit for an IO circuit is formed by connecting the circuits shown in fig. 6 and fig. 4 in series, so as to prevent current from flowing backwards from an IO port PAD to an IO power supply, and more easily enable the voltage value of the IO port signal to be pulled up to a higher value, so as to meet the circuit design requirement higher than the minimum value of the IO logic output high voltage.

Fig. 7 is a schematic circuit diagram of a signal generating module in a pull-up circuit for an IO circuit according to a third embodiment of the present invention. Specifically, in this embodiment, the signal generating module includes a fail-safe signal generating unit, configured to generate the first interface signal TG and the second interface signal NWELL when a voltage value VDDIO of the IO power supply is a low level and a voltage value VDDIO of the IO port signal is less than or equal to the voltage value VDDIO of the IO power supply.

Preferably, the fail-safe signal generating unit includes a sixth PMOS transistor M1, a seventh PMOS transistor M2, an eighth PMOS transistor M3, a fifth NMOS transistor M4, and a sixth NMOS transistor M5. Wherein a source of the sixth PMOS transistor M1 and a gate of the seventh PMOS transistor M2 are connected and coupled to the IO power supply, a drain of the seventh PMOS transistor M2, a source of the eighth PMOS transistor M3 and a gate of the sixth PMOS transistor M1 are connected and coupled to the IO port PAD, and a substrate and a drain of the sixth PMOS transistor M1 are coupled to a source and a substrate of the seventh PMOS transistor M2 and a substrate of the eighth PMOS transistor M3, so as to determine the second interface signal according to a higher one of a voltage value of the IO port signal and a voltage value VDDIO of the IO power supply.

Preferably, the gate of the eighth PMOS transistor M3 is connected to the gate of the sixth NMOS transistor M5 and receives the first IO control signal OEH, the substrate of the eighth PMOS transistor M3 is coupled to the drain of the sixth PMOS transistor M1, and the drain of the eighth PMOS transistor M3 is coupled to the drain of the fifth NMOS transistor M4 and is configured to generate the first interface signal TG.

Preferably, the gate of the fifth NMOS transistor M4 is coupled to the IO power supply, the source of the fifth NMOS transistor M4 is coupled to the drain of the sixth NMOS transistor M5, and the substrate of the fifth NMOS transistor M4 is connected to the source of the sixth NMOS transistor M5 and ground.

In a typical application scenario, when in the transmitting mode, the voltage value of the first IO control signal OEH is high and approximately equal to the voltage value VDDIO of the IO power supply, then, similar to the circuit principle shown in fig. 2, the sixth NMOS transistor M5 and the fifth NMOS transistor M4 are both in the conducting state, so that the voltage value of the generated first interface signal TG is low; the voltage value of the second interface signal NWELL is approximately equal to the voltage value VDDIO of the IO power supply by the sixth PMOS transistor M1 and the seventh PMOS transistor M2.

In another exemplary application scenario, when the receiving mode is in the receiving mode, and the voltage value of the first IO control signal OEH is low level, based on the circuit connection structure shown in fig. 7, if the voltage value V of the IO port signal is low level_PADGreater than the threshold voltage of the eighth PMOS transistor M3, the eighth PMOS transistor M3 can be always turned on, and when VDDIO of the IO power supply suddenly drops to a low level and the voltage V of the IO port signal is lower than the threshold voltage of the eighth PMOS transistor M3_PADWhen the voltage level is still high, the voltage value of the first interface signal TG is equal to the voltage value of the second interface signal NWELL and is equal to the voltage value V of the IO port signal_PAD。

In this way, with the solution of the third embodiment, when the pull-up circuit for the IO circuit is in the failure protection state, that is, the voltage value VDDIO of the IO power supply is low (for example, the IO power supply is suddenly powered off) and the IO port signal V is in the low level_PADWhen the voltage value of (a) is high level, the generated first interface signal TG and the second interface signal NWELL are transmitted to the circuit described in the first embodiment. Those skilled in the art understand that, in practical applications, the signal output terminal of the first interface signal TG generated in the circuit shown in fig. 7 may be connected to the signal input terminal of the first interface signal TG in the circuit described in the first embodiment; the signal output of the second interface signal NWELL generated in the circuit shown in fig. 7 is connected to the signal input of the second interface signal NWELL in the circuit described above in the first embodiment. For example, the signal output terminals of the first interface signal TG and the second interface signal NWELL in the circuit shown in fig. 7 are respectively connected to the signal output terminals of the circuit shown in the above-mentioned figureThe first interface signal TG and the second interface signal NWELL in the circuit shown in FIG. 5 are connected, and a complete pull-up circuit for an IO circuit is formed in a mode of connecting the circuits shown in FIG. 7 and FIG. 5 in series, so that the voltage value of the IO port signal can be pulled up to a higher value more easily while the current is prevented from flowing backwards from an IO port PAD to an IO power supply, and the circuit design requirement of the minimum value higher than the IO logic output high voltage is met.

Further, compared with the technical solution described in the embodiment shown in fig. 6, in the technical solution of this embodiment, by optimizing the conduction condition of the eighth PMOS transistor M3, the eighth PMOS transistor M3 is more easily conducted, so as to better adapt to the voltage value change of the IO power supply and the IO port signal in the failure protection state.

Fig. 8 is a schematic diagram of a leakage current simulation result according to an embodiment of the present invention. Specifically, fig. 8 shows the result of the leakage current simulation in the pull-up circuit for the IO circuit when the voltage value of the IO port signal is higher than the voltage value VDDIO of the IO power supply in the high voltage tolerant input state.

Wherein, the series curve a represents the leakage current simulation result of the pull-up circuit for the IO circuit, which combines the circuit structures shown in fig. 6 and fig. 4, under different limit conditions; a series curve B represents the simulation result of the leakage current of the pull-up circuit for the IO circuit, combining the circuit structures shown in fig. 6 and 5, under different limit conditions; v_PADThe curve represents the voltage value simulation waveform of the IO port signal; the VDDIO curve represents a voltage value VDDIO simulation waveform of the IO power supply; VDD represents a voltage value simulation waveform of the core power supply VDD; the VOEH curve represents a voltage value simulation waveform of the first IO control signal; the VREN curve represents a voltage value simulation waveform of the pull-up control signal.

In the leakage current simulation result diagram shown in fig. 8, a region 1 is used to represent a given simulation input condition, and regions 2 to 6 are the leakage current simulation results according to the input conditions determined in the region 1. For example, in region 1 shown in FIG. 8 the first IO control signal OEH andthe voltage value of the pull-up control signal is low level (0V), when TT _25 ℃, the voltage value VDD of the core power supply VDD is 1.5V, the voltage value VDDIO of the IO power supply VDDIO is 3.3V, and the voltage value V of the IO port signal is lower than the voltage value VDD of the core power supply VDD, and lower than the voltage value V of the IO port signal_PAD5V; curve a in region 2 indicates a leakage current 512nA obtained by simulation in the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 6 and 4 under the simulation input condition; curve B in region 2 shows that the leakage current obtained by simulation in the pull-up circuit for an IO circuit employing the circuit configurations shown in fig. 6 and 5 described above under the simulation input condition is 591 nA.

Further, on the premise of keeping the voltage values of the first IO control signal OEH and the pull-up control signal at a low level (0V), the curve a in the region 3 represents that under the simulation input condition of FF _ -40 ℃, the voltage value VDD of the preset IO power supply VDD is 1.65V, the voltage value VDDIO of the IO power supply is 3.63V, and the voltage value V of the IO port signal is V_PADIn the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 6 and 4, when 5.5V is used, a leakage current of 93nA is obtained by simulation; curve B in region 3 shows that the leakage current obtained by simulation in the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 6 and 5 is 96nA under the simulation input condition.

Further, on the premise of keeping the voltage values of the first IO control signal OEH and the pull-up control signal at a low level (0V), the curve a in the region 4 represents that the simulation input condition is FF _125 ℃, the voltage value VDD of the core power supply VDD is 1.65V, the voltage value VDDIO of the IO power supply is 3.63V, and the voltage value V of the IO port signal is set to be a low level (0V)_PADWhen the voltage is 5.5V, in the pull-up circuit for the IO circuit having the circuit configuration shown in fig. 6 and 4, the leakage current obtained by simulation is 199 nA; curve B in region 4 shows that the leakage current obtained by simulation in the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 6 and 5 is 210nA under the simulation input condition.

Further, the first IO control signal OEH is maintained andon the premise that the voltage value of the pull-up control signal is low level (0V), the curve a in the region 5 indicates that the simulation input condition is SS _ -40 ℃, the voltage value VDD of the core power supply VDD is 1.35V, the voltage value VDDIO of the IO power supply VDDIO is 2.97V, and the voltage value V of the IO port signal is V_PADWhen the voltage is 4.5V, in the pull-up circuit for the IO circuit using the circuit configurations shown in fig. 6 and 4, the leakage current obtained by simulation is 1.32 uA; curve B in area 5 shows that the leakage current obtained by simulation in the pull-up circuit for the IO circuit using the circuit configurations shown in fig. 6 and 5 is 1.78uA under the simulation input condition.

Further, on the premise of keeping the voltage values of the first IO control signal OEH and the pull-up control signal at a low level (0V), the curve a in the area 6 indicates that the simulation input condition is SS _125 ℃, the voltage value VDD of the core power supply VDD is 1.35V, the voltage value VDDIO of the IO power supply is 2.97V, and the voltage value V of the IO port signal is 2.97V_PADWhen the voltage is 4.5V, in the pull-up circuit for the IO circuit using the circuit configurations shown in fig. 6 and 4, the leakage current obtained by simulation is 774 nA; curve B in region 6 shows that the leakage current obtained by simulation in the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 6 and 5 is 963nA under the simulation input condition.

As can be seen from the simulation results shown in fig. 8, in both circuit configurations represented by the curve a and the curve B, the leakage current flowing from the IO port PAD to the IO power supply is very low and can be almost ignored. It is understood by those skilled in the art that the leakage current simulation result schematic diagram shown in fig. 8 can intuitively show that by using the technical scheme of the embodiment of the present invention, leakage current flowing from an IO port PAD to an IO power supply in a high-voltage tolerant input state can be effectively prevented, and the stability of the pull-up circuit for an IO circuit is improved.

Fig. 9 is a schematic diagram of another simulation result of leakage current according to an embodiment of the present invention. Specifically, fig. 9 shows the result of the leakage current simulation in the pull-up circuit for the IO circuit in a fail-safe state, for example, when the voltage value VDDIO of the IO power supply suddenly drops to a low level while the voltage value of the IO port signal is still at a high level.

Wherein, the series curve a represents the leakage current simulation result of the pull-up circuit for the IO circuit, which combines the circuit structures shown in fig. 7 and fig. 4, under different limit conditions; a series curve B represents the simulation result of the leakage current of the pull-up circuit for the IO circuit, combining the circuit structures shown in fig. 7 and 5, under different limit conditions; v_PADThe curve represents the voltage value simulation waveform of the IO port signal; the VDDIO curve represents a voltage value VDDIO simulation waveform of the IO power supply; VDD represents a voltage value simulation waveform of the core power supply VDD; the VOEH curve represents a voltage value simulation waveform of the first IO control signal; the VREN curve represents a voltage value simulation waveform of the pull-up control signal. It is understood by those skilled in the art that due to the limitation of the size of the drawing, in the same region shown in fig. 9, the leakage currents represented by the curves a and B are too close to each other to cause the overlap of the curves a and B, and therefore, in the schematic diagram of the simulation result of the leakage current shown in fig. 9, one curve is shown in the regions 3 to 7 to represent the curves a and B in the respective regions, but this does not represent that the curves a and B are actually in an overlapping relationship, and those skilled in the art can appropriately enlarge the simulation scale in practical applications to more clearly observe the difference between the curves a and B.

In the schematic diagram of the leakage current simulation result shown in fig. 9, the

regions

1 and 2 are used to represent given simulation input conditions, and the regions 3 to 7 are the leakage current simulation results according to the simulation input conditions determined in the

regions

1 and 2. For example, in region 1 shown in FIG. 9, when TT _25 ℃, the voltage value VDDIO of the IO power supply suddenly drops from 3.3V to 0V and the voltage value V of the IO port signal_PADKept at 3.3V; at the same temperature, the voltage values of the first IO control signal OEH and the pull-up control signal in region 2 are low level (0V) and the voltage value VDD of the core power supply VDD is 1.5V; at this time, a curve a in the region 3 indicates a pull-up power for an IO circuit using the circuit configurations shown in fig. 7 and 4 under the simulation input conditionIn the way, the leakage current obtained by simulation is 86 nA; curve B in region 2 shows a leakage current of 77nA obtained by simulation in the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 7 and 5 described above under the above simulation input conditions.

Further, on the premise of keeping the voltage values of the first IO control signal OEH and the pull-up control signal at a low level (0V), the curve a in the region 4 represents that when the simulation input condition is FF _ -40 ℃, and the voltage value VDD of the core power supply VDD is 1.65V, the voltage value VDDIO of the IO power supply is suddenly decreased from 3.63V to 0V and the voltage value V of the IO port signal is decreased to a low level (0V)_PADIn the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 7 and 4, when the voltage is maintained at 3.63V, the leakage current obtained by simulation is 22 nA; curve B in region 4 shows that the leakage current obtained by simulation in the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 7 and 5 is 19nA under the simulation input condition.

Further, on the premise of keeping the voltage values of the first IO control signal OEH and the pull-up control signal at a low level (0V), the curve a in the region 5 represents that when the simulation input condition is FF _125 ℃, and the voltage value VDD of the core power supply VDD is 1.65V, the voltage value VDDIO of the IO power supply is suddenly decreased from 3.63V to 0V and the voltage value V of the IO port signal is decreased_PADIn the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 7 and 4, when the voltage is maintained at 3.63V, the leakage current obtained by simulation is 39 nA; curve B in region 5 shows that the leakage current obtained by simulation in the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 7 and 5 is 37nA under the simulation input condition.

Further, on the premise of keeping the voltage values of the first IO control signal OEH and the pull-up control signal at a low level (0V), the curve a in the area 6 represents that when the simulation input condition is SS _ -40 ℃, and the voltage value VDD of the core power supply VDD is 1.35V, the voltage value VDDIO of the IO power supply is suddenly decreased from 2.97V to 0V and the voltage value V of the IO port signal is decreased to a low level (0V)_PADWhen the pressure is maintained at 2.967V, the pressure is increasedIn the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 7 and 4 described above, a leakage current of 216nA is obtained by simulation; curve B in region 6 shows that the leakage current obtained by simulation in the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 7 and 5 is 196nA under the simulation input condition.

Further, on the premise of keeping the voltage values of the first IO control signal OEH and the pull-up control signal at a low level (0V), the curve a in the area 7 represents that when the simulation input condition is SS _125 ℃, and the voltage value VDD of the core power supply VDD is 1.35V, the voltage value VDDIO of the IO power supply is suddenly decreased from 2.97V to 0V and the voltage value V of the IO port signal is decreased_PADIn the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 7 and 4, when the voltage is maintained at 2.97V, the leakage current obtained by simulation is 113 nA; curve B in region 7 shows that the leakage current obtained by simulation in the pull-up circuit for an IO circuit using the circuit configurations shown in fig. 7 and 5 is 111nA under the simulation input condition.

As can be seen from the simulation results shown in fig. 9, in both circuit configurations represented by the curve a and the curve B, the leakage current flowing from the IO port PAD to the IO power supply is very low and can be almost ignored. Those skilled in the art understand that the leakage current simulation result schematic diagram shown in fig. 9 can intuitively show that by using the technical scheme of the embodiment of the present invention, leakage current flowing from an IO port PAD to an IO power supply in a failure protection state can be effectively prevented, and the stability of the pull-up circuit for an IO circuit is improved.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A pull-up circuit for an IO circuit, comprising:

the access control module and the pull-up module are connected in series between the IO port and the IO power supply;

the switch module is used for generating an access control signal according to an IO port signal and a received first interface signal, when the IO port is in an input or floating state, the voltage value of the IO port signal is equal to the first interface signal, the access control signal is larger than or equal to the difference value between the IO port signal and a preset threshold voltage, and the IO port signal is a signal on the IO port;

wherein the on-off state of the pull-up module is controlled by the received pull-up control signal;

when the IO port is in an input or floating state, the access control module is turned off or turned on under the control of the access control signal and a received second interface signal, and the voltage value of the second interface signal is equal to the larger one of the voltage value of the IO power supply and the voltage value of the IO port signal; the access control module includes:

a gate of the first PMOS transistor is coupled to the switch module, a substrate of the first PMOS transistor is configured to receive the second interface signal, a source of the first PMOS transistor is directly or indirectly coupled to the IO power supply, and a drain of the first PMOS transistor is directly or indirectly coupled to the IO port;

the drawing-up module includes:

the grid electrode of the second PMOS tube is used for receiving the pull-up control signal, the source electrode of the second PMOS tube is directly or indirectly coupled with the IO power supply, and the drain electrode of the second PMOS tube is directly or indirectly coupled with the IO port.

2. Pull-up circuit for an IO circuit as claimed in claim 1, wherein the switching module comprises:

the gate of each NMOS transistor is coupled to the IO port, wherein the source of the first NMOS transistor is used for receiving the first interface signal, the source of the next NMOS transistor is coupled to the drain of the previous NMOS transistor, and the drain of the last NMOS transistor is coupled to the access control module.

3. The pull-up circuit for an IO circuit as claimed in claim 2, wherein the number of the NMOS transistors included in the switch module is determined by a tradeoff between a pull-up voltage of the IO port signal when the IO port is floated and a leakage current flowing from the IO port to the IO power supply when the voltage value of the IO port signal is higher than the voltage value of the IO power supply.

4. Pull-up circuit for an IO circuit as claimed in claim 1, further comprising:

and the signal generating module is used for generating the first interface signal and the second interface signal.

5. Pull-up circuit for an IO circuit as recited in claim 4, wherein said signal generation module comprises:

and the tolerance signal generating unit is used for generating the first interface signal and the second interface signal when the IO power supply is normally powered and the voltage value of the IO port signal is higher than that of the IO power supply.

6. The pull-up circuit for an IO circuit as claimed in claim 5, wherein the margin signal generating unit includes:

third PMOS pipe, fourth PMOS pipe, fifth PMOS pipe, third NMOS pipe and fourth NMOS pipe, wherein:

the source electrode of the third PMOS tube and the gate electrode of the fourth PMOS tube are connected and coupled with the IO power supply, the drain electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the gate electrode of the third PMOS tube are connected and coupled with the IO port, and the drain electrode and the substrate of the third PMOS tube are coupled with the source electrode and the substrate of the fourth PMOS tube and the substrate of the fifth PMOS tube, so that the second interface signal is determined according to the higher one of the voltage value of the IO port signal and the voltage value of the IO power supply;

the grid electrode of the third NMOS tube is coupled with the IO power supply, and the drain electrode of the fifth PMOS tube is coupled with the drain electrode of the third NMOS tube and is used for generating the first interface signal;

the source electrode of the third NMOS tube is coupled with the drain electrode of the fourth NMOS tube, and the substrate of the third NMOS tube is connected with the source electrode of the fourth NMOS tube and is grounded;

and the grid electrode of the fourth NMOS tube is used for receiving a first IO control signal.

7. The pull-up circuit for an IO circuit as claimed in claim 6, wherein the margin signal generating unit further comprises:

the phase inverter is coupled between the IO power supply and the core power supply, wherein the input end of the phase inverter is used for receiving a second IO control signal, and the output end of the phase inverter is coupled to the grid electrode of the fifth PMOS tube.

8. Pull-up circuit for an IO circuit as recited in claim 4, wherein said signal generation module comprises:

and the failure protection signal generation unit is used for generating the first interface signal and the second interface signal when the voltage value of the IO power supply is low level and the voltage value of the IO port signal is less than or equal to the voltage value of the IO power supply.

9. Pull-up circuit for an IO circuit as claimed in claim 8, wherein the fail-safe signal generation unit comprises:

sixth PMOS pipe, seventh PMOS pipe, eighth PMOS pipe, fifth NMOS pipe and sixth NMOS pipe, wherein:

a source electrode of the sixth PMOS transistor and a gate electrode of the seventh PMOS transistor are connected and coupled with the IO power supply, a drain electrode of the seventh PMOS transistor, a source electrode of the eighth PMOS transistor and a gate electrode of the sixth PMOS transistor are connected and coupled with the IO port, and a substrate and a drain electrode of the sixth PMOS transistor are coupled with a source electrode and a substrate of the seventh PMOS transistor and a substrate of the eighth PMOS transistor, so as to determine the second interface signal according to a higher one of a voltage value of the IO port signal and a voltage value of the IO power supply;

a grid electrode of the eighth PMOS tube is connected with a grid electrode of the sixth NMOS tube and receives a first IO control signal, and a drain electrode of the eighth PMOS tube is coupled with a drain electrode of the fifth NMOS tube and is used for generating the first interface signal;

the grid electrode of the fifth NMOS tube is coupled with the IO power supply, the source electrode of the fifth NMOS tube is coupled with the drain electrode of the sixth NMOS tube, and the substrate of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube and is grounded.