CN102208909A - Level shift circuit - Google Patents
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- CN102208909A CN102208909A CN2010101440392A CN201010144039A CN102208909A CN 102208909 A CN102208909 A CN 102208909A CN 2010101440392 A CN2010101440392 A CN 2010101440392A CN 201010144039 A CN201010144039 A CN 201010144039A CN 102208909 A CN102208909 A CN 102208909A
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Abstract
The invention provides a level shift circuit which is used for shifting high-level input signal into low-level output signal. The level shift circuit comprises: VDDH, VDDL, GND, a shaping circuit and an output circuit. A first stage inverter unit of the shaping circuit comprises a pair of PMOS transistors, a first pair of NMOS transistors and a second pair of NMOS transistors. Drain electrodes of the pair of PMOS transistors are connected with grid electrodes of each other and source electrodes are connected with the VDDH. The first pair of NMOS transistors is connected in series with the second pair of NMOS transistors respectively, wherein the grid electrodes of the series-connected NMOS transistors are mutually connected with each other. The source electrodes of the first pair of NMOS transistors are grounding. The drain electrodes of the second pair of NMOS transistors are respectively connected with the drain electrodes of the pair of PMOS transistors. And the grid electrodes of the second pair of NMOS transistors are respectively connected with input terminal and output terminal of a finally stage inverter unit of the shaping circuit. The second pair of NMOS transistors is depletion-type thick grid transistors. The first pair of NMOS transistors is thin grid type transistors. The level shift circuit has a high speed responsibility and a small circuit delay.
Description
Technical field
The present invention relates to level shifting circuit (Level shift circuit), relate in particular to the level shifting circuit that a kind of low level signal converts high level signal to.
Background technology
In composite power source circuit especially SOC system, the supply power voltage of each circuit unit is also not quite identical, is difficult to unification, and the signal transmission between each circuit unit needs just can link up through conversion; In order to save energy consumption, need to reduce the operating voltage (for example 1.2V) of chip internal usually in addition, but between chip and the chip during transmission signals, still need (for example carry out under the 3.3V～5V) in higher voltage.Therefore, must use the input of level shifting circuit, to realize the level conversion of above-mentioned signal as chip, circuit unit.
In digital circuit, often utilize the CMOS inverter to form level shifting circuit.For example Fig. 1 provides a kind of existing level shifting circuit, comprising: shaping circuit 100, in order to receive the input signal of higher level, described input signal is put in order ripple; Output circuit 200 converts more low level output signal in order to the input signal that will put in order behind the ripple.Wherein shaping circuit 100 comprises the two-stage inverter module of serial connection, and the high order end of each inverter module is connected to low level line VDDL, and low order end is connected to ground wire; Output circuit 200 also comprises the two-stage inverter module of serial connection, and wherein, second level inverter module is the CMOS inverter, and its high order end is connected to high level line VDDH, and low order end is connected to ground wire; First order inverter module comprises a pair of PMOS transistor and pair of NMOS transistors, the drain electrode of this pair pmos transistor is connected with the other side's grid mutually, source electrode is connected with high level line VDDH, this is to the source grounding of NMOS, drain electrode is connected with the drain electrode of this pair pmos transistor respectively, and grid is connected with the input and the output of the last level inverter module of shaping circuit respectively, and the NMOS pipe that grid is connected with the last level inverter module output of shaping circuit, its drain electrode is connected with the second level inverter module of output circuit as the output of this grade inverter module.
In the foregoing circuit, the transistor of output circuit 200 all adopts thick gate transistor, and withstand voltage height, threshold voltage are also higher, but open, response speed is slower.The transistor of shaping circuit 100 then is thin gate transistor, and resistance to pressure is poor, and threshold voltage is relatively low, but open, response speed is very fast relatively.
The operation principle of the described circuit of Fig. 1 is as follows: suppose that input signal is a square wave, then described input signal is through behind the two-stage inverter module of shaping circuit 100, and exporting a high bit level is VDDL, and low bit level is 0 square wave, and with the input signal homophase.Behind the two-stage inverter module via output circuit 200, export a high bit level is VDDH to described square wave again, and low bit level is 0 square wave.It is that the low level signal of VDDL has changed into the high level signal that high bit level is VDDH that said process is about to high bit level.If ignore the delay of inverter module circuit, final output signal should be also and the input signal homophase.
There are the following problems for existing level shifting circuit: in the output circuit 200, in order to bear the high working voltage on the high level line VDDH, inverter modules at different levels have all adopted high voltage bearing thick gate transistor.For ease of explanation, suppose in the first order inverter module of output circuit 200 that NMOS is to being that the current potential pull-down transistor is M1 and M2, wherein the M2 transistor drain is the output of this grade inverter module, and the grid of above-mentioned M1 and M2 is connected to the input or the output of 100 last grades of inverter modules of shaping circuit respectively.Therefore then M1 or the grid of M2 and the electrical potential difference maximum of substrate only are VDDL.Above-mentioned electrical potential difference may will cause M1 or M2 to open less than the turn-on threshold voltage of thick gate transistor, make this grade inverter module produce logic error,, and then cause whole level shifting circuit to lose efficacy.Even M1 and M2 can open, its opening speed is also slower, causes circuit delay excessive.
Summary of the invention
The problem that the present invention solves provides a kind of level shifting circuit, and response speed is fast, and circuit delay is little, and output circuit first order inverter module is easy to generate logic error and the bigger problem of circuit delay in the existing level shifting circuit of solution.
Level shifting circuit provided by the invention is used for converting the input signal of high level to low level output signal, it is characterized in that, comprising:
High level line, low level line and ground wire;
Shaping circuit is coupled between low level line and the ground wire, comprises the inverter module of even level serial connection;
Output circuit, be coupled between high level line and the ground wire, the inverter module that comprises the even level serial connection, wherein first order inverter module comprises a pair of PMOS transistor, first pair nmos transistor and second pair nmos transistor, the drain electrode of this pair pmos transistor is connected with the other side's grid mutually, source electrode is connected with the high level line, described first pair nmos transistor is contacted with second pair nmos transistor respectively, and the grid of the nmos pass transistor of polyphone interconnects, the source grounding of described first nmos pass transistor, the drain electrode of second pair nmos transistor is connected with the drain electrode of this pair pmos transistor respectively, the grid of described second pair nmos transistor is connected with the input and the output of the last level inverter module of shaping circuit respectively, and the nmos pass transistor that grid is connected with the last level inverter module output of shaping circuit, its drain electrode is connected with the second level inverter module of output circuit as the output of this grade inverter module;
Described second nmos pass transistor is the thick gate transistor of depletion type, and first nmos pass transistor is thin gate type transistor.
Optionally, the inverter module of described shaping circuit is the CMOS inverter, and high order end all is connected to the low level line, and low order end all is connected to ground wire.MOS transistor in the described CMOS inverter is thin gate type transistor.
Optionally, the inverter module of described output circuit except that the first order is the CMOS inverter, and high order end all is connected to the high level line, and low order end all is connected to ground wire.MOS transistor in the described CMOS inverter is thick gate type transistor.
In the first order inverter module of described output circuit, this pair pmos transistor is thick gate type transistor; Optionally, also be coupled with nmos pass transistor between first pair nmos transistor of described polyphone and second pair nmos transistor, and the described nmos pass transistor that couples is thin gate type transistor, grid is connected with the low level line.
Compared with prior art; level shifting circuit provided by the invention has the following advantages: the current potential pull-down transistor in the first order inverter module of output circuit is selected thin grid type NMOS for use; and increase the long logical thick grid NMOS of depletion type of one-level, be used to protect above-mentioned thin grid type NMOS.Make the easier unlatching conducting of current potential pull-down transistor, thereby improve response speed, reduce circuit delay.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, feature and advantage will be more clear.Parts same as the prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size in layer and zone.
Fig. 1 is the circuit diagram of existing a kind of level shifting circuit;
Fig. 2 is the circuit diagram of level shifting circuit of the present invention;
Fig. 3 is the functional simulation figure of the described level shifting circuit of Fig. 2.
Fig. 4 is another embodiment schematic diagram of level shifting circuit of the present invention
Embodiment
In the prior art, the first order inverter module of output circuit is a CMOS mirror image inverter circuit, and wherein therefore each transistor has all adopted thick gate type transistor for the withstand voltage demand of the high working voltage that satisfies high level line VDDH.But when the signal maximum level of shaping circuit output only be VDDL, therefore might cause nmos pass transistor that grid is connected with prime to owing to grid voltage is not enough, existence is difficult to open the problem of conducting.The present invention selects the nmos pass transistor of above-mentioned output circuit first order inverter module for use and is thin gate type transistor; and increase the thick grid nmos pass transistor of depletion type pair and its polyphone of one-level normal open; play the dividing potential drop protective effect, improve the opening speed of nmos pass transistor, reduce circuit delay.
Level shifting circuit provided by the invention is used for converting the input signal of high level to low level output signal, comprising:
High level line, low level line and ground wire;
Shaping circuit is coupled between low level line and the ground wire, comprises the inverter module of even level serial connection;
Output circuit, be coupled between high level line and the ground wire, the inverter module that comprises the even level serial connection, wherein first order inverter module comprises a pair of PMOS transistor, first pair nmos transistor and second pair nmos transistor, the drain electrode of this pair pmos transistor is connected with the other side's grid mutually, source electrode is connected with the high level line, described first pair nmos transistor is contacted with second pair nmos transistor respectively, and the grid of the nmos pass transistor of polyphone interconnects, the source grounding of described first nmos pass transistor, the drain electrode of second pair nmos transistor is connected with the drain electrode of this pair pmos transistor respectively, the grid of described second pair nmos transistor is connected with the input and the output of the last level inverter module of shaping circuit respectively, and the nmos pass transistor that grid is connected with the last level inverter module output of shaping circuit, its drain electrode is connected with the second level inverter module of output circuit as the output of this grade inverter module;
Described second nmos pass transistor is the thick gate transistor of depletion type, and first nmos pass transistor is thin gate type transistor.
Optionally, the inverter module of described shaping circuit is the CMOS inverter, and high order end all is connected to the low level line, and low order end all is connected to ground wire.MOS transistor in the described CMOS inverter is thin gate type transistor.
Optionally, the inverter module of described output circuit except that the first order is the CMOS inverter, and high order end all is connected to the high level line, and low order end all is connected to ground wire.MOS transistor in the described CMOS inverter is thick gate type transistor.
In the first order inverter module of described output circuit, this pair pmos transistor is thick gate type transistor; Optionally, also be coupled with nmos pass transistor between first pair nmos transistor of described polyphone and second pair nmos transistor, and the described nmos pass transistor that couples is thin gate type transistor, grid is connected with the low level line.
Below in conjunction with specific embodiment the concrete connection and the operation principle of circuit of the present invention are set forth.
Fig. 2 is a specific embodiment of level shifting circuit of the present invention, and Fig. 3 is the functional simulation figure of node signal in the circuit shown in Figure 2.In conjunction with Fig. 2 and Fig. 3 present embodiment is described.
At first as shown in Figure 2, the level shifting circuit in the present embodiment uses the inverter module of minimum progression for simplifying circuit structure.Described level shifting circuit comprises:
High level line VDDH, low level line VDDL, ground wire GND;
Generally, PMOS or NMOS all are connected substrate in order to eliminate substrate bias effect with its source electrode.Therefore each transistor also links to each other according to above-mentioned connected mode lining source in the foregoing circuit.
Pre-conditioned following, the described circuit of Fig. 2 is carried out functional simulation below.Fig. 3 then is the analogous diagram of specific node signal wherein.
The current potential of supposing high level line VDDH is that the current potential of 5V, low level line VDDH is 1V, and the threshold voltage of thick gate type transistor is 1.8V, and the threshold voltage of thin gate type transistor is 0.7V.At the input Input of the circuit of present embodiment level conversion, the input signal of input square wave type.The high bit level of described input signal is that 0.8V hangs down bit level and is-0.8V.
Above-mentioned input signal will be spacing by shaping behind the process first order inverter module 101 of shaping circuit 100.Because the high order end of first order inverter module 101 is connected in low level line VDDL, low order end is connected in the low level line.When input signal is in high bit level 0.8V, current potential pull up transistor grid and the substrate reverse bias of PMOS, thereby close.The grid of current potential pull-down transistor NMOS and substrate potential difference are that 0.8V surpasses its threshold voltage, thereby conducting.First order inverter module 101 output levels are the level 0 of ground wire.And when input signal was in low bit level-0.8V, pull up transistor grid and the substrate potential difference of PMOS of current potential was that 1.8V surpasses its threshold voltage, thereby conducting.The grid of current potential pull-down transistor NMOS and substrate reverse bias, thereby close.First order inverter module 101 output levels are the level 1V of low level line VDDL.After also promptly passing through first order inverter module 101, be shaped to high bit level 1V, low bit level 0V, and the square wave anti-phase with input signal.After above-mentioned square wave passes through the second level inverter module 102 of shaping circuit 100 again, keep the current potential amplitude constant, obtain the square wave anti-phase with input at its output O point, but this square wave and aforementioned input signal homophase.
In the first order inverter module 201 of described output circuit 200, because the grid of nmos pass transistor M1 and nmos pass transistor M2 is connected to the input and the output of shaping circuit second level inverter module 102, therefore nmos pass transistor M1 always is in opposite unlatching or closed condition with nmos pass transistor M2, and nmos pass transistor M3 and nmos pass transistor M4 are the thick gate transistor of depletion type, be in long logical state, but ducting capacity is still relevant with its grid potential.
It is 1V that the current potential of supposing the output of second level inverter module 102 is in high-order level voltage, and it is 0V that the current potential of its input must be in the low level level voltage.This moment nmos pass transistor M2 and nmos pass transistor M4 conducting, the impedance of both inside is ignored, and makes the current potential of drain electrode B of nmos pass transistor M4 be pulled low to 0V by ground wire.Grid and the substrate potential difference of the PMOS transistor P1 that be connected with above-mentioned B point this moment are VDDH, exceed its threshold voltage, so PMOS transistor P1 conducting, and the current potential that the drain electrode A of PMOS transistor P1 is ordered is pulled up to 5V.The grid of PMOS transistor P2 is communicated with the A point, is in therefore not conducting of high potential.But nmos pass transistor M3 is owing to be in long logical state, and its drain electrode is connected with the A point, and source electrode is connected with nmos pass transistor M1.For the thin gate transistor M3 of depletion type; its grid is connected with the input of second level inverter module 102; current potential is 0V; though can be in conducting state; yet ducting capacity a little less than; exist than significantly impedance between drain electrode and the source electrode, make actual loaded to the voltage between the leakage of nmos pass transistor M1 source be less than VDDH, therefore this moment, nmos pass transistor M3 pair nmos transistor M1 can play the effect that dividing potential drop is protected.Otherwise when the current potential of the output of second level inverter module 102 was in the low level level voltage and is 0V, the path blockade of nmos pass transistor M4 and nmos pass transistor M2, nmos pass transistor M4 pair nmos transistor M2 played the effect of dividing potential drop protection.
From above-mentioned operation principle as can be seen, nmos pass transistor M1 and nmos pass transistor M2 all adopt thin gate type transistor in circuit of the present invention, and therefore the low level signal that prime shaping circuit 100 is exported has responding ability faster, can open immediately.Nmos pass transistor M3 and nmos pass transistor M4 then play the dividing potential drop protective effect, make nmos pass transistor M1 and nmos pass transistor M2 be not easy and are damaged because of the high voltage in the drain electrode.
In addition; as shown in Figure 4; in order further to improve the dividing potential drop protection of pair nmos transistor M1 and nmos pass transistor M2; can also be between the nmos pass transistor M1 and nmos pass transistor M3 of series connection, also be coupled with nmos pass transistor M5, nmos pass transistor M6 respectively between nmos pass transistor M2 and the nmos pass transistor M4; and described nmos pass transistor that couples 5 and nmos pass transistor M6 are thin gate type transistor, and grid is connected with low level line VDDL.Above-mentioned nmos pass transistor 5 and nmos pass transistor M6 are in normal open state, can select for use the bigger transistor of relative conduction impedance to realize the dividing potential drop ability.
Above-mentioned first order inverter module 201 is coupled between high level line VDDH and the ground wire GND, therefore through behind this grade inverter module, from the square wave that the drain electrode of nmos pass transistor M4 is exported, high bit level is 5V, low bit level is 0V, and square wave phase is opposite with aforementioned input signal.Final above-mentioned square wave is again via second level inverter module 202, finally obtain and the input signal homophase at the output Output of whole level shifting circuit end, but high bit level is 5V, and low bit level is the output signal of 0V, thereby finishes the level conversion of input/output signal.
It is pointed out that in the functional simulation figure of Fig. 3 the waveform of each node is owing to the existence of circuit delay, so impossible positive or anti-phase fully, but has certain hysteresis quality to exist.
The foregoing description, the inverter module level number average of shaping circuit and output circuit only is example with the two-stage, when reality is used, inverter module through odd level, the opposite signal of phase place will be obtained, and inverter module progression is many more, and the delay of circuit is just big more, but waveform quality also can correspondingly improve.Therefore should select according to concrete needs.Its operation principle and invention essence should be identical with present embodiment.Repeat no more.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (7)
1. a level shifting circuit is used for converting the input signal of high level to low level output signal,
It is characterized in that, comprising:
High level line, low level line and ground wire;
Shaping circuit is coupled between low level line and the ground wire, comprises the inverter module of even level serial connection;
Output circuit, be coupled between high level line and the ground wire, the inverter module that comprises the even level serial connection, wherein first order inverter module comprises a pair of PMOS transistor, first pair nmos transistor and second pair nmos transistor, the drain electrode of this pair pmos transistor is connected with the other side's grid mutually, source electrode is connected with the high level line, described first pair nmos transistor is contacted with second pair nmos transistor respectively, and the grid of the nmos pass transistor of polyphone interconnects, the source grounding of described first nmos pass transistor, the drain electrode of second pair nmos transistor is connected with the drain electrode of this pair pmos transistor respectively, the grid of described second pair nmos transistor is connected with the input and the output of the last level inverter module of shaping circuit respectively, and the nmos pass transistor that grid is connected with the last level inverter module output of shaping circuit, its drain electrode is connected with the second level inverter module of output circuit as the output of this grade inverter module;
Described second nmos pass transistor is the thick gate transistor of depletion type, and first nmos pass transistor is thin gate type transistor.
2. level shifting circuit as claimed in claim 1 is characterized in that the inverter module of described shaping circuit is the CMOS inverter, and high order end all is connected to the low level line, and low order end all is connected to ground wire.
3. level shifting circuit as claimed in claim 2 is characterized in that, the MOS transistor in the described CMOS inverter is thin gate type transistor.
4. level shifting circuit as claimed in claim 1 is characterized in that, the inverter module of described output circuit except that the first order is the CMOS inverter, and high order end all is connected to the high level line, and low order end all is connected to ground wire.
5. level shifting circuit as claimed in claim 4 is characterized in that, the MOS transistor in the described CMOS inverter is thick gate type transistor.
6. level shifting circuit as claimed in claim 1 is characterized in that, described this pair pmos transistor is thick gate type transistor.
7. level shifting circuit as claimed in claim 6, it is characterized in that, it is right also to be coupled with nmos pass transistor between first pair nmos transistor of described polyphone and second pair nmos transistor, and the described nmos pass transistor that couples is thin gate type transistor, and grid all is connected with the low level line.
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| CN201010144039.2A CN102208909B (en) | 2010-03-31 | 2010-03-31 | Level shifting circuit |
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| CN201010144039.2A CN102208909B (en) | 2010-03-31 | 2010-03-31 | Level shifting circuit |
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| CN102208909B CN102208909B (en) | 2015-10-21 |
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| CN102522894A (en) * | 2011-12-21 | 2012-06-27 | 北京自动测试技术研究所 | Voltage conversion circuit for power device test system |
| CN102571069A (en) * | 2012-03-19 | 2012-07-11 | 中科芯集成电路股份有限公司 | Single-power-supply positive and negative logic conversion circuit |
| CN102904535A (en) * | 2012-10-22 | 2013-01-30 | 上海集成电路研发中心有限公司 | Power amplifier |
| CN102983822A (en) * | 2012-09-18 | 2013-03-20 | 上海集成电路研发中心有限公司 | Power amplifier |
| CN104184458A (en) * | 2014-09-16 | 2014-12-03 | 上海坤锐电子科技有限公司 | Level shifter with power-on resetting function |
| CN104639151A (en) * | 2014-12-23 | 2015-05-20 | 苏州宽温电子科技有限公司 | Positive-high-voltage level conversion circuit |
| CN103178829B (en) * | 2011-12-20 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Level shift circuit |
| CN106899289A (en) * | 2017-02-23 | 2017-06-27 | 电子科技大学 | A kind of controllable type level displacement circuit |
| CN107094012A (en) * | 2017-03-22 | 2017-08-25 | 尚睿微电子（上海）有限公司 | A kind of level shifting circuit and method |
| CN103297034B (en) * | 2012-02-28 | 2017-12-26 | 恩智浦美国有限公司 | Voltage level shifter |
| CN107819462A (en) * | 2017-09-08 | 2018-03-20 | 灿芯创智微电子技术（北京）有限公司 | A kind of novel high-pressure circuit interface compatible with low pressure |
| CN108964651A (en) * | 2017-05-17 | 2018-12-07 | 中芯国际集成电路制造(北京)有限公司 | A kind of output circuit and electronic device |
| CN109541347A (en) * | 2018-11-26 | 2019-03-29 | 国网冀北电力有限公司唐山供电公司 | A kind of sensor for electrical energy measurement |
| CN109756222A (en) * | 2017-11-03 | 2019-05-14 | 展讯通信（上海）有限公司 | A kind of level shifting circuit and chip system |
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| CN103178829B (en) * | 2011-12-20 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Level shift circuit |
| CN102522894B (en) * | 2011-12-21 | 2014-05-07 | 北京自动测试技术研究所 | Voltage conversion circuit for power device test system |
| CN102522894A (en) * | 2011-12-21 | 2012-06-27 | 北京自动测试技术研究所 | Voltage conversion circuit for power device test system |
| CN103297034B (en) * | 2012-02-28 | 2017-12-26 | 恩智浦美国有限公司 | Voltage level shifter |
| CN102571069A (en) * | 2012-03-19 | 2012-07-11 | 中科芯集成电路股份有限公司 | Single-power-supply positive and negative logic conversion circuit |
| CN102571069B (en) * | 2012-03-19 | 2015-03-04 | 中科芯集成电路股份有限公司 | Single-power-supply positive and negative logic conversion circuit |
| CN102983822A (en) * | 2012-09-18 | 2013-03-20 | 上海集成电路研发中心有限公司 | Power amplifier |
| CN102904535A (en) * | 2012-10-22 | 2013-01-30 | 上海集成电路研发中心有限公司 | Power amplifier |
| CN104184458A (en) * | 2014-09-16 | 2014-12-03 | 上海坤锐电子科技有限公司 | Level shifter with power-on resetting function |
| CN104639151A (en) * | 2014-12-23 | 2015-05-20 | 苏州宽温电子科技有限公司 | Positive-high-voltage level conversion circuit |
| CN106899289A (en) * | 2017-02-23 | 2017-06-27 | 电子科技大学 | A kind of controllable type level displacement circuit |
| CN107094012A (en) * | 2017-03-22 | 2017-08-25 | 尚睿微电子（上海）有限公司 | A kind of level shifting circuit and method |
| WO2018171249A1 (en) * | 2017-03-22 | 2018-09-27 | 尚睿微电子（上海）有限公司 | Level shift circuit and method |
| CN107094012B (en) * | 2017-03-22 | 2019-12-10 | 尚睿微电子（上海）有限公司 | Level conversion circuit and method |
| CN108964651A (en) * | 2017-05-17 | 2018-12-07 | 中芯国际集成电路制造(北京)有限公司 | A kind of output circuit and electronic device |
| CN108964651B (en) * | 2017-05-17 | 2022-04-26 | 中芯国际集成电路制造(北京)有限公司 | Output circuit and electronic device |
| CN107819462A (en) * | 2017-09-08 | 2018-03-20 | 灿芯创智微电子技术（北京）有限公司 | A kind of novel high-pressure circuit interface compatible with low pressure |
| CN109756222A (en) * | 2017-11-03 | 2019-05-14 | 展讯通信（上海）有限公司 | A kind of level shifting circuit and chip system |
| CN109541347A (en) * | 2018-11-26 | 2019-03-29 | 国网冀北电力有限公司唐山供电公司 | A kind of sensor for electrical energy measurement |
| CN109541347B (en) * | 2018-11-26 | 2020-11-06 | 国网冀北电力有限公司唐山供电公司 | Sensor for electric energy metering |
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| CN102208909B (en) | 2015-10-21 |
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