CN107528581A - Level shifting circuit - Google Patents

Level shifting circuit Download PDF

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Publication number
CN107528581A
CN107528581A CN201710878695.7A CN201710878695A CN107528581A CN 107528581 A CN107528581 A CN 107528581A CN 201710878695 A CN201710878695 A CN 201710878695A CN 107528581 A CN107528581 A CN 107528581A
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CN
China
Prior art keywords
circuit
pull
voltage
nmos pass
level shifting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710878695.7A
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Chinese (zh)
Inventor
孟晨
王富中
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Galaxycore Shanghai Ltd Corp
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Galaxycore Shanghai Ltd Corp
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Priority to CN201710878695.7A priority Critical patent/CN107528581A/en
Publication of CN107528581A publication Critical patent/CN107528581A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Abstract

The present invention relates to a kind of level shifting circuit.Level shifting circuit includes：Pull-up circuit, it is connected to the first positive supply；Pull-down circuit, is connected to the second positive supply and public negative supply, and second positive supply provides two input signals of opposite in phase to the pull-down circuit；Pressure limiting circuit, it is connected between the pull-up circuit and the pull-down circuit, and connects a bias voltage；Wherein, the pull-down circuit is using operating voltage is low, speed is fast, is operated in the type of device in input power domain, the pressure limiting circuit and the pull-up circuit using operating voltage is high, speed is slow, is operated in the type of device in out-put supply domain.The present invention can improve the performance of level shifting circuit, and reduce the area of level shifting circuit.

Description

Level shifting circuit
Technical field
The present invention relates to IC design technical field, more particularly to a kind of level shifting circuit.
Background technology
In modern integrated circuits system, in order to obtain at a high speed, its core logic（Core circuit）Unit generally exists Worked under the low voltages such as 1.0V voltages, and its input/output（Intput/Output）Unit is based on stable consideration, generally exists The operating at voltages such as 3.3V, 2.5V or 1.8V.Due to the difference of operating voltage, core logic unit and I/O unit it Between and other many situations need to set with level shifting circuit, electricity is converted into the logical signal for enabling level absolute value relatively low The higher logical signal of flat absolute value, this change-over circuit are referred to as level shifting circuit.
The level shifting circuit of prior art, including PMOS transistor PG1 and PG2, nmos pass transistor are given in Fig. 1 NG1 and NG2, input signal source INp and INn high level be core logic unit operating voltage, this input signal original INp and INn is the modulated pulse signal of the square wave of a pair of opposite in phase, and its high voltage is generally 1.9V ~ 1.2V.Voltage source VDDM is The operating voltage of I/O unit, generally 2.5V ~ 3.3V.Using the high level of input signal source INp input signal as 1.2V, voltage source VDDM voltage illustrate exemplified by being 3.3V.
When input signal INp is high level, nmos pass transistor NG1 conductings, nmos pass transistor NG2 grid voltage is low Level, nmos pass transistor NG2 cut-offs, now, output voltage OUTn are pulled down to low level, PMOS transistor PG2 conductings, output End OUTp voltage turns into VDDM voltages, PMOS transistor PG1 cut-offs.When input signal INp is low level, NMOS crystal Pipe NG1 ends, and nmos pass transistor NG2 grid voltage is high level, and nmos pass transistor NG2 is turned on, now, output voltage OUTp Low level, PMOS transistor PG1 conductings are pulled down to, output end OUTn voltage turns into VDDM, PMOS transistor PG2 cut-offs.
In the prior art, NG1, NG2, PG1, PG2 are same type of device, belong to that operating voltage is high, speed is slow, work Make the type of device in out-put supply domain, and the nmos pass transistor NG1 and NG2 in level shifting circuit need sufficiently large chi It is very little to ensure normally to overturn under various power supplys, technique, temperature conditions so that the area of level shifting circuit compared with Greatly.
The content of the invention
It is an object of the invention to provide a kind of level shifting circuit, solves level shifting circuit area in the prior art Greatly, slow technical problem is overturn.
In order to solve the above-mentioned technical problem, the present invention provides a kind of level shifting circuit, including：
Pull-up circuit, it is connected to the first positive supply；
Pull-down circuit, is connected to the second positive supply and public negative supply or ground terminal, and second positive supply provides opposite in phase Two input signals are to the pull-down circuit；
Pressure limiting circuit, it is connected between the pull-up circuit and the pull-down circuit, and connects a bias voltage；
Wherein, the pull-down circuit improves electricity using operating voltage is low, speed is fast, is operated in the type of device in input power domain Flat transfer capability, reduce area；The pressure limiting circuit and the pull-up circuit are using operating voltage is high, speed is slow, it is defeated to be operated in Go out the type of device of power domain.
Optionally, the pull-up circuit includes：
First PMOS transistor, its source electrode connect first positive supply, drain electrode connection first node, the section of grid connection second Point；
Second PMOS transistor, its source electrode connect first positive supply, drain electrode connection section point, grid connection first segment Point；
First PMOS transistor and second PMOS transistor are that operating voltage is high, speed is slow, are operated in out-put supply The type of device in domain.
Optionally, the pressure limiting circuit ensures that the drain voltage of the pull-down circuit device is less than or equal to the biased electrical Pressure.
Optionally, in addition to bias-voltage generating circuit, the bias-voltage generating circuit export the bias voltage extremely The pressure limiting circuit.
Optionally, the pressure limiting circuit includes：
First nmos pass transistor, its connection first node that drains, grid connect the bias-voltage generating circuit；
Second nmos pass transistor, its connection section point that drains, grid connect the bias-voltage generating circuit；
First nmos pass transistor and second nmos pass transistor are that operating voltage is high, speed is slow, are operated in out-put supply The type of device in domain.
Optionally, the pull-down circuit includes：
3rd nmos pass transistor, it, which drains, connects the source electrode of first nmos pass transistor, and source electrode connects public negative supply or ground End, grid connect an input signal；
4th nmos pass transistor, it, which drains, connects the source electrode of second nmos pass transistor, and source electrode connects public negative supply or ground End, grid connect another input signal；
3rd nmos pass transistor and the 4th nmos pass transistor are that operating voltage is low, speed is fast, are operated in input power The type of device in domain.
Accordingly, another aspect of the present invention also provides a kind of level shifting circuit, including：
Pull-down circuit, it is connected to the first negative supply；
Pull-up circuit, is connected to the second negative supply and public positive supply or ground terminal, and second negative supply provides opposite in phase Two input signals are to the pull-up circuit；
Pressure limiting circuit, it is connected between the pull-up circuit and the pull-down circuit, and connects a bias voltage；
Wherein, the pull-up circuit structure improves using operating voltage is low, speed is fast, is operated in the type of device in input power domain Level conversion ability, reduce area；The pressure limiting circuit and the pull-down circuit are using operating voltage is high, speed is slow, is operated in The type of device in out-put supply domain.
Optionally, the pull-down circuit includes：
First nmos pass transistor, its source electrode connect first negative supply, drain electrode connection first node, the section of grid connection second Point；
Second nmos pass transistor, its source electrode connect first negative supply, drain electrode connection section point, grid connection first segment Point；
First nmos pass transistor and second nmos pass transistor are that operating voltage is high, speed is slow, are operated in out-put supply The type of device in domain.
Optionally, the pressure limiting circuit ensures that the drain voltage of the pull-up circuit device is more than or equal to the biased electrical Pressure.
Optionally, in addition to bias-voltage generating circuit, the bias-voltage generating circuit export the bias voltage extremely The pressure limiting circuit.
Optionally, the pressure limiting circuit includes：
First PMOS transistor, its connection first node that drains, grid connect the bias-voltage generating circuit；
Second PMOS transistor, its connection section point that drains, grid connect the bias-voltage generating circuit；
First PMOS transistor and second PMOS transistor are that operating voltage is high, speed is slow, are operated in out-put supply The type of device in domain.
Optionally, the pull-up circuit includes：
3rd PMOS transistor, it, which drains, connects the source electrode of first PMOS transistor, and source electrode connects public positive supply or ground End, grid connect an input signal；
4th PMOS transistor, it, which drains, connects the source electrode of second PMOS transistor, and source electrode connects public positive supply or ground End, grid connect another input signal；
3rd PMOS transistor and the 4th PMOS transistor are that operating voltage is low, speed is fast, are operated in input power The type of device in domain.
Relative to prior art, level shifting circuit of the invention, integrated circuit have the advantages that：
1）In level shifting circuit, low-voltag transistor, the ability of low-voltag transistor are used in pull-down circuit or pull-up circuit By force, area is small, speed is fast, and pressure limiting circuit can ensure that the operating voltage domain of pull-down circuit or pull-up circuit is low-voltage, from And the performance of level shifting circuit can be improved.
2）Multiple level shifting circuits and a bias-voltage generating circuit are used in integrated circuit, bias voltage produces electricity Road provides the bias voltage of low-voltage for the pressure limiting circuit in each level shifting circuit, and multiple level shifting circuits share one Individual bias-voltage generating circuit, so as to save the area of whole chip.
Brief description of the drawings
Fig. 1 is the schematic diagram of level shifting circuit in the prior art；
Fig. 2 is the schematic diagram of level shifting circuit in the present invention；
Fig. 3 is the schematic diagram of level shifting circuit in the embodiment of the present invention one；
Fig. 4 is the schematic diagram of level shifting circuit in the embodiment of the present invention two.
Embodiment
Many details are elaborated in the following description in order to fully understand the present invention.But the present invention can be with Much it is different from other manner described here to implement, those skilled in the art can be in the situation without prejudice to intension of the present invention Under do similar popularization, therefore the present invention is not limited to the specific embodiments disclosed below.
Secondly, the present invention is described in detail using schematic diagram, when the embodiment of the present invention is described in detail, for purposes of illustration only, institute It is example to state schematic diagram, and it should not limit the scope of protection of the invention herein.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with accompanying drawing to the present invention Level shifting circuit be described in detail.
Embodiment one
With reference to shown in figure 2, level shifting circuit provided by the invention includes pull-up circuit 10, pull-down circuit 20, pressure limiting circuit 30 and bias-voltage generating circuit 40.
With reference to shown in figure 3, the pull-up circuit 10 is connected to the first positive supply VDDM, for the voltage in circuit to be pulled up To the first positive supply VDDM voltage, specifically, the pull-up circuit 10 includes the first PMOS transistor PMV1 and the 2nd PMOS Transistor PMV2, the first PMOS transistor PMV1 source electrode connect the first positive supply VDDM, drain electrode connection first node S1 （Output end OUTn）, grid connection section point S2（Output end OUTp）, the second PMOS transistor PMV2 source electrode connection described in First positive supply VDDM, drain electrode connection section point S2, grid connection first node S1.Wherein, the first positive supply VDDM Voltage be 2.8V ~ 5V, so as to which pull-up circuit 10 is using operating voltage is high, speed is slow, is operated in the device in defeated out-put supply domain Type, that is, the first positive supply VDDM is operated in level section between public negative supply or ground terminal GND, to be resistant to the first positive supply VDDM voltage, it is 2.8V ~ 5V so as to the voltage of output end OUTn and OUTp high level, is I/O unit（I/O units） Voltage is provided.
The pressure limiting circuit 30 is connected between the pull-up circuit 10 and the pull-down circuit 20, is produced by bias voltage Raw circuit 40 provides the bias voltage Vbias of low-voltage to the pressure limiting circuit 30, for by the operating voltage of pull-down circuit 20 Domain is controlled in the range of public negative supply to Vbias.Specifically, the pressure limiting circuit 30 includes the first nmos pass transistor NMV1 Drain electrode with the second nmos pass transistor NMV2, the first nmos pass transistor NMV1 connects first node S1, and grid connects the biasing Bias voltage Vbias, the second nmos pass transistor NMV2 that voltage generation circuit 40 exports drain electrode connection section point S2, grid Connect the bias voltage Vbias that the bias-voltage generating circuit 40 exports.The pressure limiting circuit 30 is operating voltage height, speed Slowly the type of device in out-put supply domain, is operated in, is resistant to the first positive supply VDDM voltage, and the bias voltage Vbias voltage is 1.2V ~ 1.5V so that the first nmos pass transistor NMV1 source electrode and the second nmos pass transistor NMV2 drain electrode Voltage be no more than 1.2V ~ 1.5V.
The pull-down circuit 20 is connected to public negative supply or ground terminal and the second positive supply VDDL, with connection in the present embodiment Illustrated exemplified by ground terminal GND, pull-down circuit 20 is used to the current potential in circuit being pulled down to GND, and pull-down circuit 20 is patrolled with core The operating voltage of volume unit is identical, and for example, 1.2V ~ 1.5V, then the voltage of the second positive supply VDDL is 1.2V ~ 1.5V, from And pull-down circuit 20 is operated in the second negative electricity using operating voltage is low, speed is fast, is operated in the type of device in input power domain Source VDDL is to the level section of public negative supply or ground terminal GND.Specifically, the pull-down circuit includes the 3rd nmos pass transistor NLV3 and the 4th nmos pass transistor NLV4, the 3rd nmos pass transistor NLV3 the first nmos pass transistor NMV1's of drain electrode connection Source electrode, source electrode connection ground terminal GND, grid connection input signal INp, the 4th nmos pass transistor NLV4 drain electrode connect the 2nd NMOS Transistor NMV2 source electrode, source electrode connection ground terminal GND, grid connection input signal INn.Wherein, the input signal INp and defeated Enter the voltage signal that signal INn is a pair of opposite in phase that the second positive supply VDDL is provided, the first input signal INp and the Two input signal INn voltage domain is from public negative supply to the second positive supply VDDL voltage domain.
In the present embodiment, pressure limiting circuit causes the drain voltage of pull-down circuit device to be less than or equal to bias voltage, specifically, The first nmos pass transistor NMV1 and the second nmos pass transistor NMV2 is middle piezoelectric crystal, its voltage domain be from GND to VDDM, So that first node S1 and section point S2 are resistant to high pressure, and bias voltage Vbias voltage is chosen as VDDL so that the Three nmos pass transistor NLV3 and the 4th nmos pass transistor NLV4 drain voltage is no more than VDDL, the 3rd nmos pass transistor NLV3 and 4th nmos pass transistor NLV4 is low voltage transistor, and the performance of low voltage transistor is better than middle pressure pipe, and area is smaller, so as to low pressure Pull-down circuit reduce the area of level shifting circuit, improve the performance of level shifting circuit.
Furthermore, it is necessary to explanation, integrated circuit generally include multiple level shifting circuits, also, each level conversion Circuit shares same bias-voltage generating circuit, i.e. bias-voltage generating circuit is the pressure limiting electricity in each level shifting circuit Road provides the bias voltage of low-voltage so that the area of level shifting circuit is small, so as to save the area of whole integrated circuit.
Embodiment two
With reference to shown in figure 2 and 4, level shifting circuit provided by the invention includes pull-up circuit 10, pull-down circuit 20, pressure limiting circuit 30 and bias-voltage generating circuit 40.Unlike embodiment one, the level shifting circuit in the present embodiment is negative pressure Level shifting circuit.
The pull-down circuit 20 connects the first negative supply VSSM, for the voltage in circuit to be pulled down into the first negative supply VSSM magnitude of voltage.First negative supply VSSM voltage is -5V ~ -2.8V, so as to which the pull-down circuit 20 uses operating voltage Height, speed are slow, are operated in the type of device in out-put supply domain, that is, are operated in the first negative supply VSSM to public positive supply GND's Level section.Specifically, pull-down circuit 20 includes the first nmos pass transistor NVM1 and the second nmos pass transistor NVM2.First NMOS Transistor NVM1 source electrode connects the first negative supply VSSM, drain electrode connection first node S1, grid connection section point S2, Second nmos pass transistor NVM2 source electrode connects the first negative supply VSSM, drain electrode connection section point S2, grid connection the One node S1.
The pressure limiting circuit 30 is connected between pull-up circuit 10 and pull-down circuit 20, passes through bias-voltage generating circuit 40 The bias voltage Vbias of low-voltage is provided to the pressure limiting circuit 20, the pressure limiting circuit ensures the pull-up circuit device Drain voltage is more than or equal to the bias voltage.In the present embodiment, pressure limiting circuit 30 is using operating voltage is high, speed is slow, work Type of device in out-put supply domain, the pressure limiting circuit 30 are resistant to the first negative supply VSSM voltage.Specifically, pressure limiting The drain electrode that circuit 30 includes the first PMOS transistor PMV1 and the second PMOS transistor PMV2, the first PMOS transistor PMV1 connects First node S1, grid connect the bias-voltage generating circuit 40, the second PMOS transistor PMV2 section of drain electrode connection second Point S2, grid connect the bias-voltage generating circuit 40.In addition, the voltage domain of the bias voltage Vbias be -1.5V ~ - 1.2V so that the first PMOS transistor PMV1 source electrode and the second PMOS transistor PMV2 drain voltage not less than -1.2V ~ - 1.5V。
The pull-up circuit 10 is connected to the second negative supply VSSL and public positive supply or ground terminal, in the present embodiment, with ground Illustrated exemplified by the GND of end, upper pull-up voltage is connected with core cell, identical with the voltage domain of core cell, second negative electricity Source VSSL voltage is -1.2V ~ -1.5V, and the second negative supply VSSL provides two input signals of opposite in phase to pull-up circuit 10, so as to which the pull-up circuit 10 is using operating voltage is low, speed is fast, is operated in the type of device in input power domain, that is, work In the second negative supply VSSL to public positive supply or ground terminal GND level device.Pull-up circuit 10 includes the 3rd PMOS transistor PLV3 and the 4th PMOS transistor PLV4, specifically, the 3rd PMOS transistor PLV3 drain electrode connects the first PMOS crystal Pipe PMV1 source electrode, source electrode connection ground terminal GND, grid connect an input signal INp, the 4th PMOS transistor PLV4 drain electrode The source electrode of the second PMOS transistor PMV2, source electrode connection ground terminal GND are connected, grid connects another input signal INn.
In summary, in the present invention, low-voltag transistor is used in pull-down circuit or pull-up circuit, low-voltag transistor Ability is strong, area is small, and pressure limiting circuit can ensure that the voltage domain of pull-down circuit or pull-up circuit is low-voltage, so as to carry The performance of high level change-over circuit, save area.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area Technical staff without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this hair Bright technical scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention Any simple modifications, equivalents, and modifications made to above example of technical spirit, belong to technical solution of the present invention Protection domain.

Claims (12)

  1. A kind of 1. level shifting circuit, it is characterised in that including：
    Pull-up circuit, it is connected to the first positive supply；
    Pull-down circuit, is connected to the second positive supply and public negative supply or ground terminal, and second positive supply provides opposite in phase Two input signals are to the pull-down circuit；
    Pressure limiting circuit, it is connected between the pull-up circuit and the pull-down circuit, and connects a bias voltage；
    Wherein, the pull-down circuit improves electricity using operating voltage is low, speed is fast, is operated in the type of device in input power domain Flat transfer capability, reduce area；The pressure limiting circuit and the pull-up circuit are using operating voltage is high, speed is slow, it is defeated to be operated in Go out the type of device of power domain.
  2. 2. level shifting circuit according to claim 1, it is characterised in that the pull-up circuit includes：
    First PMOS transistor, its source electrode connect first positive supply, drain electrode connection first node, the section of grid connection second Point；
    Second PMOS transistor, its source electrode connect first positive supply, drain electrode connection section point, grid connection first segment Point；
    First PMOS transistor and second PMOS transistor are that operating voltage is high, speed is slow, are operated in out-put supply The type of device in domain.
  3. 3. level shifting circuit according to claim 1, it is characterised in that the pressure limiting circuit ensures the pull-down circuit The drain voltage of device is less than or equal to the bias voltage.
  4. 4. level shifting circuit according to claim 1, it is characterised in that described also including bias-voltage generating circuit Bias-voltage generating circuit exports the bias voltage to the pressure limiting circuit.
  5. 5. level shifting circuit according to claim 4, it is characterised in that the pressure limiting circuit includes：
    First nmos pass transistor, its connection first node that drains, grid connect the bias-voltage generating circuit；
    Second nmos pass transistor, its connection section point that drains, grid connect the bias-voltage generating circuit；
    First nmos pass transistor and second nmos pass transistor are that operating voltage is high, speed is slow, are operated in out-put supply The type of device in domain.
  6. 6. level shifting circuit according to claim 5, it is characterised in that the pull-down circuit includes：
    3rd nmos pass transistor, it, which drains, connects the source electrode of first nmos pass transistor, and source electrode connects public negative supply or ground End, grid connect an input signal；
    4th nmos pass transistor, it, which drains, connects the source electrode of second nmos pass transistor, and source electrode connects public negative supply or ground End, grid connect another input signal；
    3rd nmos pass transistor and the 4th nmos pass transistor are that operating voltage is low, speed is fast, are operated in input power The type of device in domain.
  7. A kind of 7. level shifting circuit, it is characterised in that including：
    Pull-down circuit, it is connected to the first negative supply；
    Pull-up circuit, is connected to the second negative supply and public positive supply or ground terminal, and second negative supply provides opposite in phase Two input signals are to the pull-up circuit；
    Pressure limiting circuit, it is connected between the pull-up circuit and the pull-down circuit, and connects a bias voltage；
    Wherein, the pull-up circuit structure improves using operating voltage is low, speed is fast, is operated in the type of device in input power domain Level conversion ability, reduce area；The pressure limiting circuit and the pull-down circuit are using operating voltage is high, speed is slow, is operated in The type of device in out-put supply domain.
  8. 8. level shifting circuit according to claim 7, it is characterised in that the pull-down circuit includes：
    First nmos pass transistor, its source electrode connect first negative supply, drain electrode connection first node, the section of grid connection second Point；
    Second nmos pass transistor, its source electrode connect first negative supply, drain electrode connection section point, grid connection first segment Point；
    First nmos pass transistor and second nmos pass transistor are that operating voltage is high, speed is slow, are operated in out-put supply The type of device in domain.
  9. 9. level shifting circuit according to claim 7, it is characterised in that the pressure limiting circuit ensures the pull-up circuit The drain voltage of device is more than or equal to the bias voltage.
  10. 10. level shifting circuit according to claim 7, it is characterised in that described also including bias-voltage generating circuit Bias-voltage generating circuit exports the bias voltage to the pressure limiting circuit.
  11. 11. level shifting circuit according to claim 10, it is characterised in that the pressure limiting circuit includes：
    First PMOS transistor, its connection first node that drains, grid connect the bias-voltage generating circuit；
    Second PMOS transistor, its connection section point that drains, grid connect the bias-voltage generating circuit；
    First PMOS transistor and second PMOS transistor are that operating voltage is high, speed is slow, are operated in out-put supply The type of device in domain.
  12. 12. level shifting circuit according to claim 11, it is characterised in that the pull-up circuit includes：
    3rd PMOS transistor, it, which drains, connects the source electrode of first PMOS transistor, and source electrode connects public positive supply or ground End, grid connect an input signal；
    4th PMOS transistor, it, which drains, connects the source electrode of second PMOS transistor, and source electrode connects public positive supply or ground End, grid connect another input signal；
    3rd PMOS transistor and the 4th PMOS transistor are that operating voltage is low, speed is fast, are operated in input power The type of device in domain.
CN201710878695.7A 2017-09-26 2017-09-26 Level shifting circuit Pending CN107528581A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112383298A (en) * 2021-01-18 2021-02-19 灿芯半导体(上海)有限公司 DDR (double data Rate) sending circuit
CN113285707A (en) * 2020-02-19 2021-08-20 圣邦微电子（北京）股份有限公司 Voltage level conversion circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6084459A (en) * 1996-11-28 2000-07-04 Lg Semicon Co., Ltd. Voltage level shifting circuit
US7030678B1 (en) * 2004-02-11 2006-04-18 National Semiconductor Corporation Level shifter that provides high-speed operation between power domains that have a large voltage difference
CN101123430A (en) * 2006-08-10 2008-02-13 中芯国际集成电路制造(上海)有限公司 Level conversion circuit
CN101741376A (en) * 2008-11-18 2010-06-16 台湾积体电路制造股份有限公司 Ultra-low voltage level shifting circuit
CN207559971U (en) * 2017-09-26 2018-06-29 格科微电子（上海）有限公司 Level shifting circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6084459A (en) * 1996-11-28 2000-07-04 Lg Semicon Co., Ltd. Voltage level shifting circuit
US7030678B1 (en) * 2004-02-11 2006-04-18 National Semiconductor Corporation Level shifter that provides high-speed operation between power domains that have a large voltage difference
CN101123430A (en) * 2006-08-10 2008-02-13 中芯国际集成电路制造(上海)有限公司 Level conversion circuit
CN101741376A (en) * 2008-11-18 2010-06-16 台湾积体电路制造股份有限公司 Ultra-low voltage level shifting circuit
CN207559971U (en) * 2017-09-26 2018-06-29 格科微电子（上海）有限公司 Level shifting circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113285707A (en) * 2020-02-19 2021-08-20 圣邦微电子（北京）股份有限公司 Voltage level conversion circuit
CN112383298A (en) * 2021-01-18 2021-02-19 灿芯半导体(上海)有限公司 DDR (double data Rate) sending circuit
CN112383298B (en) * 2021-01-18 2021-06-11 灿芯半导体(上海)股份有限公司 DDR (double data Rate) sending circuit

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