CN102751974B

CN102751974B - Output buffer

Info

Publication number: CN102751974B
Application number: CN201110102900.3A
Authority: CN
Inventors: 李建锡; 辛东橙
Original assignee: Novatek Microelectronics Corp
Current assignee: Novatek Microelectronics Corp
Priority date: 2011-04-22
Filing date: 2011-04-22
Publication date: 2015-02-25
Anticipated expiration: 2031-04-22
Also published as: CN102751974A

Abstract

The invention discloses an output buffer which comprises a level conversion module, a preceding-stage drive module and an output module, wherein the level conversion module is used for generating a first logic signal with a first level range and a second logic signal with a second level range according to an input signal; the preceding-stage drive module is composed of a low-voltage transistor and is used for generating a first control signal and a second control signal according to the first logic signal and the second logic signal; the output module is used for generating an output signal with a third level range according to the first control signal and the second control signal; and the size of either of the first level range and the second level range is smaller than the size of the third level range.

Description

Output buffer

Technical field

The present invention relates to a kind of output buffer, espespecially a kind of output buffer with low output jitter.

Background technology

Please refer to Fig. 1, Fig. 1 is the schematic diagram of known technology one output buffer 10.Output buffer 10 can be applicable to the purposes that need output voltage signal to IC outside usually, for example be applied to system single chip (System-on-a-chip, SoC) on, output signal to be sent to the signal drive circuit needed for the memory devices such as such as DRAM (Dynamic Random Access Memory) (Dynamic Random Access Memory, DRAM).As shown in Figure 1, output buffer 10 usually include one in logic and the accurate converting unit in (AND) lock 100, position 102,104, fore-stage driver unit 110,112, output transistor array 120_1 ~ 120_M, 122_1 ~ 122_M in parallel and resistance 130.And lock 100 to an enable signal OE and a data-signal DATA actuating logic " and " operation, with according to enable signal OE, determine whether communicated data signal DATA, as an input signal IN.The value of input signal IN is between an initial high voltage VDD and an initial low-voltage VSS.

The input and output transformation curve that the accurate converting unit 102,104 in position is preset according to one, changing also amplification input signal IN is respectively one first logical signal LG1 and one second logical signal LG2, the codomain of the first logical signal LG1 and the second logical signal LG2 is all between one first high voltage VDDQ and one first low-voltage VSSQ, and VDDQ-VSSQ > VDD-VSS.Fore-stage driver unit 110,112 by the inverter be connected in series or step by step amplifier form, respectively according to the first logical signal LG1 and the second logical signal LG2, produce one first control signal CON1 and one second control signal CON2.Finally, output transistor array 120_1 ~ 120_M, 122_1 ~ 122_M in parallel is respectively according to the first control signal CON1 and the second control signal CON2, and generated value is between an output signal OUT of the first high voltage VDDQ and the first low-voltage VSSQ.Resistance 130 is used to provide static discharge (electrostaticdischarge, ESD) guard delay.

Output transistor array 120_1 ~ 120_M, 122_1 ~ 122_M is directly in the face of the output stage of load, is be made up of high-voltage complementary metal-oxide semiconductor (MOS) (ComplementaryMetal-Oxide-Semiconductor, CMOS) transistor.In addition, fore-stage driver unit 110,112 is similarly high-voltage complementary metal oxide semiconductor component.But, the operating voltage that high-speed interface circuit uses constantly declines, such as interface is 1.8v to second generation double data rate SDRAM (Double-Data-Rate Two Synchronous Dynamic Random Access Memory, DDR2SDRAM), third generation double data rate SDRAM (DDR3SDRAM) interface is down to 1.5v, low-voltage third generation double data rate SDRAM (DDR3L SDRAM) interface is more down to 1.35v.Under the trend that this output stage power supply supply voltage position standard reduces, the drive current of high voltage transistor by with weaken, and then produce larger signal delay time.Meanwhile, low operating voltage is also unfavorable for resisting the noise produced when operating from line lock relatively.As a result, output signal OUT and can produce larger output jitter.

Therefore, how under the continuous downward trend of operating voltage, one of stable effort target having become industry maintaining output buffer output signal.

Summary of the invention

Therefore, namely main purpose of the present invention is to provide a kind of output buffer with low output jitter.

The present invention discloses a kind of output buffer, includes an accurate modular converter, is used for producing one first logical signal with first accurate scope and one second logical signal with the accurate scope of second according to an input signal; One prime driver module, it is made up of low voltage transistor, for according to this first logical signal and this second logical signal, and produces one first control signal in a first node and produces one second control signal in a Section Point; And an output module, be coupled to this first node and this Section Point of this prime driver module, for producing an output signal with the 3rd accurate scope in an output according to this first control signal and this second control signal, wherein the size of this first accurate scope and the central each of the accurate scope of this second is the size being less than the 3rd accurate scope.

Coordinate detailed description and claims of following accompanying drawing, embodiment at this, by address after other object of the present invention and advantage be specified in.

Accompanying drawing explanation

Fig. 1 is the configuration diagram of known technology one output buffer.

Fig. 2 is the configuration diagram of the output buffer according to an embodiment.

Wherein, description of reference numerals is as follows:

VDD initial high voltage

VSS initial low-voltage

VDDQ first high voltage

VSSQ first low-voltage

VSS_SINK second low-voltage

DATA data-signal

OE enable signal

IN input signal

LG1 first logical signal

LG2 second logical signal

CON1 first control signal

CON2 second control signal

OUT outputs signal

VSWP [1:N] first programming signal

VSWN [1:N] second programming signal

N1 first node

N2 Section Point

N_out output

10,20 output buffers

100 and lock

110,112 fore-stage driver unit

120_1 ~ 120_M, 122_1 ~ 122_M output transistor array

200 logical blocks

210 accurate modular converters

102,104,212 accurate converting units

214 delay cells

220 prime driver modules

222 first low pressure fore-stage driver unit

224 second low pressure fore-stage driver unit

230 output modules

232_1 first exports block

232_2 second exports block

232_p first type low voltage transistor

232_n Second-Type low voltage transistor

234 high pressure programmed cell

234_1 first Programmed control block

234_2 second Programmed control block

234_p1 ~ 234_pN first type high voltage transistor

234_n1 ~ 234_nN Second-Type high voltage transistor

130,240 resistance

Embodiment

In the output buffer that following examples provide, the stable of output signal can be maintained under the continuous downward trend of operating voltage.Following examples are considered at CMOS (Complementary Metal Oxide Semiconductor) (Complementary Metal-Oxide-Semiconductor, CMOS) in processing procedure, the effect that the drive current of low-voltag transistor weakens by the reduction of supply voltage position standard is less obvious, is therefore changed by the members in the face of load not direct in the middle of output buffer and realizes with low pressure components.As a result, output buffer is better for the resistivity of power supply noise, and can reach less output signal time of delay, and then more easily realizes the output signal of low jitter.

Please refer to Fig. 2, Fig. 2 is the configuration diagram of the output buffer 20 according to an embodiment.Output buffer 20 includes a logical block 200, accurate modular converter 210, prime driver module 220, output module 230 and a resistance 240.In addition, similar with the known technology of Fig. 1, the input signal IN being positioned at input side has the accurate scope of an initial bit, and it is equally between an initial high voltage VDD and an initial low-voltage VSS.The output signal OUT being positioned at an output n_out then has the 3rd accurate scope, and it is equally between one first high voltage VDDQ and one first low-voltage VSSQ.But compared to the output buffer 10 shown in Fig. 1, output buffer 20 has several significant differences, comprising: the members directly in the middle of the prime driver module 220 and output module 230 of load changes and realizes with low pressure components.In addition, in order to coordinate above-mentioned low-pressure structure, the accurate conversion range in position of the accurate modular converter in position 210 and structure are also revised to some extent.Structure and the operation of each assembly in output buffer 20 are below more specifically described.

Logical block 200 is preferably one and (AND) lock, be used for an enable signal OE and a data-signal DATA actuating logic " and " operation, with according to enable signal OE, determine whether communicated data signal DATA, as an input signal IN.

The accurate modular converter 210 in position is used for producing the one first logical signal LG1 with one first accurate scope and the one second logical signal LG2 with the accurate scope of a second according to input signal IN.One specific characteristic of the accurate modular converter 210 in position is, low pressure components can be adopted implement in order to the prime driver module 220 at rear can be allowed, the accurate modular converter 210 in position does not need amplification input signal IN, that is its accurate conversion range can be arranged to compared with the accurate conversion range in the position of known technology be little.

Specifically, first logical signal LG1 and the second logical signal LG2 is all converted to the accurate scope in large position of the supply voltage of output module 230 by the accurate modular converter 210 in position known technology no longer as shown in Figure 1, that is the 3rd accurate scope (VDDQ ~ VSSQ), but less first the accurate scope of the scope that is converted to and the accurate scope of second.In other words, the size of the size of first accurate scope of the first logical signal LG1 and the accurate scope of second of the second logical signal LG2 is all less than the size of the 3rd the accurate scope outputing signal OUT.

In addition, with known technology unlike, the large I of first accurate scope of the first logical signal LG1 and the central each of the accurate scope of second (VDD ~ VSS) of the second logical signal LG2 is no longer arranged to the accurate scope of the initial bit being greater than input signal IN (VDD ~ VSS), but changes the size being arranged to and being less than or equal in fact the accurate scope of initial bit (VDD ~ VSS) into.Preferably, the accurate modular converter in position 210 can continue to use the accurate scope of (LG2) initial bit or the accurate scope of translation (LG1) initial bit, can drive the low pressure components of prime driver module 220.More careful, first the accurate scope obtained after conversion then can be arranged between one first high voltage VDDQ and one second low-voltage VSS_SINK.Wherein the first high voltage VDDQ and the second low-voltage VSS_SINK must meet the condition of (VDDQ-VSS_SINK≤VDD-VSS), for example first accurate scope is the accurate scope of initial bit of translation, that is VSS_SINK is set as equaling VDDQ-(VDD-VSS).In addition, the accurate scope of second then can be set as different from first accurate scope, such as can be set as the accurate scope of initial bit continuing to use (namely equaling in fact) input signal IN, is also between initial high voltage VDD and initial low-voltage VSS.

Fig. 2 also shows an example thin portion framework of the accurate modular converter in position 210, and it can be used to realize the above-mentioned accurate conversion range in preferably position.As shown in Figure 2, the accurate modular converter in position 210 includes an accurate converting unit 212 and a delay cell 214.The accurate converting unit 212 in position is used for input signal IN being carried out position standard conversion and producing the first logical signal LG1 with first accurate scope, wherein first accurate scope can arrange between the first high voltage VDDQ and the second low-voltage VSS_SINK, wherein the condition of (VDDQ-VSS_SINK≤VDD-VSS) must meet, such as is VSS_SINK=VDDQ-(VDD-VSS).In addition, delay cell 214 is used for delay input signal IN, and to produce the second logical signal LG2 with the accurate scope of second, wherein the accurate scope of second can be arranged between initial high voltage VDD and initial low-voltage VSS.

Prime driver module 220 can by the inverter be connected in series or step by step amplifier form.One specific characteristic of prime driver module 220 is, its known technology not as Fig. 1 adopts high voltage transistor to implement, and changes with low voltage transistor composition, therefore has less operating voltage range.Prime driver module 220 for foundation the first logical signal LG1 and the second logical signal LG2, and produces one first control signal CON1 in a first node n1 and produces one second control signal CON2 in a Section Point n2.In the specific embodiment shown in Fig. 2, more show an example thin portion structure of prime driver module 220, wherein prime driver module 220 can include one first low pressure fore-stage driver unit 222 and one second low pressure fore-stage driver unit 224.First low pressure fore-stage driver unit 222, for according to the first logical signal LG1, exports the first high voltage VDDQ or the second low-voltage VSS_SINK to first node n1, as the first control signal CON1.Second low pressure fore-stage driver unit 224, for according to the second logical signal LG2, exports initial high voltage VDD or initial low-voltage VSS to Section Point n2, as the second control signal CON2.

Output module 230 is for producing the output signal OUT with the 3rd accurate scope (VDDQ ~ VSSQ) according to the first control signal CON1 and the second control signal CON2 in output n_out.Resistance 240 is used to provide static discharge (electrostatic discharge, ESD) guard delay.In the specific embodiment shown in Fig. 2, a more example thin portion structure of display translation module 230, wherein output module 230 includes a low pressure output unit and a high pressure programmed cell 234.The former, due to not directly in the face of load, therefore can be made up of low voltage transistor; Latter, because of directly in the face of load, is therefore made up of high voltage transistor.

Low pressure output unit includes one first and exports block 232_1 and one second output block 232_2, be made up of one first type low voltage transistor (such as being a P-type crystal pipe) 232_p and Second-Type low voltage transistor (such as being N-type transistor) 232_n respectively, for receiving the control of the first control signal CON1 and the second control signal CON2, to determine whether the first high voltage VDDQ is passed to output n_out, and determine whether the first low-voltage VSSQ is passed to output n_out.

In addition, high pressure programmed cell 234 includes one first Programmed control block 234_1 and one second Programmed control block 234_2, be made up of one or more first type high voltage transistor 234_p1 ~ 234_pN and one or more Second-Type high voltage transistor 234_n1 ~ 234_nN respectively, it is coupled between low pressure output unit and output n_out, for receiving the control of one first programming signal VSWP [1:N] and one second programming signal VSWN [1:N], to determine between the first type low voltage transistor 232_p and output n_out whether conducting, and to determine between Second-Type low voltage transistor 232_n and output n_out whether conducting.By controlling the conducting number in high voltage transistor 234_p1 ~ 234_pN, 234_n1 ~ 234_nN, first programming signal VSWP [1:N] and the second programming signal VSWN [1:N] can control an output impedance of output buffer 20, and then the position controlling output signal OUT is accurate.

It is noted that, in this embodiment, in the middle of output buffer 20, to only have the high pressure programmed cell 234 in the face of load to realize with high potential assembly, and prime driver module 220 and all changing with low pressure output unit realizes with low pressure components.Because the high pressure programmed cell 234 directly in the face of load realizes with high potential assembly, therefore, it is possible to prevent output stage from being punctured (punch-through), or can avoid different application outputing signal OUT position standard changes the integrity problem caused.In addition, because prime driver module 220 and all changing with low pressure output unit realizes with low pressure components, therefore output buffer 20 is better for the resistivity of power supply noise, reaches the time of delay of less output signal OUT, and then comparatively easily realizes the demand of output signal OUT low jitter.

In addition, it should be noted that, bridge circuit (232_1,234_1) or lower bridge circuit (232_1,234_1) conducting are only gone up in running due to output module 230 the same time, and therefore the first control signal CON1 and the second control signal CON2 must keep contrary phase place.For this reason, output buffer 20 preferably also can be set up a coupling capacitance 250 and be coupled between first node n1 and Section Point n2, in order to the handover operation of synchronous first control signal CON1 and the second control signal CON2, and then improve the work period of output signal OUT.

In known technology, the fore-stage driver unit 110,112 of output buffer 10 and output transistor array 120_1 ~ 120_M, 122_1 ~ 122_M all realize with high potential assembly, cause when operating voltage declines, output signal OUT shake is comparatively large or cannot the problem of normal start because the conducting threshold voltage (Vth) of high potential assembly is higher.In comparison, the high pressure programmed cell 234 in the face of load is only had to realize with high potential assembly in the middle of output buffer 20, and prime driver module 220 and low pressure output unit all change with low pressure components realization, and then reach when low operating voltage, the object of stable output signal OUT.

In sum, the present invention, in the driving stage of output buffer and output stage, replaces high potential assembly with low pressure components, with under the trend reduced at operating voltage, maintains stablizing of output signal.

The foregoing is only the preferred embodiments of the present invention, all equalizations done according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. an output buffer, is characterized in that, includes:

An accurate modular converter, is used for producing one first logical signal with first accurate scope and one second logical signal with the accurate scope of second according to an input signal, comprises:

An accurate converting unit, is coupled to a logical block, is used for this input signal being carried out position standard conversion and producing this first logical signal with this first accurate scope; And

One delay cell, is coupled to this logical block, is used for postponing this input signal to produce this second logical signal with the accurate scope of this second;

One prime driver module, it is made up of low voltage transistor, for according to this first logical signal and this second logical signal, and produces one first control signal in a first node and produces one second control signal in a Section Point; And

One output module, is coupled to this first node and this Section Point of this prime driver module, for producing an output signal with the 3rd accurate scope in an output according to this first control signal and this second control signal, comprising:

One low pressure output unit, it is made up of low voltage transistor, for receiving the control of this first control signal and this second control signal, to determine whether one first high voltage source is coupled to this output, and determine whether one first low-voltage source is coupled to this output; And

One high pressure programmed cell, it is made up of high voltage transistor, and be coupled to this low pressure output unit in one the 3rd node and one the 4th node, for receiving the control of one first programming signal and one second programming signal, to determine between the 3rd node and this output whether conducting, and to determine between the 4th node and this output whether conducting;

Wherein the size of this first accurate scope and the central each of the accurate scope of this second is the size being less than the 3rd accurate scope.

2. output buffer as claimed in claim 1, it is characterized in that, this first accurate scope is different from the accurate scope of this second.

3. output buffer as claimed in claim 1, is characterized in that, the size in the middle of this first and second accurate scope each is the size of the accurate scope of an initial bit being less than or equal in fact this input signal.

4. output buffer as claimed in claim 1, it is characterized in that, the accurate scope of one initial bit of this input signal is between an initial high voltage and an initial low-voltage, 3rd accurate scope is between one first high voltage and one first low-voltage, this first accurate scope is between this first high voltage and one second low-voltage different from this first low-voltage, and the accurate scope of this second is between this initial high voltage and this initial low-voltage.

5. output buffer as claimed in claim 4, it is characterized in that, this second low-voltage equals in fact this first high voltage-(this initial high voltage-this initial low-voltage).

6. output buffer as claimed in claim 1, it is characterized in that, this low pressure output unit comprises:

One first exports block, comprises one first type low voltage transistor coupled in parallel in this first high voltage source

And between one the 3rd node, for receiving the control of this first control signal with conducting or cut-out; And

One second exports block, comprises a Second-Type low voltage transistor coupled in parallel between this first low-voltage source and one the 4th node, for receiving this second control signal with conducting or cut-out.

7. output buffer as claimed in claim 1, it is characterized in that, this high pressure programmed cell comprises:

One first Programmed control block, comprises at least one first type high voltage transistor coupled in parallel between the 3rd node and this output, for receiving the control of this first programming signal with conducting or cut-out; And

One second Programmed control block, comprises at least one Second-Type high voltage transistor coupled in parallel between the 4th node and this output, for receiving the control of this second programming signal with conducting or cut-out.

8. output buffer as claimed in claim 1, it is characterized in that, this prime driver module includes:

One first low pressure fore-stage driver unit, is coupled between one first high voltage source and one second low-voltage source, for according to this first logical signal to produce this first control signal in this first node; And

One second low pressure fore-stage driver unit, is coupled between an initial high voltage source and an initial low-voltage source, for according to this second logical signal to produce this second control signal in this Section Point.

9. output buffer as claimed in claim 1, is characterized in that, also comprise a coupling capacitance, be coupled between this first node and this Section Point, for increasing the work period of this output signal.