CN103903645A - Static random storage unit employing radiation hardening design - Google Patents
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Abstract
The invention discloses a static random storage unit employing a radiation hardening design. The static random storage unit comprises a first access N-channel metal oxide semiconductor (NMOS) transistor, a first differential serial voltage switch logic unit, a second differential serial voltage switch logic unit and a second access NMOS transistor, which are sequentially connected, wherein the first differential serial voltage switch logic unit and the second differential serial voltage switch logic unit form a cross-coupled latch; the latch is connected between positive VCC and power ground GND; the grid end of the first access NMOS transistor is connected with a word line; the source end or the drain end is connected with a bit line; the grid end of the second access NMOS transistor is connected with the word line; the source end or the drain end of the second access NMOS transistor is reversely connected with the bit line. Consumption of area caused by the radiation hardening design can be effectively reduced when the radiation resistance of the static random storage unit is improved. Compared with the static random storage unit with a DICE structure employing the radiation hardening design, the static random storage unit employing radiation hardening design disclosed by the invention has the advantage that the area is reduced by 17%.
Description
Technical field
The present invention relates to technical field of integrated circuits, relate more specifically to a kind of static ram cell of radiation harden design.
Background technology
According to data storage method, semiconductor memory is divided into dynamic RAM (DRAM), nonvolatile memory and static RAM (SRAM).SRAM can realize operating speed fast in a kind of mode simple and low-power consumption, and compared with DRAM, SRAM does not need periodic refresh canned data, so Design and manufacture is relatively easy, thereby SRAM is used widely in field of data storage.But in the application such as space, aerospace, the radiation effect that a large amount of high energy particle, cosmic rayss etc. that exist produce, as single-particle inversion etc., will cause the loss of static ram cell data in SRAM, destroy thus the normal work of SRAM, and along with constantly reducing of integration characteristic circuit size, radiation effect increases the weight of for the impact of static ram cell thereupon.For the specific demand of the application such as meeting spatial, aerospace, the radiation harden design of static ram cell is become to particularly important.
Known traditional static ram cell is 6 pipe units, as shown in Figure 1, 6 pipe units comprise: first, the second driving N MOS transistor 310, 320, first, the second load PMOS transistor 315, 325, wherein the first driving N MOS transistor 310 and the first load PMOS transistor 315 form the first phase inverter 31, the second driving N MOS transistor 320 and the second load PMOS transistor 325 form the second phase inverter 32, the first phase inverter output is connected with the second phase inverter input, the second phase inverter output is connected with the first phase inverter input, form thus cross-linked latch, this latch is connected between positive voltage (VCC) and power supply ground (GND), two access nmos pass transistors 340,341, its drain electrode is connected with the first phase inverter output 312, the second phase inverter output 322 respectively, and its source electrode is connected with bit line 301, bit line anti-302 respectively, and its grid is all connected with word line 330.In the time that 6 pipe units are carried out to read/write operation, word line 330 is converted to high voltage, two pairs of paratope line read/write data.
Under radiation environment, due to the impact of radiation effect, especially, in the time that single event occurs, if when arbitrary memory node generation transient state of latch is overturn, all may cause the upset of latch data, thereby there is error in data in 6 pipe units of traditional structure.
As shown in Figure 2, Fig. 2 is the static ram cell of the radiation harden design of DICE structure, it comprises: 4 PMOS pipes, the different phase inverter of NMOS pipe input, the first phase inverter 41, the second phase inverter 42, the 3rd phase inverter 43, the 4th phase inverter 44, the first phase inverter comprises a driving N metal-oxide-semiconductor 410 and a load PMOS pipe 415, the second phase inverter comprises a driving N metal-oxide-semiconductor 420 and a load PMOS pipe 425, the 3rd phase inverter comprises a driving N metal-oxide-semiconductor 430 and a load PMOS pipe 435, the 4th phase inverter comprises a driving N metal-oxide-semiconductor 440 and a load PMOS pipe 445, and these 4 anti-phase outputs 412, 413, 414, 415 press shown in Fig. 2, manage with the PMOS of corresponding phase inverter respectively, the input of NMOS pipe is connected, form thus one group of latch that comprises 4 memory nodes, 4 access nmos pass transistors 440,441,442,443, its drain electrode is connected with the first phase inverter output 412, the second phase inverter output 413 respectively, the 3rd phase inverter output 414, the 4th phase inverter output 415 are connected, its source electrode respectively, bit line 401 anti-402 with bit line 401, bit line, bit line anti-402 is connected, and its grid is all connected with word line 430.Compared with traditional 6 pipe units, it is by increasing the latch point of one group of (2) redundancy, form the redundancy latch of 4 nodes, and then strengthen the stability of this storage unit, thereby show good anti-radiation performance, but its area is 2 times of traditional six pipe units, and this will restrict the scale of storer greatly.
Summary of the invention
(1) technical matters that will solve
In view of this, fundamental purpose of the present invention is to provide a kind of static ram cell of radiation harden design, in improving static ram cell anti-radiation performance, effectively reduces the consumption of the area that radiation harden design brings.
(2) technical scheme
For achieving the above object, the invention provides a kind of static ram cell of radiation harden design, this static ram cell comprises the first access nmos pass transistor 103, the first differential series voltage switch logical block 1, the second differential series voltage switch logical block 2 and the second access nmos pass transistor 203 that connect successively, wherein: this first differential series voltage switch logical block 1 forms cross-linked latch with this second differential series voltage switch logical block 2, this latch is connected between positive voltage VCC and power supply ground GND; The grid end of this first access nmos pass transistor 103 is connected with word line 102, and source or drain terminal are connected with bit line 101; The grid end of this second access nmos pass transistor 203 is connected with word line 102, and source or drain terminal are connected with bit line anti-201.
In such scheme, described the first differential series voltage switch logical block 1 comprises the first input PMOS transistor 104, the second input PMOS transistor 106, the first load nmos pass transistor 105 and the second load nmos pass transistor 107, wherein: source or the drain terminal of the first input PMOS transistor 104 are connected with source or the drain terminal of the first load nmos pass transistor 105, form the first output terminal out10 of the first differential series voltage switch logical block 1; Source or the drain terminal of the second input PMOS transistor 106 are connected with source or the drain terminal of the second load nmos pass transistor 107, form the second output terminal out11 of the first differential series voltage switch logical block 1; The grid end of the first input PMOS transistor 104 is the first input end in10 of the first differential series voltage switch logical block 1; The grid end of the second input PMOS transistor 106 is the second input end in11 of the first differential series voltage switch logical block 1.
In such scheme, the second output terminal out11 of the grid termination first differential series voltage switch logical block 1 of described the first load nmos pass transistor 105, the first output terminal out10 of the grid termination first differential series voltage switch logical block 1 of described the second load nmos pass transistor 107.
In such scheme, described one second differential series voltage switch logical block 2 comprises the 3rd input PMOS transistor 204, the 4th input PMOS transistor 206, the 3rd load nmos pass transistor 205 and the 4th load nmos pass transistor 207, wherein: source or the drain terminal of the 3rd input PMOS transistor 204 are connected with source or the drain terminal of the 3rd load nmos pass transistor 205, form the first output out20 of the second differential series voltage switch logical block 2; Source or the drain terminal of the 4th input PMOS transistor 206 are connected with source or the drain terminal of the 4th load nmos pass transistor 207, form the second output out21 of the second differential series voltage switch logical block 2; The grid end of the 3rd input PMOS transistor 204 is the first input in20 of the second differential series voltage switch logical block 2; The grid end of the 4th input PMOS transistor 206 is the second input in21 of the second differential series voltage switch logical block 2.
In such scheme, the second output out21 of the grid termination second differential series voltage switch logical block 2 of described the 3rd load nmos pass transistor 205, the first output out20 of the grid termination second differential series voltage switch logical block 2 of described the 4th load nmos pass transistor 207.
In such scheme, the first input end in10 of described the first differential series voltage switch logical block 1 is connected with the first output out20 of described the second differential series voltage switch logical block 2, the second input end in11 of described the first differential series voltage switch logical block 1 is connected with the second output out21 of described the second differential series voltage switch logical block 2, the first output terminal out10 of described the first differential series voltage switch logical block 1 is connected with the first input in20 of described the second differential series voltage switch logical block 2, the second output terminal out11 of described the first differential series voltage switch logical block 1 is connected with the second input in21 of described the second differential series voltage switch logical block 2, described the first differential series voltage switch logical block 1 forms cross-linked latch with described the second differential series voltage switch logical block 2 thus.
In such scheme, the drain terminal of described the first access nmos pass transistor 103 or source are connected with the first input end in10 of described the first differential series voltage switch logical block 1, and the drain terminal of described the second access nmos pass transistor 203 or source are connected with the second input end in11 of described the first differential series voltage switch logical block 1.
In such scheme, in this static ram cell and the array that comprising multiple these static ram cells, described word line 102 is vertical with power ground.
In such scheme, in this static ram cell and the array that comprising multiple these static ram cells, described rheme line 101 is parallel with power ground.
In such scheme, in this static ram cell and the array that comprising multiple these static ram cells, described rheme line anti-201 is parallel with power ground.
(3) beneficial effect
Can find out from technique scheme, the static ram cell of radiation harden design provided by the invention, adopt 2 differential series voltage switch logical blocks to form latch structure, there are 2 extra redundant storage nodes compared with traditional 6 pipe units, i.e. 4 memory nodes (out10, out11, out20, out21) altogether, wherein any one memory node is all subject to the control of other 2 memory nodes.Therefore,, in the time that wherein upset occurs any one memory node in single event, the probability that upset occurs other memory nodes reduces greatly, can effectively improve the anti-radiation performance of this static ram cell.Moreover, the static ram cell of radiation harden design provided by the invention, compared with the static ram cell of the radiation harden design of DICE structure, its area has also reduced 17%, can effectively reduce the consumption of the area that radiation harden design brings.
Brief description of the drawings
At length foregoing invention content is described by accompanying drawing image, so that the features and advantages of the invention become more clear, these accompanying drawings comprise:
Shown in Fig. 1 is the circuit diagram of traditional six pipe static ram cells;
Shown in Fig. 2 is the circuit diagram of the static ram cell of the radiation harden design based on DICE structure;
Shown in Fig. 3 is the circuit diagram according to the static ram cell of the radiation harden design of the embodiment of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, hereinafter, by with reference to accompanying drawing, one embodiment of the present of invention will be described in detail.But the present invention can be implemented in many different forms, should not be defined in example given here, this example to provide in order to make the disclosure be thoroughly with complete, and pass on all sidedly thought of the present invention to those skilled in the art.
As shown in Figure 3, shown in Fig. 3 is the circuit diagram according to the static ram cell of the radiation harden design of the embodiment of the present invention, this static ram cell comprises the first access nmos pass transistor 103, the first differential series voltage switch logical block 1, the second differential series voltage switch logical block 2 and the second access nmos pass transistor 203 that connect successively, wherein:
The first differential series voltage switch logical block 1, it comprises one first input PMOS transistor 104, one second input PMOS transistor 106, one first load nmos pass transistor 105, one second load nmos pass transistors 107; Source or the drain terminal of the first input PMOS transistor 104 are connected with source or the drain terminal of the first load nmos pass transistor 105, form the first output terminal out10 of the first differential series voltage switch logical block 1; Source or the drain terminal of the second input PMOS transistor 106 are connected with source or the drain terminal of the second load nmos pass transistor 107, form the second output terminal out11 of the first differential series voltage switch logical block 1; The grid end of the first input PMOS transistor 104 is the first input end in10 of the first differential series voltage switch logical block 1; The grid end of the second input PMOS transistor 106 is the second input end in11 of the first differential series voltage switch logical block 1; The second output terminal out11 of the grid termination first differential series voltage switch logical block 1 of the first load nmos pass transistor 105; The first output terminal out10 of the grid termination first differential series voltage switch logical block 1 of the second load nmos pass transistor 107.
Source or drain terminal at above-mentioned the first input PMOS transistor 104 are connected with source or the drain terminal of the first load nmos pass transistor 105, while forming the first output terminal out10 of the first differential series voltage switch logical block 1, both can be that first source of input PMOS transistor 104 and source or the drain terminal of the first load nmos pass transistor 105 are connected, can be also that first drain terminal of input PMOS transistor 104 and source or the drain terminal of the first load nmos pass transistor 105 are connected.Equally, source or drain terminal at the second input PMOS transistor 106 are connected with source or the drain terminal of the second load nmos pass transistor 107, while forming the second output terminal out11 of the first differential series voltage switch logical block 1, both can be that second source of input PMOS transistor 106 and source or the drain terminal of the second load nmos pass transistor 107 are connected, can be also that second drain terminal of input PMOS transistor 106 and source or the drain terminal of the second load nmos pass transistor 107 are connected.
The second differential series voltage switch logical block 2, it comprises one the 3rd input PMOS transistor 204, the 4th input PMOS transistor 206, the 3rd load nmos pass transistor 205, the 4th load nmos pass transistor 207; Source or the drain terminal of the 3rd input PMOS transistor 204 are connected with source or the drain terminal of the 3rd load nmos pass transistor 205, form the first output out20 of the second differential series voltage switch logical block 2; Source or the drain terminal of the 4th input PMOS transistor 206 are connected with source or the drain terminal of the 4th load nmos pass transistor 207, form the second output out21 of the second differential series voltage switch logical block 2; The grid end of the 3rd input PMOS transistor 204 is the first input in20 of the second differential series voltage switch logical block 2; The grid end of the 4th input PMOS transistor 206 is the second input in21 of the second differential series voltage switch logical block 2; The second output out21 of the grid termination second differential series voltage switch logical block 2 of the 3rd load nmos pass transistor 205; The first output out20 of the grid termination second differential series voltage switch logical block 2 of the 4th load nmos pass transistor 207.
Source or drain terminal at above-mentioned the 3rd input PMOS transistor 204 are connected with source or the drain terminal of the 3rd load nmos pass transistor 205, while forming the first output out20 of the second differential series voltage switch logical block 2, the source that can be both the 3rd input PMOS transistor 204 is connected with source or the drain terminal of the 3rd load nmos pass transistor 205, can be also that the drain terminal of the 3rd input PMOS transistor 204 is connected with source or the drain terminal of the 3rd load nmos pass transistor 205.Equally, source or drain terminal at the 4th input PMOS transistor 206 are connected with source or the drain terminal of the 4th load nmos pass transistor 207, while forming the second output out21 of the second differential series voltage switch logical block 2, the source that can be both the 4th input PMOS transistor 206 is connected with source or the drain terminal of the 4th load nmos pass transistor 207, can be also that the drain terminal of the 4th input PMOS transistor 206 is connected with source or the drain terminal of the 4th load nmos pass transistor 207.
The first input end in10 of the first differential series voltage switch logical block 1 is connected with the first output out20 of the second differential series voltage switch logical block 2; The second input end in11 of the first differential series voltage switch logical block 1 is connected with the second output out21 of the second differential series voltage switch logical block 2; The first output terminal out10 of the first differential series voltage switch logical block 1 is connected with the first input in20 of the second differential series voltage switch logical block 2; The second output terminal out11 of the first differential series voltage switch logical block 1 is connected with the second input in21 of the second differential series voltage switch logical block 2; The first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 form cross-linked latch thus, and this latch is connected between positive voltage and power supply ground.
The first access nmos pass transistor 103, its drain terminal or source are connected with the first input end in10 of the first differential series voltage switch logical block 1, and its grid end is connected with word line 102, and its source or drain terminal are connected with bit line 101.
The second access nmos pass transistor 203, its drain terminal or source are connected with the second input end in11 of the first differential series voltage switch logical block 1, and its grid end is connected with word line 102, and its source or drain terminal are connected with bit line anti-201.
In this static ram cell and the array that comprising multiple these static ram cells, described word line 102 is vertical with power ground, and described rheme line 101 is parallel with power ground, and described rheme line anti-201 is parallel with power ground.
In the time this static ram cell being carried out to one writing operation, bit line 101 is high level, bit line anti-201 is low level, word line 102 is high level, the first access nmos pass transistor 103 and the second access nmos pass transistor 203 are all opened, low level on high level on bit line 101 and bit line anti-201 will be linked into respectively on the first input end in10 and the second input end in11 of the first differential series voltage switch logical block 1, the first output terminal out10 and the second output terminal out11 of the first differential series voltage switch logical block 1 will obtain respectively low level and high level, according to the annexation of static ram cell, the first input in20 of the second differential series voltage switch logical block 2 and the second input in21 will obtain respectively low level and high level, the first output out20 of the second differential series voltage switch logical block 2 and the second output out21 will obtain respectively high level and low level, and respectively with first input end in10 and the second input end in11 of the first differential series voltage switch logical block 1 on high level and low level coupling, static ram cell completes one writing operation, in the time that word line 102 is low level, the first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 form latch structure, keep " 1 " data that write.
In the time this static ram cell being write to " 0 " operation, bit line 101 is low level, bit line anti-201 is high level, word line 102 is high level, the first access nmos pass transistor 103 and the second access nmos pass transistor 203 are all opened, high level on low level on bit line 101 and bit line anti-201 is by upper to the first input end in10 and the second input end in11 that are linked into respectively the first differential series voltage switch logical block 1, and the first output out10 and the second output terminal out11 of the first differential series voltage switch logical block 1 will obtain respectively high level and low level; According to the annexation of static ram cell, the first input in20 of the second differential series voltage switch logical block 2 and the second input in21 will obtain respectively high level and low level, the first output out20 of the second differential series voltage switch logical block 2 and the second output out21 will obtain respectively low level and high level, and respectively with first input end in10 and the second input end in11 of the first differential series voltage switch logical block 1 on low level and high level coupling, static ram cell completes writes " 0 " operation; In the time that word line 102 is low level, the first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 form latch structure, keep " 0 " data that write.
If when this static ram cell latch data is " 1 ", first of the second output terminal out11 of the first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 the output out20 is high level, the second output out21 of the first output terminal out10 of the first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 is low level, while considering, in radiation environment, single event occurs, suppose that high energy particle acts on the first output out20 of the second differential series voltage switch logical block 2, the first output out20 is low level by high level upset, because the low level on high level and the second output terminal out11 on the first output terminal out10 of the first differential series voltage switch logical block 1 is not all overturn, it will act in the second differential series voltage switch logical block 2, the the first output out20 that recovers the second differential series voltage switch logical block 2 is high level.
The static ram cell of this radiation harden design of realizing based on 0.2 μ m technique, it is carried out to the emulation testing of HSPICE single-particle, can obtain its single-particle inversion threshold value is 160MeV.cm2/mg, and the static ram cell single-particle inversion threshold value of radiation harden design based on DICE structure is only 9MeV.cm
2/ mg, six traditional pipe static ram cell single-particle inversion threshold values are only 3MeV.cm
2/ mg.Therefore, the static ram cell of radiation harden design provided by the invention, in improve static ram cell anti-radiation performance, has also effectively reduced the consumption of the area that radiation harden design brings.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. the static ram cell of a radiation harden design, it is characterized in that, this static ram cell comprises the first access nmos pass transistor (103), the first differential series voltage switch logical block (1), the second differential series voltage switch logical block (2) and the second access nmos pass transistor (203) that connect successively, wherein:
This first differential series voltage switch logical block (1) forms cross-linked latch with this second differential series voltage switch logical block (2), and this latch is connected between positive voltage VCC and power supply ground GND;
The grid end of this first access nmos pass transistor (103) is connected with word line (102), and source or drain terminal are connected with bit line (101);
The grid end of this second access nmos pass transistor (203) is connected with word line (102), and source or drain terminal are connected with bit line anti-(201).
2. the static ram cell of radiation harden design according to claim 1, it is characterized in that, described the first differential series voltage switch logical block (1) comprises the first input PMOS transistor (104), the second input PMOS transistor (106), the first load nmos pass transistor (105) and the second load nmos pass transistor (107), wherein:
Source or the drain terminal of the first input PMOS transistor (104) are connected with source or the drain terminal of the first load nmos pass transistor (105), form first output terminal (out10) of the first differential series voltage switch logical block;
Source or the drain terminal of the second input PMOS transistor (106) are connected with source or the drain terminal of the second load nmos pass transistor (107), form second output terminal (out11) of the first differential series voltage switch logical block;
The grid end of the first input PMOS transistor (104) is the first input end (in10) of the first differential series voltage switch logical block;
The grid end of the second input PMOS transistor (106) is second input end (in11) of the first differential series voltage switch logical block.
3. the static ram cell of radiation harden design according to claim 2, it is characterized in that, second output terminal (out11) of the grid termination first differential series voltage switch logical block of described the first load nmos pass transistor (105), first output terminal (out10) of the grid termination first differential series voltage switch logical block of described the second load nmos pass transistor (107).
4. the static ram cell of radiation harden design according to claim 1, it is characterized in that, described one second differential series voltage switch logical block (2) comprises the 3rd input PMOS transistor (204), the 4th input PMOS transistor (206), the 3rd load nmos pass transistor (205) and the 4th load nmos pass transistor (207), wherein:
Source or the drain terminal of the 3rd input PMOS transistor (204) are connected with source or the drain terminal of the 3rd load nmos pass transistor (205), form the first output (out20) of the second differential series voltage switch logical block;
Source or the drain terminal of the 4th input PMOS transistor (206) are connected with source or the drain terminal of the 4th load nmos pass transistor (207), form the second output (out21) of the second differential series voltage switch logical block;
The grid end of the 3rd input PMOS transistor (204) is the first input (in20) of the second differential series voltage switch logical block;
The grid end of the 4th input PMOS transistor (206) is the second input (in21) of the second differential series voltage switch logical block.
5. the static ram cell of radiation harden design according to claim 4, it is characterized in that, the second output (out21) of the grid termination second differential series voltage switch logical block of described the 3rd load nmos pass transistor (205), the first output (out20) of the grid termination second differential series voltage switch logical block of described the 4th load nmos pass transistor (207).
6. according to the static ram cell of the radiation harden design described in claim 2 or 4, it is characterized in that, the first input end (in10) of described the first differential series voltage switch logical block is connected with the first output (out20) of described the second differential series voltage switch logical block, second input end (in11) of described the first differential series voltage switch logical block is connected with the second output (out21) of described the second differential series voltage switch logical block, first output terminal (out10) of described the first differential series voltage switch logical block is connected with the first input (in20) of described the second differential series voltage switch logical block, second output terminal (out11) of described the first differential series voltage switch logical block is connected with the second input (in21) of described the second differential series voltage switch logical block, described the first differential series voltage switch logical block (1) forms cross-linked latch with described the second differential series voltage switch logical block (2) thus.
7. the static ram cell of radiation harden design according to claim 6, it is characterized in that, the drain terminal of described the first access nmos pass transistor (103) or source are connected with the first input end (in10) of described the first differential series voltage switch logical block, and the drain terminal of described the second access nmos pass transistor (203) or source are connected with second input end (in11) of described the first differential series voltage switch logical block.
8. the static ram cell of radiation harden design according to claim 1, it is characterized in that, in this static ram cell and the array that comprising multiple these static ram cells, described word line (102) is vertical with power ground.
9. the static ram cell of radiation harden design according to claim 1, it is characterized in that, in this static ram cell and the array that comprising multiple these static ram cells, described rheme line (101) is parallel with power ground.
10. the static ram cell of radiation harden design according to claim 1, it is characterized in that, in this static ram cell and the array that comprising multiple these static ram cells, described rheme line anti-(201) is parallel with power ground.
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| US10262724B2 (en) | 2015-03-27 | 2019-04-16 | Institute Of Automation Chinese Academy Of Sciences | Memory cell of static random access memory based on DICE structure |
| CN105049031A (en) * | 2015-07-29 | 2015-11-11 | 西北工业大学 | DICE structure latch unit resisting single-particle irradiation effect |
| CN105897223A (en) * | 2016-03-31 | 2016-08-24 | 中国人民解放军国防科学技术大学 | D trigger resistant to single event upset |
| CN105897223B (en) * | 2016-03-31 | 2018-10-12 | 中国人民解放军国防科学技术大学 | A kind of primary particle inversion resistant d type flip flop |
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| CN108183706B (en) * | 2018-01-29 | 2021-09-07 | 中国人民解放军国防科技大学 | Single event upset resistant register file storage array write unit |
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