CN203276858U - SRAM (Static Random Access Memory) - Google Patents
SRAM (Static Random Access Memory) Download PDFInfo
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- CN203276858U CN203276858U CN 201320326372 CN201320326372U CN203276858U CN 203276858 U CN203276858 U CN 203276858U CN 201320326372 CN201320326372 CN 201320326372 CN 201320326372 U CN201320326372 U CN 201320326372U CN 203276858 U CN203276858 U CN 203276858U
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- 230000003068 static effect Effects 0.000 title abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 153
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 2
- 230000005055 memory storage Effects 0.000 description 1
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Abstract
The utility model discloses an SRAM (Static Random Access Memory). The SRAM comprises a first N type MOS (Metal Oxide Semiconductor) transistor, a second N type MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth N type MOS transistor, and a first to fourth P type MOS transistors, wherein the first N type MOS transistor and the first P type MOS transistor form a first phase inverter, and the second N type MOS transistor and the second P type MOS transistor form a second phase inverter; the fifth N type MOS transistor and the first N type MOS transistor are connected in parallel, and the sixth N type MOS transistor and the second N type MOS transistor are connected in parallel; the first P type MOS transistor and the third P type MOS transistor are connected in parallel, and the second P type MOS transistor and the fourth P type MOS transistor are connected in parallel; grid electrodes of the third MOS transistor and the fourth MOS transistor are connected with a word line by signal, the grid electrode of the third MOS transistor is connected with a bit line by signal, a leakage electrode of the fourth MOS transistor is connected with a bit line without signals, a source electrode of the third MOS transistor is connected with a first memory node, a source electrode of the fourth MOS transistor is connected with a second memory node. With the SRAM, the divider resistance can be reduced, and further the static noise margin can be promoted.
Description
Technical field
The utility model relates to technical field of integrated circuits, particularly a kind of SRAM storer.
Background technology
SRAM (Static RAM), i.e. static RAM, it is comprised of transistor.For transistor, connect and to represent 1, disconnect expression 0, and state can remain to received one change signal till.These transistors do not need to refresh, but external noise may cause information to damage, and its main cause is that static noise margin is too low low, cause the stability of SRAM storer to reduce.
Fig. 1 is the SRAM storage unit of 6T (i.e. 6 transistors) structure of prior art.Wherein M5, M6 represent two P type metal-oxide-semiconductors, and M1, M2, M3, M4 represent four N-type metal-oxide-semiconductors.Wherein, WL represents word-line signal, and BL represents bit line signal, and BLB represents the non-signal of bit line, and Q and NQ represent memory node.Metal-oxide-semiconductor M3 is connected grid and is connected with word-line signal WL with M4, drain electrode is connected with bit line signal BL, the non-signal NBL of bit line respectively, and source electrode is connected with memory node Q, QB respectively.Metal-oxide-semiconductor M5 and M1, M6 and M2 consist of respectively phase inverter, in order to the data of latch stores node Q and QB.
When read operation, two bit lines BL and BLB charge to respectively Vdd/2, if left side memory node Q storing value is 1, the right memory node QB storing value is 0, when read operation, WL=1, M5 conducting, due to 1 of Q storage, the M2 transistor gate voltage is in opening always, and BLB read 0 o'clock that stores in QB, and itself is charged to high level, therefore M2 and M4 form a discharge path, and QB voltage rises from 0.If QB voltage rises to a certain degree, can make the M1 conducting, thus drop-down Q point current potential, if static noise margin is too low, the risk that whole sram memory storage data all can be overturn.Thus, when read operation, certain level between the node voltage of storage 0 rises to 0 to Vdd/2, this depends on the conducting resistance between M2 and M4.Equally, the problem that also exists storage node voltage to change when reading " 1 "; In Fig. 1, BL and BLB were precharged to Vdd/2 before reading the storage data, if Q=1, QB=0, M3 and M5 form path, and Q point current potential is in certain level between Vdd/2 and Vdd, and this depends on the size of M3 and M5 conducting resistance.
The utility model content
Technical problem to be solved in the utility model is to provide a kind of SRAM storer that can promote static noise margin, thereby promotes the stability of SRAM storer.
For solving the problems of the technologies described above, the utility model provides a kind of SRAM storer, comprising: the first N-type metal-oxide-semiconductor, the second N-type metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th N-type metal-oxide-semiconductor, the 6th N-type metal-oxide-semiconductor, first to fourth P type metal-oxide-semiconductor;
Described the 3rd metal-oxide-semiconductor is consistent with described the 4th metal-oxide-semiconductor structure;
The grid of described the 3rd metal-oxide-semiconductor and described the 4th metal-oxide-semiconductor all is connected with word-line signal, the drain electrode of described the 3rd metal-oxide-semiconductor is connected with bit line signal, the drain electrode of described the 4th metal-oxide-semiconductor is connected with the non-signal of bit line, the source electrode of described the 3rd metal-oxide-semiconductor is connected with the first memory node, and the source electrode of described the 4th metal-oxide-semiconductor is connected with the second memory node; The grid of the grid of the grid of a described P type metal-oxide-semiconductor, described the 3rd P type metal-oxide-semiconductor, the grid of described the first N-type metal-oxide-semiconductor and described the 5th N-type metal-oxide-semiconductor is connected with described the second memory node; The drain electrode of the drain electrode of a described P type metal-oxide-semiconductor and described the 3rd P type metal-oxide-semiconductor is connected with the first memory node, and the source electrode of the source electrode of a described P type metal-oxide-semiconductor and described the 3rd P type metal-oxide-semiconductor is connected with high power level; The drain electrode of the drain electrode of described the first N-type metal-oxide-semiconductor and described the 5th N-type metal-oxide-semiconductor is connected with the first memory node, and the source electrode of the source electrode of described the first N-type metal-oxide-semiconductor and described the 5th N-type metal-oxide-semiconductor is connected with low power level; The grid of the grid of the grid of described the 2nd P type metal-oxide-semiconductor, described the 4th P type metal-oxide-semiconductor, the grid of described the second N-type metal-oxide-semiconductor and described the 6th N-type metal-oxide-semiconductor is connected with described the first memory node; The drain electrode of the drain electrode of described the 2nd P type metal-oxide-semiconductor and described the 4th P type metal-oxide-semiconductor is connected with the second memory node, and the source electrode of the source electrode of described the 2nd P type metal-oxide-semiconductor and described the 4th P type metal-oxide-semiconductor is connected with high power level; The drain electrode of the drain electrode of described the second N-type metal-oxide-semiconductor and described the 6th N-type metal-oxide-semiconductor is connected with the second memory node, and the source electrode of the source electrode of described the second N-type metal-oxide-semiconductor and described the 6th N-type metal-oxide-semiconductor is connected with low power level.
Further, described the 3rd metal-oxide-semiconductor and described the 4th metal-oxide-semiconductor are the N-type metal-oxide-semiconductor.
Further, described the 3rd metal-oxide-semiconductor and described the 4th metal-oxide-semiconductor are P type metal-oxide-semiconductor.
The SRAM storer that the utility model provides is in parallel with four metal-oxide-semiconductors that consist of two phase inverters one to one respectively by having increased by four metal-oxide-semiconductors compared to existing 6T type SRAM storer, thereby reduction divider resistance, the static noise margin of read operation is got a promotion, strengthened the stability of SRAM storer.
Description of drawings
Fig. 1 is the structural drawing of the 6T structure SRAM storer of prior art;
The structural drawing of the SRAM storer that Fig. 2 provides for the utility model embodiment;
Wherein, M1-the first N-type metal-oxide-semiconductor, M2-the second N-type metal-oxide-semiconductor, M3-the 3rd metal-oxide-semiconductor, M4-the 4th metal-oxide-semiconductor, M5-the 5th N-type metal-oxide-semiconductor, M6-the 6th N-type metal-oxide-semiconductor, M7-the one P type metal-oxide-semiconductor, M8-the 2nd P type metal-oxide-semiconductor, M9-the 3rd P type metal-oxide-semiconductor, M10-the 4th P type metal-oxide-semiconductor.
Embodiment
Referring to Fig. 2, the SRAM storer of a kind of 10T structure that the utility model embodiment provides comprises: the first N-type metal-oxide-semiconductor, the second N-type metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th N-type metal-oxide-semiconductor, the 6th N-type metal-oxide-semiconductor, first to fourth P type metal-oxide-semiconductor;
The 3rd metal-oxide-semiconductor is consistent with the 4th metal-oxide-semiconductor structure;
The grid of the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor all is connected with word-line signal, the drain electrode of the 3rd metal-oxide-semiconductor is connected with bit line signal, the drain electrode of the 4th metal-oxide-semiconductor is connected with the non-signal of bit line, and the source electrode of the 3rd metal-oxide-semiconductor is connected with the first memory node, and the source electrode of the 4th metal-oxide-semiconductor is connected with the second memory node; The grid of the grid of the grid of the one P type metal-oxide-semiconductor, the 3rd P type metal-oxide-semiconductor, the grid of the first N-type metal-oxide-semiconductor and the 5th N-type metal-oxide-semiconductor is connected with the second memory node; The drain electrode of the drain electrode of the one P type metal-oxide-semiconductor and the 3rd P type metal-oxide-semiconductor is connected with the first memory node, and the source electrode of the source electrode of a P type metal-oxide-semiconductor and the 3rd P type metal-oxide-semiconductor is connected with high power level; The drain electrode of the drain electrode of the first N-type metal-oxide-semiconductor and the 5th N-type metal-oxide-semiconductor is connected with the first memory node, and the source electrode of the source electrode of the first N-type metal-oxide-semiconductor and the 5th N-type metal-oxide-semiconductor is connected with low power level; The grid of the grid of the grid of the 2nd P type metal-oxide-semiconductor, the 4th P type metal-oxide-semiconductor, the grid of the second N-type metal-oxide-semiconductor and the 6th N-type metal-oxide-semiconductor is connected with the first memory node; The drain electrode of the drain electrode of the 2nd P type metal-oxide-semiconductor and the 4th P type metal-oxide-semiconductor is connected with the second memory node, and the source electrode of the source electrode of the 2nd P type metal-oxide-semiconductor and the 4th P type metal-oxide-semiconductor is connected with high power level; The drain electrode of the drain electrode of the second N-type metal-oxide-semiconductor and the 6th N-type metal-oxide-semiconductor is connected with the second memory node, and the source electrode of the source electrode of the second N-type metal-oxide-semiconductor and the 6th N-type metal-oxide-semiconductor is connected with low power level.
The 10T structure SRAM reading out data " 1 " and " 0 " that now provide by the present embodiment are described the stage of reading.
Before reading, the non-signal BLB of bit line signal BL and bit line first is precharged to Vdd, virtual earth Virtual_Gnd=0 and Virtual_Vdd=1.If the first memory point Q=1, the second memory point QB=0 connects with transfer tube M4 after M2 and M8 parallel connection, forms the path that reads QB=0; On the other hand, be composed in series with transfer tube M3 the path that reads Q=1 after M5 and M9 parallel connection.With respect to six traditional pipe units, the divider resistance after M2 and M8 parallel connection is less with respect to the conducting resistance of M2, and the current potential of QB is relatively lower, more is conducive to make QB to remain on 0; In like manner, the divider resistance after M5 is in parallel with M9 reduces, and is less with respect to the conducting resistance of M5, thereby makes Q=1 closer to Vdd.Thereby promoted the static noise margin of read operation, made the SRAM storer more stable.
In whole circuit, write with hold mode under, Virtual_Gnd=1, Virtual_Vdd=0, so only conducting when read operation of M7 to M10, thereby reduce power consumption and leakage current.
The metal-oxide-semiconductor of storer is built type selecting can be flexible and changeable, and further, the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4 can be P type metal-oxide-semiconductors; It can also be the N-type metal-oxide-semiconductor.
The SRAM storer of the 10T structure that the utility model provides is compared to existing 6T type SRAM storer, in parallel with four metal-oxide-semiconductors that consist of two phase inverters one to one respectively by having increased by four metal-oxide-semiconductors, thereby reduction divider resistance, the static noise margin of read operation is got a promotion, strengthened the stability of SRAM storer.
It should be noted last that, above embodiment is only unrestricted in order to the technical solution of the utility model to be described, although with reference to example, the utility model is had been described in detail, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement the technical solution of the utility model, and not breaking away from the spirit and scope of technical solutions of the utility model, it all should be encompassed in the middle of claim scope of the present utility model.
Claims (3)
1. a SRAM storer, is characterized in that, comprising: the first N-type metal-oxide-semiconductor, the second N-type metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th N-type metal-oxide-semiconductor, the 6th N-type metal-oxide-semiconductor, first to fourth P type metal-oxide-semiconductor;
Described the 3rd metal-oxide-semiconductor is consistent with described the 4th metal-oxide-semiconductor structure;
The grid of described the 3rd metal-oxide-semiconductor and described the 4th metal-oxide-semiconductor all is connected with word-line signal, the drain electrode of described the 3rd metal-oxide-semiconductor is connected with bit line signal, the drain electrode of described the 4th metal-oxide-semiconductor is connected with the non-signal of bit line, the source electrode of described the 3rd metal-oxide-semiconductor is connected with the first memory node, and the source electrode of described the 4th metal-oxide-semiconductor is connected with the second memory node; The grid of the grid of the grid of a described P type metal-oxide-semiconductor, described the 3rd P type metal-oxide-semiconductor, the grid of described the first N-type metal-oxide-semiconductor and described the 5th N-type metal-oxide-semiconductor is connected with described the second memory node; The drain electrode of the drain electrode of a described P type metal-oxide-semiconductor and described the 3rd P type metal-oxide-semiconductor is connected with described the first memory node, and the source electrode of the source electrode of a described P type metal-oxide-semiconductor and described the 3rd P type metal-oxide-semiconductor is connected with high power level; The drain electrode of the drain electrode of described the first N-type metal-oxide-semiconductor and described the 5th N-type metal-oxide-semiconductor is connected with described the first memory node, and the source electrode of the source electrode of described the first N-type metal-oxide-semiconductor and described the 5th N-type metal-oxide-semiconductor is connected with low power level; The grid of the grid of the grid of described the 2nd P type metal-oxide-semiconductor, described the 4th P type metal-oxide-semiconductor, the grid of described the second N-type metal-oxide-semiconductor and described the 6th N-type metal-oxide-semiconductor is connected with described the first memory node; The drain electrode of the drain electrode of described the 2nd P type metal-oxide-semiconductor and described the 4th P type metal-oxide-semiconductor is connected with described the second memory node, and the source electrode of the source electrode of described the 2nd P type metal-oxide-semiconductor and described the 4th P type metal-oxide-semiconductor is connected with described high power level; The drain electrode of the drain electrode of described the second N-type metal-oxide-semiconductor and described the 6th N-type metal-oxide-semiconductor is connected with described the second memory node, and the source electrode of the source electrode of described the second N-type metal-oxide-semiconductor and described the 6th N-type metal-oxide-semiconductor is connected with described low power level.
2. SRAM storer as claimed in claim 1, it is characterized in that: described the 3rd metal-oxide-semiconductor and described the 4th metal-oxide-semiconductor are the N-type metal-oxide-semiconductor.
3. SRAM storer as claimed in claim 1, it is characterized in that: described the 3rd metal-oxide-semiconductor and described the 4th metal-oxide-semiconductor are P type metal-oxide-semiconductor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320326372 CN203276858U (en) | 2013-06-06 | 2013-06-06 | SRAM (Static Random Access Memory) |
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| CN 201320326372 CN203276858U (en) | 2013-06-06 | 2013-06-06 | SRAM (Static Random Access Memory) |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956183A (en) * | 2014-04-24 | 2014-07-30 | 中国科学院微电子研究所 | Anti-radiation static random access memory (SRAM) unit |
| CN104464796A (en) * | 2014-12-04 | 2015-03-25 | 中国科学院微电子研究所 | Ten-transistor transient effect resisting SRAM unit |
| CN105225690A (en) * | 2014-05-29 | 2016-01-06 | 展讯通信（上海）有限公司 | SRAM memory cell and storage array |
| CN105336363A (en) * | 2014-05-29 | 2016-02-17 | 展讯通信（上海）有限公司 | SRAM memory cell, storage array and memory |
| CN110047535A (en) * | 2019-03-20 | 2019-07-23 | 上海华虹宏力半导体制造有限公司 | SARM storage unit |
-
2013
- 2013-06-06 CN CN 201320326372 patent/CN203276858U/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956183A (en) * | 2014-04-24 | 2014-07-30 | 中国科学院微电子研究所 | Anti-radiation static random access memory (SRAM) unit |
| CN103956183B (en) * | 2014-04-24 | 2017-01-04 | 中国科学院微电子研究所 | Radioprotective sram cell |
| CN105225690A (en) * | 2014-05-29 | 2016-01-06 | 展讯通信（上海）有限公司 | SRAM memory cell and storage array |
| CN105336363A (en) * | 2014-05-29 | 2016-02-17 | 展讯通信（上海）有限公司 | SRAM memory cell, storage array and memory |
| CN105336363B (en) * | 2014-05-29 | 2018-01-26 | 展讯通信（上海）有限公司 | SRAM memory cell, storage array and memory |
| CN105225690B (en) * | 2014-05-29 | 2018-01-26 | 展讯通信（上海）有限公司 | SRAM memory cell and storage array |
| CN104464796A (en) * | 2014-12-04 | 2015-03-25 | 中国科学院微电子研究所 | Ten-transistor transient effect resisting SRAM unit |
| CN110047535A (en) * | 2019-03-20 | 2019-07-23 | 上海华虹宏力半导体制造有限公司 | SARM storage unit |
| CN110047535B (en) * | 2019-03-20 | 2021-01-22 | 上海华虹宏力半导体制造有限公司 | SRAM memory cell |
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| C14 | Grant of patent or utility model | ||
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| TR01 | Transfer of patent right |
Effective date of registration: 20170714 Address after: 100029 Beijing city Chaoyang District Beitucheng West Road No. 11 building 4 layer Institute of Microelectronics Patentee after: BEIJING ZHONGKE XINWEITE SCIENCE & TECHNOLOGY DEVELOPMENT Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
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Granted publication date: 20131106 |