CN110767251B - 11T TFET SRAM unit circuit structure with low power consumption and high write margin - Google Patents

11T TFET SRAM unit circuit structure with low power consumption and high write margin Download PDF

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CN110767251B
CN110767251B CN201910984510.XA CN201910984510A CN110767251B CN 110767251 B CN110767251 B CN 110767251B CN 201910984510 A CN201910984510 A CN 201910984510A CN 110767251 B CN110767251 B CN 110767251B
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ntfet
transistor
drain
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ntfet transistor
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CN110767251A (en
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李正平
陈朌盼
蔺智挺
彭春雨
吴秀龙
卢文娟
陈军宁
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Anhui University
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Anhui University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Abstract

The invention discloses a 11T TFET SRAM unit circuit structure with low power consumption and high write margin, which comprises nine NTFET transistors and two PTFET transistors, wherein the nine NTFET transistors are sequentially marked as N1-N9, the two PTFET transistors are sequentially marked as P1 and P2, VDD is connected with the drain electrodes of the NTFET transistors N4, and VDD is also electrically connected with the source electrodes of the PTFET transistors P1 and P2; the drain of the PTFET transistor P1 is electrically connected to the drain of the NTFET transistor N1, the source of the NTFET transistor N5, the drain of the NTFET transistor N7, the gate of the PTFET transistor P2, and the gate of the NTFET transistor N2. The circuit structure not only solves the problem that the traditional TFET SRAM unit structure is poor in holding and reading capacity, but also improves the stability of the SRAM unit.

Description

11T TFET SRAM unit circuit structure with low power consumption and high write margin
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an 11T TFET SRAM unit circuit structure with low power consumption and high write margin.
Background
With the continuous progress of the MOS manufacturing process, the device size is also reduced, which promotes the vigorous development and technological progress of the integrated circuit industry. However, as the MOSFET (metal-oxide semiconductor field effect transistor) is used as an important component of digital integrated circuits and analog integrated circuits, the requirements for low-power devices are increasingly stringent due to the fact that the static leakage current and static power consumption of the circuits are increased due to the continuous reduction of the feature size, the gradually increased threshold voltage and the gradual deterioration of the off-state current. Furthermore, the subthreshold swing of a MOSFET is limited by thermoelectric potential at room temperature and theoretically difficult to be lower than 60mv/decade, which means that it is not possible to reduce the static power consumption of a chip built with MOSFET devices by lowering the supply voltage without limit. Also, since a Static Random Access Memory (SRAM) is widely used in high-performance microprocessors, most of the static power consumption of the processor is consumed.
Aiming at the problems that the static power consumption of the MOSFET is gradually worsened and the like, a plurality of solutions are provided at home and abroad, and other problems are brought, so that the static power consumption of the SRAM is still very difficult to further reduce under the sub-threshold working voltage. Under such a development situation, a Tunneling Field Effect Transistor (TFET) (tunneling Field transistor) has a subthreshold swing lower than 60mv/decade due to a band-band tunneling mechanism, and at the same time, a higher switching ratio can be achieved at a low voltage, so that the TFET has a great potential in a low power consumption Field, thereby possibly replacing a MOSFET. However, unidirectional conductivity (unidirectional conductivity) due to the different source-drain doping of the TFET limits the application of the TFET in SRAM. TFET unidirectional conductivity means that at a certain gate voltage, when Vds is less than 0 and Vds is greater than 0, an asymmetric current can be observed across the source and drain of the device, rather than a unidirectional power flow. For the NTFET, when the voltage at the source terminal is higher than that at the drain terminal, a p-i-n forward bias current which is not controlled by the gate always occurs, so that when the NTFET is applied to an SRAM circuit, the NTFET may have a serious influence on the static noise margin, the read noise margin, and the static power consumption. It is important to effectively reduce or avoid p-i-n forward bias current.
Disclosure of Invention
The invention aims to provide a 11T TFET SRAM unit circuit structure with low power consumption and high write margin, which can reduce the static power consumption of a Static Random Access Memory (SRAM) unit and improve the stability of the SRAM unit.
The purpose of the invention is realized by the following technical scheme:
a low power consumption and high write margin 11T TFET SRAM cell circuit structure, the circuit structure includes nine NTFET transistors and two PTFET transistors, the nine NTFET transistors are sequentially marked as N1-N9, the two PTFET transistors are sequentially marked as P1 and P2, wherein:
VDD is connected to the drain of NTFET transistor N4, while VDD is also electrically connected to the source of PTFET transistor P1 and the source of PTFET transistor P2;
a drain of the PTFET transistor P1 electrically connected to a drain of the NTFET transistor N1, a source of the NTFET transistor N5, a drain of the NTFET transistor N7, a gate of the PTFET transistor P2, and a gate of the NTFET transistor N2;
a drain of PTFET transistor P2 electrically connected to a drain of NTFET transistor N2, a gate of PTFET transistor P1, a gate of NTFET transistor N1, and a gate of NTFET transistor N8;
the drain of NTFET transistor N3 is electrically connected to the source of NTFET transistor N1;
the source of NTFET transistor N4 is electrically connected to the drain of NTFET transistor N5;
the source of NTFET transistor N7 is electrically connected to the drain of NTFET transistor N6;
the source of NTFET transistor N9 is electrically connected to the drain of NTFET transistor N8;
the source of the NTFET transistor N3, the source of the NTFET transistor N2, the source of the NTFET transistor N6, and the source of the NTFET transistor N8 are electrically connected to GND;
wherein the circuit structure further comprises:
word line WLA is electrically connected to the gate of NTFET transistor N5 and the gate of NTFET transistor N7, and word line WLB is electrically connected to the gate of NTFET transistor N3;
bit line BL is connected to the gate of NTFET transistor N4, bit line BLB is connected to the gate of NTFET transistor N6;
read word line WR connects the gate of NTFET transistor N9 and read bit line RBL connects the drain of NTFET transistor N9.
According to the technical scheme provided by the invention, the problem that the traditional TFET SRAM unit structure is poor in holding and reading capacity is solved, and the p-i-n forward bias current caused by the unidirectional conductivity of the TFET is avoided, so that the static power consumption of the SRAM unit is greatly improved, and the stability of the SRAM unit is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a general schematic diagram of a 11T TFET SRAM cell circuit structure with low power consumption and high write margin according to an embodiment of the present invention;
FIG. 2 is a data diagram comparing the retention margin of the circuit structure with the retention margins of other cells according to an embodiment of the present invention;
FIG. 3 is a data diagram comparing write margins of a circuit structure with write margins of other cells according to an embodiment of the present invention;
fig. 4 is a data diagram comparing static power consumption of the circuit structure provided by the embodiment of the invention with static power consumption of other units.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The following will describe an embodiment of the present invention in further detail with reference to the accompanying drawings, and as shown in fig. 1, is an overall schematic diagram of a circuit structure of an 11T TFET SRAM cell with low power consumption and high write margin, the circuit structure includes nine NTFET transistors and two PTFET transistors, the nine NTFET transistors are sequentially denoted as N1 to N9, and the two PTFET transistors are sequentially denoted as P1 and P2, where:
VDD is connected to the drain of NTFET transistor N4, while VDD is also electrically connected to the sources of PTFET transistor P1 and PTFET transistor P2;
a drain of the PTFET transistor P1 electrically connected to a drain of the NTFET transistor N1, a source of the NTFET transistor N5, a drain of the NTFET transistor N7, a gate of the PTFET transistor P2, and a gate of the NTFET transistor N2;
a drain of PTFET transistor P2 electrically connected to a drain of NTFET transistor N2, a gate of PTFET transistor P1, a gate of NTFET transistor N1, and a gate of NTFET transistor N8;
the drain of NTFET transistor N3 is electrically connected to the source of NTFET transistor N1;
the source of NTFET transistor N4 is electrically connected to the drain of NTFET transistor N5;
the source of NTFET transistor N7 is electrically connected to the drain of NTFET transistor N6;
the source of NTFET transistor N9 is electrically connected to the drain of NTFET transistor N8;
the sources of the NTFET transistor N3, the NTFET transistor N2, the NTFET transistor N6, and the NTFET transistor N8 are electrically connected to GND.
In addition, referring to fig. 1, the circuit structure further includes:
word line WLA is electrically connected to the gates of NTFET transistor N5 and NTFET transistor N7, and word line WLB is electrically connected to the gate of NTFET transistor N3;
bit line BL is connected to the gate of NTFET transistor N4, bit line BLB is connected to the gate of NTFET transistor N6;
read word line WR connects the gate of NTFET transistor N9 and read bit line RBL connects the drain of NTFET transistor N9.
Based on the above connection relationship, the PTFET transistor P1 and the NTFET transistor N1, the PTFET transistor P2 and the NTFET transistor N2 constitute two cross-coupled inverters, in which:
the source of the NTFET transistor N1 is connected with the drain of the NTFET transistor N3, the NTFET transistor N3 is a write assist transistor, and the gate of the NTFET transistor N3 is connected with a control word line WLB, so that the phenomenon of poor write capability and even write failure caused by the voltage reduction of a Q point of a storage point when the SRAM unit performs write 1 operation is avoided, and meanwhile, the write margin of the SRAM unit during write 1 operation is improved.
The NTFET transistors N8 and N9 form a read-write separation structure which is used as a circuit for reading the SRAM unit, and the read-write separation structure can effectively improve the reading capability of the SRAM unit.
The NTFET transistors N4, N5, N6 and N7 are transmission transistors, and are used for solving the problem of p-i-N forward bias leakage current caused by forward bias voltage appearing in the SRAM due to TFET, wherein:
two NTFET transistors N4 and N5 are connected in series and the source of NTFET transistor N5 is connected to the storage point Q, the drain of NTFET transistor N4 is connected high; the other two NTFET transistors N6 and N7 are connected in series, the drain of the NTFET transistor N7 is connected with the storage point Q, the source of the NTFET transistor N6 is connected with a low level, and the drain voltage of each transmission tube is higher than the source voltage, so that the existence of p-i-N forward bias current can be effectively avoided, and the problem of large p-i-N forward bias leakage current caused by the forward bias voltage of the TFET in the SRAM is solved.
In a specific implementation, the principle of the 11T TFET SRAM cell circuit structure with low power consumption and high write margin is as follows:
(1) in the hold state, WLA and WR are low, BL and BLB are low, RBL is high, and NTFET transistors N4, N5, N6, and N7 are in an off state. WLB is high and NTFET transistor N3 is on, thus putting the latch formed by P1, P2, N1, N2 and N3 in a latched state, improving the retention capability of the cell. Meanwhile, the transmission tube structure used by the invention can effectively avoid the occurrence of forward bias voltage in the structure, thereby effectively solving the problems of p-i-n forward bias current and the like when the TFET is used as an SRAM transmission tube.
(2) In the write operation state: assuming that the cell will write a "1" operation, BL and WLA are set high while WLB is set low; at this time, NTFET transistors N4 and N5 are turned on, NTFET transistor N3 is turned off, the latch state of the latch is broken due to the turning off of NTFET transistor N3, VDD charges the Q point through NTFET transistors N4 and N5, and since BLB is low, NTFET transistor N6 is turned off, NTFET transistors N6 and N7 do not pull down the Q point voltage, so that the Q point voltage is rapidly raised to a high level, and the Q point is inverted and then fed back to the inverter composed of PTFET transistor P2 and NTFET transistor N2 to invert QB, thereby improving the write capability and write margin of the SRAM cell. After the write operation is completed, WLA is set to be low level, WLB is set to be high level, NTFET transistor N3 is opened, the latch restores the latch state, and the stability of the unit is ensured. When the cell writes a '0' operation, the storage point Q point is '1', QB is '0', WLA and BLB are set to high level, WLB keeps the original state '1', transmission tube NTFET transistors N6 and N7 are turned on, the storage point Q is discharged to low level through N6 and N7, and simultaneously, the storage point voltage is also discharged through N3 because the NTFET transistor N3 is turned on, thereby completing the writing of '0'. Since the 11T TFET SRAM cell proposed by the present invention has asymmetry, the cell breaks its latch state when it performs a write "1" operation, so its write "1" capability is stronger than write "0" capability.
(3) In a read operation state: assuming that the data stored at the cell storage point Q is "0", when the cell performs a read operation, RBL is first precharged to a high level, WLA maintains the original state of "0", and WLB maintains the high level of "1", thereby putting the latch composed of the transistors P1, P2, N1, N2, and N3 in a latched state. Setting WR of a read word line where a cell to be read is at a high level, setting the voltage of a point Q to be 0, setting the voltage of a point QB to be 1, so that an NTFET transistor N8 is turned on, meanwhile, setting the WR to be at the high level, setting an NTFET transistor N9 to be in a turned-on state, discharging the voltage of an RBL to a low level through N8 and N9, and detecting the change of the voltage of the RBL by a sensitive amplifier in an SRAM array to realize the reading of the storage data of the SRAM cell.
In order to more clearly show the technical solutions and the technical effects provided by the present invention, the following compares the performance of the unit circuit provided by the embodiment of the present invention with other TFET SRAM units with reference to the accompanying drawings, and the specific contents thereof are as follows:
(1) as shown in fig. 2, the remaining static noise margin (denoted as HSNM) of four TFET SRAM cells is shown, and according to the experimental simulation result, the circuit structure provided by the present invention has a very high remaining margin when the operating voltage is greater than 0.6V. The transfer transistors of the 8T-DP structure and the 8T-TG structure do not eliminate p-i-n forward bias leakage current of the TFET, so that the stability of the storage unit in a holding state is poor.
The circuit structure provided by the invention has asymmetry, and the static noise tolerance is slightly different when noise interference is added at a storage point Q (Pro-11T HSNMQ) and a QB point (Pro-11T HSNMQ) (as shown in figure 2), because when the noise interference is added at the QB point, although the NTFET transistor N3 is in a conducting state, the noise interference still has certain influence on the VTC of an inverter formed by the PTFET transistor P1 and the NTFET transistor N1. The transmission transistor of the circuit structure provided by the invention does not generate forward bias voltage in a holding state, so that the voltage of the storage points Q and QB cannot be raised. Even under the condition of larger operating voltage, the SRAM unit cell structure still has larger holding margin compared with other TFET SRAM unit structures.
(2) The write noise margin (denoted WSNM) of four TFET SRAM cells is shown in fig. 3. The circuit of the unit structure has asymmetry, so the write noise tolerance of the unit structure is measured by adopting a word line write margin method. According to the experimental simulation result, as can be seen from the figure, the circuit structure provided by the invention has a large write margin when writing '1' operation; in the 0 writing operation, if the working voltage is lower than 0.7v, the writing margin is also greatly improved (i.e. the curve represented by the solid triangle and the solid circle). This is because the structure proposed by the present invention adopts a way of breaking the latch when performing the write 1 operation, which improves the write capability without affecting the holding state of other cells. But due to its asymmetry, its write "0" and write "1" margins are different (as shown in fig. 3). Since the 6T-OA structure and the 8T-DP structure have the same circuit structure for performing the write operation, they have the same write margin.
(3) The static power consumption of the four types of cell structures in the retention state is shown in fig. 4. According to experimental simulation results, the circuit structure provided by the invention can effectively avoid the forward bias phenomenon of the TFET transmission tube, so that p-i-n forward bias current does not exist in the transmission transistor. Therefore, as the power supply voltage increases, the static power consumption of the memory cell still does not change much. As shown in fig. 4, compared with the 6T-OA cell structure, the static power consumption of the cell structure proposed by the present invention is reduced by at least 3 orders of magnitude at operating voltages higher than 0.5V, wherein the static power consumption is reduced by at least 5 orders of magnitude at 0.9V.
Because the circuit structure provided by the invention has asymmetric characteristics, the static power consumption is different when the unit keeps 0 or 1. This is because the static leakage current at the Q-point of the high level storage node is discharged by two paths of NTFET transistors N1, N3 and N6, N7 when the cell remains "1". When the cell holds "0", the charge leakage discharge of high level storage point QB discharges to ground through only one path of NTFET transistor N2, so the static power consumption of the cell when holding "1" is greater than the static power consumption of the cell when holding "0".
It is noted that those skilled in the art will recognize that embodiments of the present invention are not described in detail herein.
In summary, the circuit structure according to the embodiment of the invention utilizes the characteristic that the subthreshold value of the TFET can break through the limit of 60mv/dec at room temperature, and compared with the characteristic that the MOSFET has a higher switching ratio, the circuit structure not only solves the problem that the traditional TFET SRAM cell structure has poor holding and reading capabilities, but also eliminates p-i-n positive bias current caused by unidirectional conductivity of the TFET, thereby greatly improving the static power consumption. Under the same working voltage, such as 0.5V to 0.9V, the static power consumption of the TFET SRAM unit is reduced by at least 3 orders of magnitude, and when the working voltage is 0.9V, the holding margin of the TFET SRAM unit is increased by at least 1.8 times, so that the writing margin, the reading margin and the stability of the TFET SRAM unit are improved.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (4)

1. A circuit structure of 11T TFET SRAM unit with low power consumption and high write margin is characterized in that the circuit structure comprises nine NTFET transistors and two PTFET transistors, wherein the nine NTFET transistors are sequentially marked as N1-N9, and the two PTFET transistors are sequentially marked as P1 and P2, wherein:
VDD is connected to the drain of NTFET transistor N4, while VDD is also electrically connected to the source of PTFET transistor P1 and the source of PTFET transistor P2;
a drain of the PTFET transistor P1 electrically connected to a drain of the NTFET transistor N1, a source of the NTFET transistor N5, a drain of the NTFET transistor N7, a gate of the PTFET transistor P2, and a gate of the NTFET transistor N2;
a drain of PTFET transistor P2 electrically connected to a drain of NTFET transistor N2, a gate of PTFET transistor P1, a gate of NTFET transistor N1, and a gate of NTFET transistor N8;
the drain of NTFET transistor N3 is electrically connected to the source of NTFET transistor N1;
the source of NTFET transistor N4 is electrically connected to the drain of NTFET transistor N5;
the source of NTFET transistor N7 is electrically connected to the drain of NTFET transistor N6;
the source of NTFET transistor N9 is electrically connected to the drain of NTFET transistor N8;
the source of the NTFET transistor N3, the source of the NTFET transistor N2, the source of the NTFET transistor N6, and the source of the NTFET transistor N8 are electrically connected to GND;
wherein the circuit structure further comprises:
word line WLA is electrically connected to the gate of NTFET transistor N5 and the gate of NTFET transistor N7, and word line WLB is electrically connected to the gate of NTFET transistor N3;
bit line BL is connected to the gate of NTFET transistor N4, bit line BLB is connected to the gate of NTFET transistor N6;
read word line WR connects the gate of NTFET transistor N9 and read bit line RBL connects the drain of NTFET transistor N9.
2. The low power consumption and high write margin 11T TFET SRAM cell circuit structure of claim 1, wherein the PTFET P1 and NTFET N1, the PTFET P2 and NTFET N2 respectively form two cross-coupled inverters, wherein:
the source of the NTFET transistor N1 is connected with the drain of the NTFET transistor N3, the NTFET transistor N3 is a write assist transistor, and the gate of the NTFET transistor N3 is connected with a control word line WLB, so that the phenomenon of poor write capability and even write failure caused by the voltage reduction of a Q point of a storage point when the SRAM unit performs write 1 operation is avoided, and meanwhile, the write margin of the SRAM unit during write 1 operation is improved.
3. The 11T TFET SRAM cell circuit structure with low power consumption and high write margin as claimed in claim 1, wherein the NTFET transistors N8 and N9 constitute a read/write separation structure for SRAM cell read operation, which effectively improves the read capability of SRAM cell.
4. The 11T TFET SRAM cell circuit structure with low power consumption and high write margin as claimed in claim 1, wherein the NTFET transistors N4, N5, N6 and N7 are pass transistors for solving the p-i-N forward bias leakage current problem of TFET in SRAM due to the forward bias voltage appearing, wherein:
two NTFET transistors N4 and N5 are connected in series and the source of NTFET transistor N5 is connected to the storage point Q, the drain of NTFET transistor N4 is connected high;
the other two NTFET transistors N6 and N7 are connected in series, the drain of the NTFET transistor N7 is connected with the storage point Q, the source of the NTFET transistor N6 is connected with a low level, and the drain voltage of each transmission tube is higher than the source voltage, so that the existence of p-i-N forward bias current can be effectively avoided, and the problem of large p-i-N forward bias leakage current caused by the forward bias voltage of the TFET in the SRAM is solved.
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CN112509621A (en) * 2020-11-30 2021-03-16 安徽大学 MOSFET-TFET mixed 11T SRAM unit circuit
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