CN209312439U - A kind of 12T TFET SRAM cell circuit for writing nargin with super low-power consumption and height - Google Patents
A kind of 12T TFET SRAM cell circuit for writing nargin with super low-power consumption and height Download PDFInfo
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- CN209312439U CN209312439U CN201822069491.1U CN201822069491U CN209312439U CN 209312439 U CN209312439 U CN 209312439U CN 201822069491 U CN201822069491 U CN 201822069491U CN 209312439 U CN209312439 U CN 209312439U
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Abstract
The utility model discloses a kind of with super low-power consumption and the high 12T TFET SRAM cell circuit for writing nargin, it has the characteristics such as smaller subthreshold swing and higher on-off ratio compared to MOSFET using TFET, not only solve the big problem of the quiescent dissipation of conventional MOS FET SRAM cell structure, when under identical operating voltage such as 0.3V to 0.6V, its quiescent dissipation is compared with other TFET SRAM cell structures, its quiescent dissipation at least reduces 4 orders of magnitude, and improve TFET sram cell writes nargin and stability；It eliminates TFET and does the positively biased current leakage occurred when SRAM transfer tube, reduce the quiescent dissipation of unit, improve the stability and write capability of unit.
Description
Technical field
The utility model relates to IC design field more particularly to a kind of super low-power consumptions, the high 12T for writing nargin
TFET SRAM cell circuit.
Background technique
With the development of mobile electronic product, demand of the people to integrated circuit low-power consumption becomes more more and more urgent.In recent years
Come, MOSFET (Metal-Oxide Semiconductor field effect transistor) has become the important of digital integrated electronic circuit and Analogous Integrated Electronic Circuits
Component part.However, some disadvantages of the MOSFET in super low-power consumption circuit make it with the development of integrated circuit technique node
It is difficult to obtain satisfied result.Because with the reduction of MOSFET size, since the short-channel effect of MOSFET causes it in Asia
Closing reduced capability under threshold voltage, so that the static leakage current of circuit and quiescent dissipation increase.In addition, MOSFET is in room temperature
Under subthreshold swing be theoretically difficult to be less than 60mv/decade.In the microprocessor, static random access memory (SRAM)
50% or more of chip occupying area, and consume most of quiescent dissipation of processor.
Although having proposed many methods for reducing the quiescent dissipation of SRAM under subthreshold voltage extensively at present.
However, further decreasing SRAM quiescent dissipation under subthreshold value operating voltage is still very due to the disadvantages mentioned above of MOSFET
It is limited.Compared to MOSFET, TFET (Tunneling Field-Effect Transistor) is due to lower subthreshold
The value amplitude of oscillation and higher on-off ratio make TFET substitution MOSFET have broad prospects.But the unidirectional conduction of TFET
(unidirectional conduction) characteristic limits the application of TFET in sram, especially its biography as SRAM
When defeated pipe.Because SRAM requires transfer tube bidirectionally conductive.When unidirectional transport properties apply reverse-biased and positive bias-voltage to TFET, electricity
It is different to flow transmission characteristic.When applying positive bias-voltage to TFET, it always will appear the forward current not controlled by grid voltage, this makes
TFET when doing SRAM transfer tube, transfer tube may always will appear positively biased leakage current in the hold state, thus increasing circuit
Quiescent dissipation.
As shown in Figure 1, be 6 traditional pipe SRAM cell structures, due to the asymmetry of TFET (AL, AR) structure, so that
There may be three kinds of structures (Fig. 1 right part, arrow therein represent source terminal) when TFET does SRAM transfer tube, i.e., two
TFET transfer tube source electrode, which is external to respectively on bit line BL and BLB (Fig. 1 (a)), is denoted as OA-6T, two TFET transfer tube source electrode difference
It is inside connected to storage point Q and QB upper (Fig. 1 (b)) and two TFET transfer tube source electrodes distinguishes one inscribed to store another external
Bit line (Fig. 1 (c)).There are paper and experiment to show the unidirectional transport properties due to TFET at present, leads to the 6T of traditional structure
TFET sram cell cannot concurrently reach ideal reading and writing and keep function.OA-6T structure has good write capability, still
Reading ability is excessively poor, or even can not carry out read operation.
8T TFET SRAM (the being denoted as DP-8T) structure of read and write abruption mode shown in Fig. 2 and Schmitt- shown in Fig. 3
Although 10T TFET SRAM (being denoted as ST-10T) structure of Trigger structure solves the problems, such as that OA-6T structure reading ability is weak,
But since TFET does SRAM transfer tube generated positively biased leakage current when the states such as keeping, to will cause its quiescent dissipation larger.
Utility model content
It (is denoted as the purpose of the utility model is to provide a kind of with super low-power consumption and the high 12T TFET SRAM for writing nargin
Pro-12T) element circuit, had not only improved the reading and writing and holding capacity of TFET SRAM, but also eliminated TFET and do SRAM transfer tube
When the positively biased current leakage that occurs, reduce the quiescent dissipation of sram cell, improve the stability of sram cell.
The purpose of this utility model is achieved through the following technical solutions:
A kind of 12T TFET SRAM cell circuit for writing nargin with super low-power consumption and height, comprising: eight NTFET crystal
Pipe and four PTFET transistors；Eight NTFET transistors are successively denoted as N1~N8, four PTFET transistors be successively denoted as P1~
P4；Wherein:
The drain electrode of VDD and NTFET transistor N1 is electrically connected, at the same VDD also with PTFET transistor P1 and PTFET transistor
The source electrode of P2 is electrically connected；
The drain electrode of PTFET transistor P1, grid, the NTFET of drain electrode, PTFET transistor P2 with NTFET transistor N3
The grid of transistor N4 and NTFET transistor N8 is electrically connected；
The drain electrode of PTFET transistor P2, the drain electrode and NTFET with PTFET transistor P3 and PTFET transistor P4 are brilliant
The drain electrode of body pipe N4 and NTFET transistor N5 is electrically connected；
The source electrode of PTFET transistor P3, grid, NTFET with the source electrode of PTFET transistor P4, PTFET transistor P1
The grid electrical connection of the source electrode and NTFET transistor N3 of transistor N2；
The source electrode of NTFET transistor N1 is electrically connected with the drain electrode of NTFET transistor N2；
The source electrode of NTFET transistor N5 is electrically connected with the drain electrode of NTFET transistor N6；
The source electrode of NTFET transistor N7 is electrically connected with the drain electrode of NTFET transistor N8；
Source electrode and the GND electricity of NTFET transistor N3, NTFET transistor N4, NTFET transistor N6 and NTFET transistor N8
Connection.
The utility model is using TFET compared to MOSFET it can be seen from above-mentioned technical solution provided by the utility model
With the characteristics such as smaller subthreshold swing and higher on-off ratio, conventional MOS FET SRAM cell structure is not only solved
The big problem of quiescent dissipation, and solve other TFET sram cells since the one-way conduction characteristic of TFET occurs just
The big problem of quiescent dissipation caused by inclined leakage current.When under identical operating voltage such as 0.3V to 0.6V, quiescent dissipation and
Other TFET SRAM cell structures are compared, and quiescent dissipation at least reduces 4 orders of magnitude, and improves TFET SRAM
Unit writes nargin and stability；It eliminates TFET and does the positively biased current leakage occurred when SRAM transfer tube, reduce
The quiescent dissipation of sram cell improves the stability and write capability of unit.
Detailed description of the invention
It, below will be to required in embodiment description in order to illustrate more clearly of the technical solution of the utility model embodiment
The attached drawing used is briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the utility model
Example, for those of ordinary skill in the art, without creative efforts, can also be according to these attached drawings
Obtain other accompanying drawings.
Fig. 1 is three kinds of configurations of traditional 6T SRAM cell circuit schematic diagram and its TFET transfer tube that background technique provides
The structural schematic diagram of mode；
Fig. 2 is the structural schematic diagram for traditional DP-8T element circuit that background technique provides；
Fig. 3 is the structural schematic diagram for traditional ST-10T element circuit that background technique provides；
Fig. 4 is the principle of super low-power consumption provided by the utility model embodiment, the high Pro-12T element circuit for writing nargin
Figure；
Fig. 5 be the utility model embodiment provided by Pro-12T element circuit write nargin and writing for other units is abundant
Degree compares datagram；
Fig. 6 is the holding nargin of Pro-12T element circuit provided by the utility model embodiment and the guarantor of other units
It holds nargin and compares datagram；
Fig. 7 is the quiet of quiescent dissipation and other units of Pro-12T element circuit provided by the utility model embodiment
State power consumption compares datagram.
Specific embodiment
Below with reference to the attached drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out clear
Chu is fully described by, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole realities
Apply example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without making creative work
The every other embodiment obtained, belongs to the protection scope of the utility model.
Basic device used in traditional SRAM memory cell circuit be MOSFET, the utility model proposes Pro-
Basic device used in 12T element circuit is tunneling field-effect transistor (TFET).TFET does SRAM transfer tube in hold mode
When the positively biased leakage current as caused by its positive bias-voltage will increase the quiescent dissipation of SRAM.Simultaneously because the unidirectional conduction of TFET is special
Property makes it unsuitable for doing the transfer tube of SRAM because this will lead to 6 traditional pipe SRAM structures be difficult to obtain simultaneously it is good
Literacy, traditional 6T SRAM require transfer tube to have bidirectionally conductive ability.It is provided by the utility model a kind of with ultralow
Power consumption and the high Pro-12T element circuit for writing nargin, had not only improved the reading and writing and holding capacity of TFET SRAM, but also eliminate
TFET does the positively biased current leakage occurred when SRAM transfer tube, reduces the quiescent dissipation of SRAM unit, improves unit
Stability.
As described in Figure 4, eight NTFET transistors and four PTFET transistors are specifically included that；Eight NTFET transistors
It is successively denoted as N1~N8, four PTFET transistors are successively denoted as P1~P4；Wherein:
PTFET transistor P1 and NTFET transistor N3, PTFET transistor P2 and NTFET transistor N4 constitutes two instead
Phase device；The two phase inverters and PTFET transistor P3 and P4 constitute latch cicuit, PTFET transistor P3 and P4 for writing behaviour
As when interrupt latch structure, can achieve the purpose that when unit carry out write operation when improve unit write capability；NTFET transistor
N7 and N8 constitutes the circuit that read and write abruption is used as read operation part, can be improved the reading ability of sram cell using this structure
And speed；The positive bias-voltage that NTFET transistor N1, N2, N5 and N6 are used to occur when eliminating TFET as SRAM transfer tube causes
The transfer tube structure of positively biased current leakage.
The structure of entire element circuit is as follows:
The drain electrode of VDD and NTFET transistor N1 is electrically connected, at the same VDD also with PTFET transistor P1 and PTFET transistor
The source electrode of P2 is electrically connected；
The drain electrode of PTFET transistor P1, grid, the NTFET of drain electrode, PTFET transistor P2 with NTFET transistor N3
The grid of transistor N4 and NTFET transistor N8 is electrically connected；
The drain electrode of PTFET transistor P2, the drain electrode and NTFET with PTFET transistor P3 and PTFET transistor P4 are brilliant
The drain electrode of body pipe N4 and NTFET transistor N5 is electrically connected；
The source electrode of PTFET transistor P3, grid, NTFET with the source electrode of PTFET transistor P4, PTFET transistor P1
The grid electrical connection of the source electrode and NTFET transistor N3 of transistor N2；
The source electrode of NTFET transistor N1 is electrically connected with the drain electrode of NTFET transistor N2；
The source electrode of NTFET transistor N5 is electrically connected with the drain electrode of NTFET transistor N6；
The source electrode of NTFET transistor N7 is electrically connected with the drain electrode of NTFET transistor N8；
Source electrode and the GND electricity of NTFET transistor N3, NTFET transistor N4, NTFET transistor N6 and NTFET transistor N8
Connection.
In addition, the grid and PTFET transistor P4 of bit line WL and NTFET transistor N1, that is, NTFET transistor N6
Grid electrical connection；The grid of bit line WLA connection NTFET transistor N2 and the grid of PTFET transistor P3；Bit line WLB connection
The grid of NTFET transistor N5；The grid of readout word line WR connection NTFET transistor N7；Sense bit line RBL connection NTFET transistor
The drain electrode of N7.
The super low-power consumption provided by the utility model embodiment, the high Pro-12T element circuit principle for writing nargin are as follows:
In the hold state, WL and WLA and WLB is low level, and NTFET transistor N1, N2, N5 and N6 are in close state, and PTFET is brilliant
Body pipe P3 and P4 are opened.To make the latch being made of P1, P2, N3, N4, P3, P4 be in latch mode, it ensure that unit exists
Stability under hold mode.While transfer tube structure used in the utility model can effectively eliminate TFET and make SRAM transmission
When pipe the problems such as caused positively biased leakage current, because transfer tube NTFET transistor N1, N2, N5, N6 is not in just at this time
Bias-voltage.Write operation: assuming that unit will be write " 0 " operation, WL and WLA are set to high level at this time, while WLB maintains the original state
That is low level；At this point, NTFET transistor N1 and N2 is opened, PTFET transistor P3 and P4 are closed, due to PTFET transistor P3
It is closed with P4 so that the latch mode of latch is interrupted, VDD is charged by NTFET transistor N1 and N2 to Q2 point, so that Q2
It is high level that point voltage, which increases rapidly, causes the phase inverter being made of PTFET transistor P1 and NTFET transistor N3 to overturn and is
" 0 " can feed back to after the overturning of Q point and by the phase inverter that PTFET transistor P2 and NTFET transistor N4 is formed QB be overturn, from
And it greatly improves the write capability of sram cell and writes nargin.After completing write operation, WL, WLA are set to low level, PTFET
Transistor P3, P4 are opened, and two phase inverters restore latch mode, ensure that the stability of unit.When unit carries out one writing operation
When, it is assumed here that Q is " 0 ", and QB is " 1 ", and WL, WLB are set to high level when one writing operates, and WLA maintains the original state " 0 ", transmission
Pipe NTFET transistor N5, N6 are opened, and QB is low level by N5, N6 electric discharge, simultaneously because WLA is low level, so when
PTFET transistor P3 is to open, and Q2 is discharged to low level by PTFET transistor P3 and NTFET transistor N5, N6, so that
The phase inverter overturning of P1, N3 composition is " 1 " to complete one writing operation.Read operation: assuming that the data of unit storage point Q storage
It is first high level by RBL preliminary filling when unit carries out read operation for " 1 ", WL, WLA, WLB maintain the original state 0, by the list that continues
Sense bit line WR where first is set to high level；Since Q point voltage is " 1 ", therefore NTFET transistor N8 is opened, simultaneously because WR is
High level, therefore NTFET transistor N7 is also at open state, RBL is discharged to low level by N7, N8, the spirit in SRAM array
Quick amplifier detects that the reading to sram cell storing data is realized in the variation of RBL level.
In order to more clearly from show technical solution provided by the utility model and generated technical effect, below
In conjunction with Fig. 1 to Fig. 7, by the performance of Pro-12T element circuit provided by the utility model embodiment, with other TFET SRAM
Unit compares；Its particular content is as follows:
(1) as shown in figure 5, illustrating the comparison of the write-in noise margin of four kinds of TFET sram cells.Write noise margin
(being denoted as WSNM) obtains from VTC curve.According to Simulation results, it can be seen from the figure that Pr0- provided by the utility model
12T element circuit (i.e. curve representated by open circles) writes nargin with bigger than other several cellular constructions.This is because
The structure that the utility model is proposed is when carrying out write operation, by the way of breaking latch, improves write capability, together
When do not influence the hold modes of other units.Due to the circuit structure for being used to carry out write operation part of OA-6T structure and DP-8T
It is identical, therefore they are having the same writes nargin.
(2) as shown in fig. 6, illustrating the holding static noise margin (being denoted as HSNM) of four kinds of TFET sram cells.Root
According to Simulation results, Pro-12T element circuit provided by the utility model has very strong holding stability.Work as driving voltage
When greater than 0.6V, the holding static noise margin of OA-6T unit can be gradually reduced.This is because two transmission transistor is just
Very big to biased leakage currents, this has seriously affected the stability of OA-6T structure.DP-8T structure and ST-10T structure have with
OA-6T identical problem, i.e., its transmission transistor due to leaking electricity there are forward bias leakage current and under big operating voltage
Stream is very big, to seriously affect the stability of storage unit in the hold state.Because of Pro- provided by the utility model
The access transistor of 12T element circuit is not in forward bias current leakage in the hold state, therefore will not cause to store
The voltage fluctuation of point Q and QB, so even if compared to other units still there is biggish holding to make an uproar under big voltage operation conditions
Acoustic capacitance limit.
(3) as shown in fig. 7, Fig. 7 illustrates the quiescent dissipation of the four seed type units in hold mode.It is imitative according to experiment
With the rising of operating voltage known to true result, since in the hold state, the forward bias voltage of access transistor gradually increases
Add, therefore the quiescent dissipation of the quiescent dissipation of sram cell unit in the case where not eliminating forward bias voltage is in the order of magnitude
Increase, such as OA-6T, DP-8T and ST-10T.However, Pro-12T element circuit provided by the utility model eliminates TFET forward direction
Phenomenon is biased, and does not have positively biased leakage current in transfer tube transistor, therefore, with the increase of driving voltage, even if in 0.9V
When, the quiescent dissipation of storage unit will not increase too much.Compared with OA-6T unit, cellular construction proposed in this paper is in 0.3V
Quiescent dissipation at least reduces 4 orders of magnitude under operating voltage, and quiescent dissipation at least reduces by 6 quantity under 0.6V operating voltage
Grade.
Since Pro-12T element circuit provided by the utility model has asymmetrical characteristic, when unit keeps " 0 " or keeps
Quiescent dissipation is different when " 1 ".This is because QB is " 1 ", the static leakage current of QB under the hold mode that unit is maintained at " 0 "
There are two charge leakage discharge paths for tool.One charge leakage discharge path passes through NTFET transistor N4 to ground, another path
Pass through NTFET transistor N5 and N6 to ground.When unit keeps " 1 ", QB is " 0 ", and the charge leakage electric discharge of high level node Q is only
Pass through the paths of NTFET transistor N3 to ground.Therefore quiescent dissipation of the unit in holding " 0 " state is being kept than unit
Quiescent dissipation when one state is big.
The preferable specific embodiment of the above, only the utility model, but the protection scope of the utility model is not
It is confined to this, anyone skilled in the art can readily occur in the technical scope that the utility model discloses
Change or replacement, should be covered within the scope of the utility model.Therefore, the protection scope of the utility model should
Subject to the scope of protection of the claims.
Claims (2)
1. a kind of with super low-power consumption and the high 12T TFET SRAM cell circuit for writing nargin characterized by comprising eight
NTFET transistor and four PTFET transistors；Eight NTFET transistors are successively denoted as N1~N8, four PTFET transistors according to
It is secondary to be denoted as P1~P4；Wherein:
The drain electrode of VDD and NTFET transistor N1 is electrically connected, while VDD is also with PTFET transistor P1 and PTFET transistor P2's
Source electrode electrical connection；
The drain electrode of PTFET transistor P1, grid, the NTFET transistor of drain electrode, PTFET transistor P2 with NTFET transistor N3
The grid of N4 and NTFET transistor N8 is electrically connected；
The drain electrode of PTFET transistor P2, drain electrode and NTFET transistor with PTFET transistor P3 and PTFET transistor P4
The drain electrode of N4 and NTFET transistor N5 is electrically connected；
The source electrode of PTFET transistor P3, with the source electrode of PTFET transistor P4, the grid of PTFET transistor P1, NTFET transistor
The grid electrical connection of the source electrode and NTFET transistor N3 of N2；
The source electrode of NTFET transistor N1 is electrically connected with the drain electrode of NTFET transistor N2；
The source electrode of NTFET transistor N5 is electrically connected with the drain electrode of NTFET transistor N6；
The source electrode of NTFET transistor N7 is electrically connected with the drain electrode of NTFET transistor N8；
The source electrode and GND of NTFET transistor N3, NTFET transistor N4, NTFET transistor N6 and NTFET transistor N8 is electrically connected
It connects.
2. a kind of 12T TFET SRAM cell circuit that nargin is write with super low-power consumption and height according to claim 1,
It is characterized in that, the grid electricity of the grid and PTFET transistor P4 of bit line WL and NTFET transistor N1, that is, NTFET transistor N6
Connection；The grid of bit line WLA connection NTFET transistor N2 and the grid of PTFET transistor P3；Bit line WLB connection NTFET is brilliant
The grid of body pipe N5；The grid of readout word line WR connection NTFET transistor N7；The leakage of sense bit line RBL connection NTFET transistor N7
Pole.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822069491.1U CN209312439U (en) | 2018-12-10 | 2018-12-10 | A kind of 12T TFET SRAM cell circuit for writing nargin with super low-power consumption and height |
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|---|---|---|---|
| CN201822069491.1U CN209312439U (en) | 2018-12-10 | 2018-12-10 | A kind of 12T TFET SRAM cell circuit for writing nargin with super low-power consumption and height |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109658960A (en) * | 2018-12-10 | 2019-04-19 | 安徽大学 | A kind of 12T TFET SRAM cell circuit for writing nargin with super low-power consumption and height |
| CN110675905A (en) * | 2019-08-29 | 2020-01-10 | 安徽大学 | 12T TFET SRAM unit circuit structure with high stability |
-
2018
- 2018-12-10 CN CN201822069491.1U patent/CN209312439U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109658960A (en) * | 2018-12-10 | 2019-04-19 | 安徽大学 | A kind of 12T TFET SRAM cell circuit for writing nargin with super low-power consumption and height |
| CN109658960B (en) * | 2018-12-10 | 2024-03-15 | 安徽大学 | 12T TFET SRAM cell circuit with ultralow power consumption and high write margin |
| CN110675905A (en) * | 2019-08-29 | 2020-01-10 | 安徽大学 | 12T TFET SRAM unit circuit structure with high stability |
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