CN110379449B - 10T TFET and MOSFET device hybrid SRAM unit circuit with high write margin - Google Patents

10T TFET and MOSFET device hybrid SRAM unit circuit with high write margin Download PDF

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CN110379449B
CN110379449B CN201910599805.5A CN201910599805A CN110379449B CN 110379449 B CN110379449 B CN 110379449B CN 201910599805 A CN201910599805 A CN 201910599805A CN 110379449 B CN110379449 B CN 110379449B
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transistor
ntfet
tfet
transistors
nmosfet
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CN110379449A (en
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卢文娟
欧阳春
董兰志
彭春雨
吴秀龙
蔺智挺
陈军宁
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Anhui University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

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Abstract

The invention discloses a 10T TFET and MOSFET device hybrid SRAM unit circuit with high write margin, which adopts a read-write separation mode in the whole structure, adopts a TFET device in the main body of the unit circuit, and adopts a TFET device and MOSFET device combination mode in a transmission pipe part, thereby overcoming the defect of weak transmission capability of stacked TFET and avoiding the P-I-N positive bias current problem when the TFET device is used as an SRAM unit transmission pipe. The writing capability of the unit is improved, and the static power consumption of the unit is reduced.

Description

10T TFET and MOSFET device hybrid SRAM unit circuit with high write margin
Technical Field
The invention relates to the field of integrated circuit design, in particular to a 10T TFET and MOSFET device hybrid SRAM unit circuit with high write margin.
Background
With the development of mobile electronic products, the demand for low power consumption of integrated circuits is becoming more and more urgent. In recent years, MOSFETs (metal-oxide semiconductor field effect transistors) have become an important component of digital integrated circuits and analog integrated circuits. However, as the integrated circuit technology node is developed, the size of the MOSFET is gradually reduced, and the turn-off capability of the MOSFET at the sub-threshold voltage is weakened due to the short channel effect, so that the static leakage current and the static power consumption of the circuit are increased. In microprocessors, Static Random Access Memory (SRAM) occupies more than 50% of the chip area and consumes most of the static power consumption of the processor. The static power consumption of the microprocessor can be reduced by reducing the working voltage of the microprocessor. However, the sub-threshold swing of a MOSFET at room temperature is theoretically difficult to be less than 60mv/decade, making circuits based on MOSFET devices difficult to adapt to operate at ultra-low voltages.
Although many methods for reducing the static power consumption of the SRAM at the subthreshold voltage have been widely proposed at present. However, due to the above-mentioned drawbacks of MOSFETs, further reduction of SRAM static power consumption at sub-threshold operating voltages remains quite limited. Compared with the MOSFET, the TFET (Tunneling Field-Effect Transistor) has a wide prospect for replacing the MOSFET due to the lower subthreshold swing and the higher switching ratio. TFETs have a smaller off-current and a larger on-current at low voltages than MOSFETs due to the tunneling conduction principle. And the subthreshold swing can be smaller than the limit pole of the subthreshold swing of the MOSFET (metal oxide semiconductor field effect transistor) by 60mV/dec, and the minimum value can reach 10mV/dec or even lower, so that the control capability of a grid electrode of the TFET to a device is stronger under low voltage, and the switching frequency characteristic of the TFET is far higher than that of the MOSFET device. In summary, TFETs have advantages over MOSFETs in terms of operating speed, static power consumption, etc. at low voltages. However, the unidirectional conductivity characteristics of TFETs limit the use of TFETs in SRAMs, particularly as the pass transistors of SRAMs, since conventional SRAMs require the pass transistors to conduct in both directions. Unidirectional conductivity means that when reverse bias and forward bias voltages are applied to the TFET, the current transfer characteristics are different. When a positive bias voltage is applied to the TFET, P-I-N positive bias current which is not controlled by gate voltage always appears, so that when the TFET is used as an SRAM transmission tube, positive bias leakage current can always appear in the transmission tube in a holding state, the static power consumption of a circuit is increased, and the stability of the SRAM in the holding state is influenced.
To overcome the P-I-N forward bias current that occurs when TFET devices are used as SRAM transistors, the academia proposes a stacked TFET transistors structure, as shown in fig. 1. Although this structure perfectly solves the P-I-N forward bias current problem of TFETs, stacking TFETs results in very weak write capability of the cell, and at minimum size, the cell cannot even write successfully (as shown in table 1). In order to realize the write function, the transfer tube must be increased in size, which results in an increase in the unit area and an increase in the chip cost.
Disclosure of Invention
The invention aims to provide a 10T TFET and MOSFET device hybrid SRAM unit circuit with high write margin, which avoids the problem of P-I-N forward bias current when a TFET is used as an SRAM transmission tube, thereby increasing the holding stability of the unit and reducing the power consumption of the unit. Meanwhile, the unit adopts a read-write separation mode, so that the read speed of the unit is improved. The transmission pipe of the unit adopts a mode of combining the TFET and the MOSFET device, so that the problem of poor conduction capability when the TFET is stacked is avoided, the writing capability of the unit is improved, and the writing operation function of the unit can be smoothly completed under the minimum size.
The purpose of the invention is realized by the following technical scheme:
a 10T TFET and MOSFET device hybrid SRAM cell circuit with high write margin, comprising: six NTFET transistors, two PTFET transistors, and two NMOSFET transistors; the six NTFET transistors are sequentially marked as N1-N6; two PTFET transistors designated as P1 and P2; the two NMOSFET transistors are respectively marked as N7 and N8; wherein:
VDD is electrically connected to the source of PTFET transistor P1 and the source of PTFET transistor P2;
a drain of PTFET transistor P1 electrically connected to the drain of NTFET transistor N1, the drain of NTFET transistor N3, the gate of PTFET transistor P2 and the gate of NTFET transistor N2;
a drain of PTFET transistor P2 electrically connected to the gate of PTFET transistor P1, the gate of NTFET transistor N1, the gate of NTFET transistor N6, the drain of NTFET transistor N2 and the drain of NTFET transistor N4;
the source of the NTFET transistor N3 is electrically connected to the drain of the NMOSFET transistor N7;
the source of the NTFET transistor N4 is electrically connected to the drain of the NMOSFET transistor N8;
the source of NTFET transistor N5 is electrically connected to the drain of NTFET transistor N6;
the source of the NTFET transistor N1, the source of the NTFET transistor N2, the source of the NTFET transistor N6, the source of the NMOSFET transistor N7, and the source of the NMOSFET transistor N8 are all electrically connected to GND.
Word line WL is electrically connected to the gate of NTFET transistor N3, and the gate of NTFET transistor N4; the bit line BL is electrically connected to the gate of the NMOSFET transistor N7; the bit line BLB is electrically connected to the gate of the NMOSFET transistor N8; read word line RWL is electrically connected to the gate of NTFET transistor N5; the read bit line RBL is electrically connected to the drain of an NTFET transistor N5.
According to the technical scheme provided by the invention, the SRAM transmission tube has better performance than a unit with a pure TFET stacking mode adopted by the SRAM transmission tube by utilizing a mode of combining a TFET and an MOSFET device, under the same working voltage and minimum size, the write margin of the SRAM unit structure provided by the embodiment of the invention is increased more, and the SRAM unit with the pure TFET stacking mode adopted by the transmission tube can not complete write operation under the minimum size; meanwhile, the SRAM unit circuit provided by the invention has the same maintaining noise tolerance and reading noise tolerance as those of an SRAM unit in a pure TFET stacking mode, but the technical scheme provided by the invention enables the unit to complete writing operation under the minimum size, so that the unit has great advantage in area.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a 10T stacked TFET SRAM cell circuit according to the background art of the present invention;
FIG. 2 is a schematic diagram of a 10T TFET and MOSFET device hybrid SRAM cell circuit with high write margin according to an embodiment of the present invention;
fig. 3 is a simulation waveform diagram of a 10T TFET and MOSFET device hybrid SRAM cell circuit with high write margin during read, write, and hold operations according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The basic device used by the traditional SRAM memory unit circuit is a MOSFET, the basic device used by the 10T TFET and MOSFET device hybrid SRAM unit circuit provided by the invention is a Tunneling Field Effect Transistor (TFET), and in order to eliminate the defects of P-I-N forward bias current and poor conduction capability of stacked TFETs when the TFET is used as an SRAM transmission tube, the invention provides a mode of combining the TFET and the MOSFET device for the SRAM transmission tube in the embodiment of the invention.
Fig. 2 is a schematic diagram of a 10T TFET and MOSFET device hybrid SRAM cell circuit (hereinafter referred to as SRAM cell circuit) with high write margin according to an embodiment of the present invention; it mainly comprises: six NTFET transistors, two PTFET transistors, and two NMOSFET transistors; the six NTFET transistors are sequentially marked as N1-N6; two PTFET transistors designated as P1 and P2; the two NMOSFET transistors are respectively marked as N7 and N8; the concrete structure is as follows:
VDD is electrically connected to the source of PTFET transistor P1 and the source of PTFET transistor P2;
a drain of PTFET transistor P1 electrically connected to the drain of NTFET transistor N1, the drain of NTFET transistor N3, the gate of PTFET transistor P2 and the gate of NTFET transistor N2;
a drain of PTFET transistor P2 electrically connected to the gate of PTFET transistor P1, the gate of NTFET transistor N1, the gate of NTFET transistor N6, the drain of NTFET transistor N2 and the drain of NTFET transistor N4;
the source of the NTFET transistor N3 is electrically connected to the drain of the NMOSFET transistor N7;
the source of the NTFET transistor N4 is electrically connected to the drain of the NMOSFET transistor N8;
the source of NTFET transistor N5 is electrically connected to the drain of NTFET transistor N6;
the source of the NTFET transistor N1, the source of the NTFET transistor N2, the source of the NTFET transistor N6, the source of the NMOSFET transistor N7, and the source of the NMOSFET transistor N8 are all electrically connected to GND.
Word line WL is electrically connected to the gate of NTFET transistor N3, and the gate of NTFET transistor N4; the bit line BL is electrically connected to the gate of the NMOSFET transistor N7; the bit line BLB is electrically connected to the gate of the NMOSFET transistor N8; read word line RWL is electrically connected to the gate of NTFET transistor N5; the read bit line RBL is electrically connected to the drain of an NTFET transistor N5.
In the above-described device of the SRAM cell circuit, the PTFET transistor P1 and the NTFET transistor N1, and the PTFET transistor P2 and the NTFET transistor N2 constitute two inverters, which constitute a latch portion of the SRAM cell circuit; NTFET transistors N5 and N6 constitute a circuit for reading and writing separately as a read operation part; by adopting the structure, the reading capability and the speed of the SRAM unit can be improved; the circuits of the latch part and the read operation part are all TFET devices. The transmission tube part of the SRAM unit circuit adopts a mode of combining NMOSFET and TFET devices, namely the NTFET transistors N3 and N4 and the NMOSFET transistors N7 and N8 form the transmission tube part of the SRAM unit circuit; therefore, the problems of P-I-N forward bias current (because the voltage of a storage point of an SRAM unit circuit is not less than 0 level) and low write margin of the stacked TFET transmission tube SRAM when the TFET is used as the SRAM transmission tube are solved; meanwhile, the conduction capability of the transmission tube is enhanced by the aid of the configuration mode of the transmission tube, and the NTFET transistors N3 and N4 have the advantage that the off current of the TFET is smaller, so that leakage current and static power consumption of the cell can be reduced when the cell is in a holding state.
The SRAM unit circuit adopts a read-write separation mode, and during write operation, a grid voltage control end of the NMOSFET adopts a boosting mode, namely when a bit line BL and a bit line BLB are enabled, the grid voltage of the NMOSFET is N volts, and the N is a set value (for example, 1.2 volts here).
The principle of the above-described SRAM cell circuit is described in conjunction with the simulated waveform diagram shown in fig. 3:
in the hold state, the word line WL, bit line BL and bit line BLB, and read word line RWL are low, and the NMOSFET transistors N7 and N8, and the NTFET transistors N3, N4, and N5 are all in the off state; although the leakage current of the NMOSFET transistor is larger than that of the NTFET in the off state, since the NTFET transistors N3 and N4 are in the off state, the static leakage current of the cell can be greatly reduced in the holding state regardless of the transfer transistor part and the circuit for the read function part, thereby reducing the power consumption of the cell. Meanwhile, the transmission tube structure cannot encounter the problem of P-I-N forward bias current when the voltage Vds of the TFET transmission tube is less than 0, and the static power consumption of the unit is reduced.
As the mode that the NMOSFET and the TFET device are combined is adopted in the transmission tube part, the defect of weak conduction capability when the TFET is stacked is avoided, and therefore the writing capability of the cell can be improved. When the SRAM unit circuit carries out write 0 operation, the word line WL is set to be high level, the bit line BL is set to be N volt (for example, 1.2 volt), the bit line BLB and the read word line RWL keep the original state 0 unchanged, and then the write 0 operation can be completed; when the SRAM unit circuit carries out 1 writing operation, the word line WL is set to be high level, the bit line BLB is set to be N volt (for example, 1.2 volt), the bit line BL and the reading word line RWL keep the original state 0 unchanged, and then 1 writing operation can be completed;
when the unit is read, the word line WL, the bit lines BL and BLB are at low level 0, the read word line RWL is at high level, if the SRAM unit circuit is stored as 0, the read bit line RBL is discharged through NTFET transistors N5 and N6, otherwise, the read bit line RBL is still at high level, and a sensitive amplifier in the SRAM array realizes the reading of the data stored in the SRAM unit circuit by detecting the level change of the read bit line RBL, so that the reading operation is completed.
In order to more clearly show the technical solutions and the technical effects provided by the present invention, the performance of the 10T TFET and MOSFET device hybrid SRAM cell circuit provided by the embodiment of the present invention is compared with other TFET SRAM cells.
Table 1 shows data obtained after testing the write margin (denoted as WSNM) by the word line scan method, the read noise margin (denoted as RSNM) by the butterfly curve (VTC) method, and the retention noise margin (denoted as HSNM) of the SRAM cell circuit provided by the embodiment of the present invention and the 10T stacked TFET SRAM cell circuit provided by the background art, both under the minimum size and the 0.4 v operating voltage.
Figure BDA0002118826230000061
TABLE 1
(1) As shown in table 1, a comparison of write margins of the 10T TFET and MOSFET device hybrid SRAM cell circuit proposed by the embodiment of the present invention and the 10T stacked TFET SRAM cell in the background art is shown. The write margin (denoted as WSNM) is obtained by a method of word line scanning. From the experimental simulation results, it can be seen from the table that the 10T TFET and MOSFET device hybrid SRAM cell circuit provided by the present invention has a larger write margin than the 10T stacked TFET SRAM cell in the background art, under the condition of 0.4 v operating voltage and the minimum size of both cells. While the 10T stacked TFET SRAM cell in the background art cannot complete the write operation at the minimum size. The invention is because when the structure provided by the invention is used for writing, the transmission tube structure adopts a mode of combining a TFET device and an MOSFET device, thereby improving the writing capability, utilizing the advantage of smaller off current of the TFET and overcoming the P-I-N forward bias current of the TFET.
(2) As shown in table 1, the read noise margin and the retention noise margin (RSNM, HSNM, respectively) of the 10T TFET and MOSFET device hybrid SRAM cell circuit proposed by the embodiment of the present invention are compared with the 10T stacked TFET SRAM cell in the background art. Since the structures of the 10T TFET and MOSFET device hybrid SRAM cell circuit and the 10T stacked TFET SRAM cell in the background art proposed by the embodiments of the present invention both adopt the read-write separation method, and the read noise margin and the retention noise margin of the cell adopting the read-write separation structure are the same as the measurement result by the butterfly curve method (VTC), the measurement results of the read noise margin and the retention noise margin of the 10T TFET and MOSFET device hybrid SRAM cell proposed by the embodiments of the present invention are the same as the measurement result of the 10T stacked TFET SRAM cell in the background art. From experimental simulation results, it can be seen from the figure that under the condition of 0.4 volt working voltage and the minimum size of both cells, the 10T TFET and MOSFET device hybrid SRAM cell circuit provided by the invention has the same read noise tolerance and hold noise tolerance as the 10T stacked TFET SRAM cell in the background art. However, the 10T stacked TFET SRAM cell in the background art cannot complete the write operation at the minimum size, so the cell proposed by the present invention has great advantages.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (3)

1. A 10T TFET and MOSFET device hybrid SRAM cell circuit with high write margin, comprising: six NTFET transistors, two PTFET transistors, and two NMOSFET transistors; the six NTFET transistors are sequentially marked as N1-N6; two PTFET transistors designated as P1 and P2; the two NMOSFET transistors are respectively marked as N7 and N8; wherein:
VDD is electrically connected to the source of PTFET transistor P1 and the source of PTFET transistor P2;
a drain of PTFET transistor P1 electrically connected to the drain of NTFET transistor N1, the drain of NTFET transistor N3, the gate of PTFET transistor P2 and the gate of NTFET transistor N2;
a drain of PTFET transistor P2 electrically connected to the gate of PTFET transistor P1, the gate of NTFET transistor N1, the gate of NTFET transistor N6, the drain of NTFET transistor N2 and the drain of NTFET transistor N4;
the source of the NTFET transistor N3 is electrically connected to the drain of the NMOSFET transistor N7;
the source of the NTFET transistor N4 is electrically connected to the drain of the NMOSFET transistor N8;
the source of NTFET transistor N5 is electrically connected to the drain of NTFET transistor N6;
the source of the NTFET transistor N1, the source of the NTFET transistor N2, the source of the NTFET transistor N6, the source of the NMOSFET transistor N7, and the source of the NMOSFET transistor N8 are all electrically connected to GND;
word line WL is electrically connected to the gate of NTFET transistor N3, and the gate of NTFET transistor N4; the bit line BL is electrically connected to the gate of the NMOSFET transistor N7; the bit line BLB is electrically connected to the gate of the NMOSFET transistor N8; read word line RWL is electrically connected to the gate of NTFET transistor N5; the read bit line RBL is electrically connected to the drain of an NTFET transistor N5.
2. The 10T TFET and MOSFET device hybrid SRAM cell circuit with high write margin of claim 1,
the PTFET transistor P1 and the NTFET transistor N1, and the PTFET transistor P2 and the NTFET transistor N2 constitute two inverters which constitute a latch portion of the SRAM cell circuit; NTFET transistors N5 and N6 constitute a circuit for reading and writing separately as a read operation part; the transmission tube part of the SRAM unit circuit adopts a mode of combining NMOSFET and TFET devices, namely the NTFET transistors N3 and N4 and the NMOSFET transistors N7 and N8 form the transmission tube part of the SRAM unit circuit;
the SRAM unit circuit adopts a read-write separation mode, and during write operation, a grid voltage control end of the NMOSFET adopts a boosting mode, namely when a bit line BL and a bit line BLB are enabled, the grid voltage is N V, and N is a set value.
3. The 10T TFET and MOSFET device hybrid SRAM cell circuit with high write margin of claim 1,
in the hold state, the word line WL, bit line BL and bit line BLB, and read word line RWL are low, and the NMOSFET transistors N7 and N8, and the NTFET transistors N3, N4, and N5 are all in the off state;
when the SRAM unit circuit carries out write 0 operation, the word line WL is set to be high level, the bit line BL is set to be N volt, the bit line BLB and the read word line RWL keep the original state 0 unchanged, and then the write 0 operation can be completed; when the SRAM unit circuit carries out 1 writing operation, the word line WL is set to be high level, the bit line BLB is set to be N volt, the bit line BL and the reading word line RWL keep the original state 0 unchanged, and then 1 writing operation can be completed;
when the unit is read, the word line WL, the bit lines BL and BLB are at low level 0, the read word line RWL is at high level, if the SRAM unit circuit is stored as 0, the read bit line RBL is discharged through NTFET transistors N5 and N6, otherwise, the read bit line RBL is still at high level, and a sensitive amplifier in the SRAM array realizes the reading of the data stored in the SRAM unit circuit by detecting the level change of the read bit line RBL, so that the reading operation is completed.
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