CN112133347B - Memory unit based on 7T1C structure, operation method thereof and memory - Google Patents
Memory unit based on 7T1C structure, operation method thereof and memory Download PDFInfo
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- CN112133347B CN112133347B CN202010957666.1A CN202010957666A CN112133347B CN 112133347 B CN112133347 B CN 112133347B CN 202010957666 A CN202010957666 A CN 202010957666A CN 112133347 B CN112133347 B CN 112133347B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/416—Read-write [R-W] circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a memory unit based on a 7T1C structure, an operation method thereof and a memory. Wherein the memory cell includes: a 6T structure and a 1T1C structure, the 6T structure being used for input and storage of data 1 or 0; the 1T1C structure is connected with a first storage node of the 6T structure and is used for storing data 1 or 0 when the 6T structure is powered off and recovering the data 1 or 0 to the 6T structure when the 6T structure is powered on. By the 1T1C structure, under the condition of not changing a read-write circuit of the SRAM in the prior art, good structural compatibility is maintained by a simple circuit design, leakage current is prevented, meanwhile, the increase of the area size of a memory cell is avoided, the operation speed is higher, and the static power consumption is lower.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a memory unit based on a 7T1C structure, an operation method thereof and a memory.
Background
An energy-saving chip (applicable to wearable equipment, internet of things equipment and the like) adopts a static random access memory (Static random access memory, SRAM) for calculation, and a Non-volatile memory (NVM) for power-off storage so as to reduce standby current. However, this 2 macro (sram+nvm) scheme is slow to store (power down) due to high power consumption. Thus, in the case of using a low power supply voltage in the sleep mode, the sram+nvm scheme cannot realize a frequent power-off and a recovery (power-on) operation caused by serially transmitting data word by word.
Ferroelectric memories have led to the development of non-volatile logic incorporating NVM into CMOS circuitry in Flip-Flop (FF), SRAM or ternary content addressable memory (Ternary Content Addressable Memory, TCAM) to enable parallel data movement between NVM devices and CMOS due to recent advances in NVM devices compatible with complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) logic processes. Nonvolatile memory devices are mainly used for fast, local and low power storage/restore operations. Compared with the SRAM+NVM scheme, the NVSRAM unit performs parallel transmission between each unit of the SRAM and the NVM device, and has the characteristics of low power consumption and parallel data recovery, so that the NVSRAM unit is widely applied to the Internet of things.
Currently, various NVSRAM cells have been developed using magnetic tunnel junction (Magnetic Tunnel Junctions, MTJ) and resistive memory (Resistive Random Access Memory, reRAM) devices, such as 4T2R, 6T2R, 7T2R, 8T2R, and 7T1R, among others. However, the NVSRAM cells of the various structures described above in the prior art still have various drawbacks:
1) The NVSRAM cells of the 4T2R, 6T2R and 7T2R structures, although small in area, suffer from a large Direct Current (DC) short circuit Current at the storage nodes (Q and QB), and the stability of the structural cells is significantly reduced in the SRAM mode;
2) Although the NVSRAM unit with the 8T2R structure eliminates DC short-circuit current in the SRAM mode, the consumed memory area is large, and the NVSRAM unit with the 8T2R structure based on two nonvolatile memory devices can realize high recovery rate, but consumes extremely large memory and recovery power consumption due to the use of the two memory devices;
3) The RRAM-based 7T1R architecture of NVSRAM cells can reduce storage power consumption but the number of times of storage and recovery is low.
Disclosure of Invention
First, the technical problem to be solved
In order to solve at least one technical problem of the NVSRAM unit in the prior art, the invention discloses a memory unit based on a 7T1C structure, an operation method thereof and a memory.
(II) technical scheme
One aspect of the invention discloses a memory cell based on a 7T1C structure, comprising: a 6T structure and a 1T1C structure, the 6T structure being used for input and storage of data 1 or 0; the 1T1C structure is connected with a first storage node of the 6T structure and is used for storing data 1 or 0 when the 6T structure is powered off and recovering the data 1 or 0 to the 6T structure when the 6T structure is powered on.
Optionally, the 1T1C structure comprises: and the switching transistor is connected with the first storage node of the 6T structure and used for controlling the conduction of the passage of the 1T1C structure.
Optionally, the switching transistor is an NMOS transistor or a PMOS transistor; the gate of the switching transistor is connected to the switching word line SWL, and the source is connected to the first storage node.
Optionally, the 1T1C structure further comprises: and one end of the ferroelectric memory unit is connected with the drain electrode of the switching transistor, and the other end of the ferroelectric memory unit is connected with the control line PL, and is used for storing data 1 or 0 when the 6T structure is powered off and recovering the data 1 or 0 to the structure of claim 6T when the 6T structure is powered back.
Optionally, the 6T structure comprises: a first inverter and a second inverter. The first inverter is used for providing a first storage node to store data 1 or 0; the second inverter is cross-coupled with the first inverter and symmetrically arranged with respect to each other for providing a second storage node which stores data 1 when the first storage node stores data 0 and stores data 0 when the first storage node stores data 1.
Optionally, the first inverter includes: a first upper transistor and a first lower transistor, a source of the first upper transistor being connected to the control word line PWL; the first lower transistor and the first upper transistor are symmetrically arranged in the first direction, the source electrode of the first lower transistor is connected with the drain electrode of the first upper transistor, the drain electrode is grounded, and the grid electrode is connected with the grid electrode of the first upper transistor.
Optionally, the second inverter includes: a second upper transistor and a second lower transistor symmetrically arranged in a second direction with the first upper transistor, the source electrode being connected to the control word line PWL; the second lower transistor and the second upper transistor are symmetrically arranged in the first direction, the second lower transistor and the first lower transistor are symmetrically arranged in the second direction, the source electrode is connected with the drain electrode of the second upper transistor, the drain electrode is grounded, and the grid electrode is connected with the grid electrode of the second upper transistor.
Optionally, the 6T structure further comprises: a first access transistor and a second access transistor, wherein the grid electrode of the first access transistor is connected with a word line, the source electrode of the first access transistor is connected with a first storage node, and the drain electrode of the first access transistor is connected with an inverted bit line; the second access transistor and the first access transistor are symmetrically arranged in the second direction, the grid electrode of the second access transistor is connected with the word line, the source electrode of the second access transistor is connected with the second storage node, and the drain electrode of the second access transistor is connected with the bit line.
Optionally, the first storage node is connected to a drain of a first upper transistor of the first inverter and a gate of a second upper transistor of the second inverter; the second storage node is connected to the gate of the first upper transistor of the first inverter and the drain of the second upper transistor of the second inverter.
Another aspect of the invention discloses a memory based on a 7T1C structure, having a memory cell array structure comprising a plurality of memory cells based on the 7T1C structure described above.
Another aspect of the present invention discloses a method for operating the above memory cell based on a 7T1C structure, which includes: in response to a power-off operation of the memory cell, the 1T1C structure is applied with a positive pulse voltage, storing data 1 or 0 stored by the 6T structure at the first storage node into the 1T1C structure of claim 1; in response to a power-on operation of the memory cell, the 1T1C structure is applied with a positive pulse voltage, the data 1 or 0 stored in the 1T1C structure is restored to the 6T structure, and the 1T1C structure enters a floating state.
(III) beneficial effects
The invention discloses a memory unit based on a 7T1C structure, an operation method thereof and a memory. Wherein the memory cell includes: a 6T structure and a 1T1C structure, the 6T structure being used for input and storage of data 1 or 0; the 1T1C structure is connected with a first storage node of the 6T structure and is used for storing data 1 or 0 when the 6T structure is powered off and recovering the data 1 or 0 to the 6T structure when the 6T structure is powered on. By the 1T1C structure, under the condition of not changing a read-write circuit of the SRAM in the prior art, good structural compatibility is maintained by a simple circuit design, leakage current is prevented, meanwhile, the increase of the area size of a memory cell is avoided, the operation speed is higher, and the static power consumption is lower.
Drawings
FIG. 1 is a schematic diagram of a 7T1C structure-based memory cell according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method of operating a 7T1C structure based memory cell according to an embodiment of the invention;
fig. 3 is a schematic diagram illustrating an operation timing of a memory cell based on a 7T1C structure according to an embodiment of the present invention.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
It should be noted that, in the drawings or the text of the specification, implementations not shown or described are all forms known to those of ordinary skill in the art, and not described in detail. Furthermore, the above definitions of the elements and methods are not limited to the specific structures, shapes or modes mentioned in the embodiments, and may be simply modified or replaced by those of ordinary skill in the art.
It should be further noted that, the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the drawings, and are not intended to limit the scope of the present disclosure. Like elements are denoted by like or similar reference numerals throughout the drawings. Conventional structures or constructions will be omitted when they may cause confusion in understanding the present disclosure.
And the shapes and dimensions of the various elements in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. In addition, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the description and in the claims to modify a corresponding element does not by itself connote any ordinal number of elements and does not by itself indicate the order in which a particular element is joined to another element or the order in which it is manufactured, but rather the use of ordinal numbers merely serves to distinguish one element having a particular name from another element having a same name.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, in addition, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also, in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
The NVSRAM cells in various structural forms present in the prior art still have various drawbacks:
1) NVSRAM cells in the form of 4T2R, 6T2R, and 7T2R structures are subject to large DC short circuit currents at the storage nodes and the stability of the structural cells is poor in the normal operation mode of the SRAM;
2) The NVSRAM unit with the 8T2R structure form eliminates DC short-circuit current in an SRAM mode, but occupies larger memory area, is unfavorable for high-density integration, and has extremely large power consumption in the processes of storage and recovery due to the use of two memory devices;
3) The number of store and restore operations for a RRAM-based 7T1R architecture of NVSRAM cells is too low.
In order to solve at least one technical problem of the NVSRAM unit in the prior art, the invention discloses a memory unit based on a 7T1C structure, an operation method thereof and a memory.
As shown in fig. 1, in one aspect, the present invention discloses a memory cell based on a 7T1C structure, wherein the memory cell is an NVSRAM cell, and includes: a 6T structure and a 1T1C structure, the 6T structure being used for input and storage of data 1 or 0; the 1T1C structure is connected to the first storage node QB of the 6T structure for storing data 1 or 0 when the 6T structure is powered off and restoring data 1 or 0 to the 6T structure when the 6T structure is powered on.
As shown in FIG. 1, the 6T structure includes 6 transistors (transistors) M1, M2, M3, M4, M5, M6, which may be an SRAM cell. In the normal working mode, the 6T structure is used for performing normal read-write operation and the like by a normal read-write operation circuit serving as an SRAM memory cell. The 1T1C structure comprises an M7 transistor and a FeRaM unit, and is used for storing and recovering data 1 or 0 stored in the 6T structure when the 6T structure cannot perform normal read-write operation and the like in an abnormal working mode. Specifically, the abnormal operating mode is the process of power off or power up restoration (restore) of the NVSRAM cell. During power down, in response to the power down of the NVSRAM cell, the transistor M7 generates a path, so that the FeRaM cell uses the transistor M7 as a switch path to receive the data 1 or 0 (i.e. the weight) of the 6T structure storage node QB or Q for storage (store). In the recovery process, in response to the power-up of the NVSRAM cell, the transistor M7 generates a path, so that the FeRaM cell uses the transistor M7 as a switch path to transmit the weight 1 or 0 stored in the power-off process to the first storage node QB and the second storage node Q of the 6T structure for storage through the first storage node QB, thereby completing the weight recovery (restore) of the 6T structure. The working time of the power-off process and the power-on recovery process is extremely short, and due to the existence of the 1T1C structure, DC short-circuit current at the QB position of the first storage node is avoided, so that normal read-write operation of the 6T structure is not affected, and the stability of the whole NVSRAM unit is higher.
Therefore, by the 1T1C structure, under the condition of not changing the read-write circuit of the SRAM unit in the prior art, good structural compatibility is maintained by simple circuit design, leakage current is prevented, the size of the area of the memory unit is simultaneously considered, the operation speed is higher, the static power consumption is lower, and the size of the whole device is smaller.
As shown in fig. 1, according to an embodiment of the present invention, a 1T1C structure includes: a switching transistor M7, the switching transistor M7 being connected to the first storage node QB of the 6T structure for controlling the pass-through of the 1T1C structure to be turned on in response to the power-up or power-down of the NVSRAM cell; the switching transistor M7 is a MOS transistor (Metal Oxide Semiconductor Transisitor), specifically may be an NMOS transistor or a PMOS transistor, and has a function of controlling a pass switch, so as to achieve a switching effect.
According to an embodiment of the present invention, the gate of the switching transistor M7 is connected to the switching word line FSWL for being used as an operating voltage input of the switching transistor M7, and the source of the switching transistor M7 is connected to the first storage node QB for turning on the first storage node QB and the FeRaM unit when the switching transistor M7 is turned on; the drain of the switching transistor M7 is connected to one end of the FeRaM unit.
As shown in fig. 1, according to an embodiment of the present invention, the 1T1C structure further includes: a ferroelectric memory cell, i.e. the aforementioned FeRaM cell, having one end connected to the drain of the switching transistor M7 and the other end connected to the control line PL, is used to store data 1 or 0 when the 6T structure is powered down and to restore data 1 or 0 to the structure of claim 6T when the 6T structure is powered back up.
Specifically, the FeRaM unit is a nonvolatile memory which does not lose content when power is off, and has the advantages of high density, high speed, low power consumption and radiation resistance. The FeRaM unit is a memory prepared from ferroelectric materials and mainly comprises ferroelectric materials with perovskite structures and the like. Based on the ferroelectric polarization characteristic, the capacitor of the ferroelectric film structure replaces the conventional capacitor for storing charges, and the data writing and reading are realized by utilizing the polarization inversion of the ferroelectric film, so that the problem of leakage current is fundamentally solved after the 6T structure is powered off and the power on is restored, the power consumption of the memory is reduced, and the memory has stronger competitiveness in the application field of low power consumption of the Internet of things.
It should be noted that, due to the polarization characteristics of the FeRaM unit of the embodiment of the present invention, in the process that the memory unit of the present invention is in the memory mode and the recovery mode, the electron movement is accelerated due to the action of the polarization electric field, so that the speed of memory and recovery is faster.
In an embodiment of the present invention, as shown in fig. 1, when the 6T structure is powered down, the 1T1C structure of the present invention enters a storage Mode (Store Mode), the access transistors M5 and M6 of the 6T structure are turned on, and the data on the bit line BLB and the bit line BL are written into the storage nodes QB and Q. Accordingly, the transistor M7 of the 1T1C structure is turned on and a positive pulse voltage is applied to the control line PL. Wherein if the first storage node QB is a logic "1" (i.e. the storage weight is 1), the voltage difference across the FeRAM cell is V before the positive pulse voltage of the control line PL arrives DD And the FeRAM cell will therefore be polarised to a positive polarisation state, data "1" being successfully saved to the FeRAM cell; if the second storage node Q is logic "0" (i.e. the storage weight is 0), the voltage difference across the FeRAM cell is 0 before the positive pulse voltage of the control line PL is 0, and the voltage difference across the FeRAM cell is-V when the positive pulse voltage arrives DD The FeRAM cell is thus polarized to a negative polarization state and, therefore, data "0" is also successfully saved to the FeRAM cell.
In an embodiment of the present invention, as shown in fig. 1, when the 6T structure is powered back, the 1T1C structure of the present invention enters a Restore Mode (Restore Mode), and the transistor M7 of the 1T1C structure and the power supply are turned on. Then, a positive pulse voltage is applied to the control line PL. At this time, the polarization state of the ferroelectric capacitor will reach a positive saturation state, regardless of whether the original FeRaM cell (corresponding to the ferroelectric capacitor) has stored a weight of "0" or "1". If the original storage weight of the FeRAM cell is "1", the first storage node QB of the 6T structure will have an amount of charge of 2Qr at "1", and the second storage node Q is discharged through transistor M3, so that the weight "1" is restored onto the corresponding first storage node QB in the 6T structure. If the original storage weight of FeRAM is "0", the first storage node QB will have a corresponding amount of Qr charge, and the first storage node QB is turned on by the control transistor M4, so that the voltage at the second storage node Q rises rapidly and thus turns on the transistor M1. Therefore, the first storage node QB finally discharges and restores to the weight value of "0", and accurate restoration of data is finally realized. It should be noted that, since the memory cell of the present invention has an asymmetric structure due to the 1T1C structure, the execution process of the recovery weight "0" is more complicated than that of the recovery weight "1". However, by means of the asymmetric structure, the area size of the memory cell is controlled to be smaller compared with that of a traditional NVSRAM cell, for example, compared with the existing structures such as 7T2R, 8T2R and the like, the memory cell has a 7T1C structure with 7 transistors and 1 FeRaM cell, the structure type is simpler, and the memory size can be controlled better.
It should be noted that, when the memory cell of the present invention is in the normal operation Mode, the transistor M7 of the 1T1C structure is in the off-state, so that the FeRaM cell is in the floating state, and therefore the 6T structure is in the SRAM Mode (SRAM Mode). Therefore, the memory unit of the invention does not change the read-write circuit of the prior SRAM, does not increase the design complexity of the prior SRAM circuit, and keeps better circuit compatibility. In addition, in the normal SRAM operation mode, the switching transistor M7 is in the off state, and the path is opened, so that the FeRaM unit is in the floating state, and therefore, the 1T1C structure of the memory unit does not affect the stability of the existing SRAM structure.
As shown in fig. 1, according to an embodiment of the present invention, the 6T structure includes: a first inverter and a second inverter. The first inverter is used for providing a first storage node QB to store data 1 or 0; the second inverter is cross-coupled with the first inverter and symmetrically disposed with respect to each other in a second direction to provide a second storage node Q storing data 1 when the first storage node QB stores data 0 and storing data 0 when the first storage node QB stores data 1. It should be understood by those skilled in the art that in the embodiment of the present invention, data 0 or 1 is weight 0 or 1.
According to an embodiment of the present invention, a first inverter includes: a first upper transistor M2 and a first lower transistor M1, the source of the first upper transistor M2 being connected to the control word line PWL; the first lower transistor M1 and the first upper transistor M2 are symmetrically arranged in the first direction, the source of the first lower transistor M1 is connected with the drain of the first upper transistor M2, and the drain of the first lower transistor M1 is grounded V SS The gate of the first lower transistor M1 is connected to the gate of the first upper transistor M2. Based on the above structure, the first inverter of the embodiment of the present invention can be constituted.
According to an embodiment of the present invention, the second inverter includes: a second upper transistor M4 and a second lower transistor M3, the second upper transistor M4 and the first upper transistor M2 being symmetrically arranged in a second direction, a source of the second upper transistor M4 being connected to the control word line PWL; the second lower transistor M3 and the second upper transistor M4 are symmetrically arranged in the first direction, the second lower transistor M3 and the first lower transistor M1 are symmetrically arranged in the second direction, the source electrode of the second lower transistor M3 is connected with the drain electrode of the second upper transistor M4, the drain electrode of the second lower transistor M3 is grounded V SS The gate of the second lower transistor M3 is connected to the gate of the second upper transistor M4. Based on the above structure, the second inverter symmetrical to and cross-coupled with the first inverter in the embodiment of the present invention may be configured.
As shown in fig. 1, according to an embodiment of the present invention, the 6T structure further includes: a first access transistor M5 and a second access transistor M6, the gate of the first access transistor M5 being connected to the word line WL, the source of the first access transistor M5 being connected to the first storage node QB, the drain of the first access transistor M5 being connected to the bit bar BLB; the second access transistor M6 and the first access transistor M5 are symmetrically disposed in the second direction, the gate of the second access transistor M6 is connected to the word line WL, the source of the second access transistor M6 is connected to the second storage node QB, and the drain of the second access transistor M6 is connected to the bit line BL.
According to an embodiment of the present invention, the first storage node QB is connected to the drain of the first upper transistor M2 of the first inverter and the gate of the second upper transistor M4 of the second inverter; the second storage node Q is connected to the gate of the first upper transistor M2 of the first inverter and the drain of the second upper transistor M4 of the second inverter. Thus, it may be achieved that the first inverter stores a weight of 1 or 0 to the first storage node QB through the inverse bit line BLB and/or that the second inverter stores a weight of 0 or 1 to the second storage node Q through the bit line BL.
Another aspect of the invention discloses a memory based on a 7T1C structure, having a memory cell array structure comprising a plurality of memory cells based on the 7T1C structure described above.
As shown in fig. 2, another aspect of the present invention discloses a method for operating the above-mentioned memory cell based on the 7T1C structure, wherein the method for operating the memory cell includes:
s201: in response to a power-off operation of the memory cell, the 1T1C structure is applied with a positive pulse voltage, storing data 1 or 0 stored by the 6T structure at the first storage node into the 1T1C structure of claim 1;
s202: in response to a power-on operation of the memory cell, the 1T1C structure is applied with a positive pulse voltage, the data 1 or 0 stored in the 1T1C structure is restored to the 6T structure, and the 1T1C structure enters a floating state.
As shown in fig. 1 and 3, when the memory cell of the present invention is in the normal operation Mode (SRAM Mode) of the SRAM, the SRAM cell of the 6T structure performs normal writing and reading operations.
When the storage unit is powered off, the weight data cannot be stored normally in the 6T structure, the 1T1C structure is controlled to be conducted with the first storage node QB of the 6T structure, the storage unit enters a storage Mode (Store Mode), the FeRAM unit of the 1T1C structure is used as a capacitor junction to Store the storage weight of the first storage node QB and the second storage node Q of the 6T structure, and at the moment, the storage of the storage data of the 6T structure is completed, and the reaction time of the storage Mode is delta T1. Thereafter, the memory cell is in a Power Off state (Power Off) and normal write and read operations cannot continue.
When the storage unit is recovered and powered on, the 1T1C structure is controlled to be conducted with the first storage node QB of the 6T structure, so that the storage unit enters a recovery Mode (Restore Mode), the FeRAM unit of the 1T1C structure is used as a capacitor junction to Restore the storage weight of the first storage node QB of the 6T structure, and the 6T structure finishes the recovery storage of original storage data in the first storage node QB and the second storage node Q, wherein the reaction time of the recovery Mode is delta T2. Thereafter, the memory cell is in a power-on state and normal write and read operations can continue.
Thus, embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.
While the foregoing is directed to embodiments of the present invention, other and further details of the invention may be had by the present invention, it should be understood that the foregoing description is merely illustrative of the present invention and that no limitations are intended to the scope of the invention, except insofar as modifications, equivalents, improvements or modifications are within the spirit and principles of the invention.
Claims (9)
1. The NVSRAM storage unit based on the 7T1C structure is characterized by comprising a 6T structure and a 1T1C structure;
the 6T structure is used as an SRAM memory cell for inputting and storing data 1 or 0;
the 1T1C structure is connected with a first storage node (QB) of the 6T structure and is used for storing the data 1 or 0 when the 6T structure is powered off and recovering the data 1 or 0 to the 6T structure when the 6T structure is powered on;
the 1T1C structure for avoiding a DC short circuit current at a first storage node (QB) location, the 1T1C structure comprising:
a switching transistor (M7) connected to the first storage node (QB) of the 6T structure for controlling the pass of the 1T1C structure to be turned on; the gate of the switching transistor (M7) is connected with a Switching Word Line (SWL), and the source is connected with the first storage node (QB);
a ferroelectric memory cell (FeRAM) having one end connected to the drain of the switching transistor (M7) and the other end connected to a control line (PL) for storing the data 1 or 0 when the 6T structure is powered off and for restoring the data 1 or 0 to the 6T structure when the 6T structure is restored to power;
in a normal working mode, the 6T structure is used for performing normal read-write operation by a normal read-write operation circuit serving as an SRAM storage unit;
in the power-off process of an abnormal working mode, responding to the power-off of the NVSRAM unit, a switch transistor (M7) generates a passage, so that the ferroelectric memory unit (FeRAM) takes the switch transistor (M7) as a switch passage to receive data 1 or 0 of a first storage node (QB) or a second storage node (Q) of a 6T structure for storage;
in the recovery process of the abnormal working mode, in response to the power-on of the NVSRAM unit, the switch transistor (M7) generates a passage, so that the ferroelectric memory unit (FeRAM) takes the switch transistor (M7) as the switch passage, and the weight 1 or 0 stored in the power-off process is transmitted to the first storage node (QB) or the second storage node (Q) of the 6T structure through the first storage node (QB) to be stored, namely the weight recovery of the 6T structure is completed.
2. A memory cell according to claim 1, characterized in that the switching transistor (M7) is an NMOS transistor or a PMOS transistor.
3. The memory cell of claim 1, wherein the 6T structure comprises:
a first inverter for providing a first storage node (QB) to store data 1 or 0;
and a second inverter cross-coupled with the first inverter and symmetrically arranged with each other for providing a second storage node (Q) storing data 1 when the first storage node (QB) stores data 0 and storing data 0 when the first storage node (QB) stores data 1.
4. The memory cell of claim 3, wherein the first inverter comprises:
a first upper transistor (M2) having a source connected to the control word line (PWL),
the first lower transistor (M1) is symmetrically arranged with the first upper transistor (M2) in the first direction, a source electrode is connected with a drain electrode of the first upper transistor (M2), the drain electrode is grounded, and a grid electrode is connected with a grid electrode of the first upper transistor (M2).
5. The memory cell of claim 4, wherein the second inverter comprises:
a second upper transistor (M4) symmetrically arranged in the second direction with the first upper transistor (M2), a source electrode connected with the control word line (PWL),
the second lower transistor (M3) is symmetrically arranged with the second upper transistor (M4) in the first direction, is symmetrically arranged with the first lower transistor (M1) in the second direction, has a source electrode connected with the drain electrode of the second upper transistor (M4), has a drain electrode grounded, and has a gate electrode connected with the gate electrode of the second upper transistor (M4).
6. The memory cell of claim 3, wherein the 6T structure further comprises:
a first access transistor (M5) having a gate connected to the word line, a source connected to the first storage node (QB), a drain connected to the bit bar line,
the second access transistor (M6) is symmetrically arranged in the second direction with the first access transistor (M5), the grid electrode is connected with the word line, the source electrode is connected with the second storage node (Q), and the drain electrode is connected with the bit line.
7. The memory cell of claim 6, wherein the memory cell is configured to store, in the memory cell,
the first storage node (QB) is connected with the drain electrode of a first upper transistor (M2) of the first inverter and the gate electrode of a second upper transistor (M4) of the second inverter;
the second storage node (Q) is connected to the gate of the first upper transistor (M2) of the first inverter and the drain of the second upper transistor (M4) of the second inverter.
8. A method of operation of a 7T1C structure based memory cell as claimed in any one of claims 1 to 7, comprising:
in response to a power-off operation of the memory cell, the 1T1C structure is applied with a positive pulse voltage, and data 1 or 0 stored by the 6T structure at a first storage node is stored into the 1T1C structure;
in response to a power-on operation of the memory cell, the 1T1C structure is applied with a positive pulse voltage to restore data 1 or 0 stored in the 1T1C structure into the 6T structure, the 1T1C structure entering a floating state.
9. A memory based on a 7T1C structure having a memory cell array structure comprising a plurality of memory cells based on a 7T1C structure as claimed in any one of claims 1 to 7.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103093811A (en) * | 2011-11-03 | 2013-05-08 | 中国科学院微电子研究所 | Flash memory current-limiting device and flash memory with the flash memory current-limiting device |
| US9899085B1 (en) * | 2016-12-29 | 2018-02-20 | AUCMOS Technologies USA, Inc. | Non-volatile FeSRAM cell capable of non-destructive read operations |
| CN110326049A (en) * | 2016-10-28 | 2019-10-11 | 美国Aucmos科技股份有限公司 | Without the ferroelectric storage unit of printed line |
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| US7050323B2 (en) * | 2002-08-29 | 2006-05-23 | Texas Instruments Incorporated | Ferroelectric memory |
| JP2019194931A (en) * | 2018-05-01 | 2019-11-07 | ローム株式会社 | Semiconductor memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103093811A (en) * | 2011-11-03 | 2013-05-08 | 中国科学院微电子研究所 | Flash memory current-limiting device and flash memory with the flash memory current-limiting device |
| CN110326049A (en) * | 2016-10-28 | 2019-10-11 | 美国Aucmos科技股份有限公司 | Without the ferroelectric storage unit of printed line |
| US9899085B1 (en) * | 2016-12-29 | 2018-02-20 | AUCMOS Technologies USA, Inc. | Non-volatile FeSRAM cell capable of non-destructive read operations |
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