CN103093811A - Flash memory current-limiting device and flash memory with the flash memory current-limiting device - Google Patents
Flash memory current-limiting device and flash memory with the flash memory current-limiting device Download PDFInfo
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- CN103093811A CN103093811A CN2011103437399A CN201110343739A CN103093811A CN 103093811 A CN103093811 A CN 103093811A CN 2011103437399 A CN2011103437399 A CN 2011103437399A CN 201110343739 A CN201110343739 A CN 201110343739A CN 103093811 A CN103093811 A CN 103093811A
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Abstract
The invention discloses a flash memory current-limiting device and a flash memory with the flash memory current-limiting device. The flash memory current-limiting device is arranged outside a memory cell array of the flash memory. The flash memory current-limiting device comprises a transmission pipe, a reference current generation module and a current-limiting unit. The transmission pipe is a PMOS pipe. A gate terminal of the transmission pipe is connected to a voltage control signal, a drain terminal of the transmission pipe is connected to voltage PHV needed by a source terminal erasing process on a memory cell in the memory cell array, and a source terminal of the transmission pipe is connected to a source line in the memory cell. The source terminal of the PMOS pipe and the source line of the memory cell are used as one input end of the current-limiting unit in common. A reference current produced by the reference current generation module is used as the other input end of the current-limiting unit. The flash memory current-limiting device is not integrated with the memory cell array so that a large chip area is saved.
Description
Technical field
The present invention relates to microelectronic industry memory technology field, relate in particular to a kind of flash memory current-limiting apparatus and use the flash memory of this device.
Background technology
In general, apply suitable voltage at source electrode, drain electrode and the control grid of flash memory cell, electric charge will be stored or be removed, so data just can be stored in storage unit or from cell erase with the form of this electric charge.Appearance or the disappearance of electric charge on floating grid determines when storage unit was selected, whether electric current flowed between source electrode and drain region.By the size of electric current between source electrode and drain region in the judgement storage unit, the content of distinguishing storage is " 0 " or " 1 ".Typically, the bit line of flash memory cell in array connects the drain electrode of the storage unit of arbitrary particular row, and the word line connects the grid of the storage unit of arbitrary particular column.The source electrode of each storage unit is understood ground connection usually.
Flash memory not only only has the function that reads, the function of programming in addition and wiping.Complete these the operation just need to selecteed storage unit in storage array be expert at the correspondence bit line, apply a quite high voltage.In addition, the word line that selecteed storage unit is expert at and is connected also can be applied in a high-tension electricity.Its drain and gate is applied in the high voltage generation current and is used for producing electric charge.Yet when carrying out these operator schemes, be positioned at the drain electrode of the non-selected storage unit with delegation with selecteed storage unit, also can receive the current potential of high voltage bit line, and then cause electric current when closing or leakage current to flow between the source electrode of these non-selected storage unit and drain electrode.Although the leakage current of single storage unit may be minimum, the leakage current summation of each non-selected storage unit may approach the electric current that even surpasses in selecteed storage unit, causes device failure.Storage system adds current-limiting apparatus can make the leakage current summation be no more than setting value, is unlikely to device failure.But now a lot of storage systems all do not add the scheme of upper flow, perhaps only add the current limit scheme when making device, perhaps with the current limit solution integration in device array.
Fig. 1 is the structural representation of prior art flash memory current limliting scheme.As shown in Figure 1,100 is memory cell array, 101 has been the PMOS transfer tube (MP) of metering function, wherein, the source of PMOS transfer tube (MP) 101 connects adjustable voltage VHB, its grid end is connected on a fixing voltage V0, and underlayer voltage meets VPP, and the drain terminal of PMOS transfer tube (MP) 101 is connected to the array source line 104 of memory cell array 100.Tradition current limliting scheme is by the voltage VHB on the change bit line, then comes the size of Limited Current for a suitable voltage V0.But the change of V0 can cause the floating of threshold voltage of PMOS transfer tube (MP), thereby makes current limliting can not accurately reach setting value.
Fig. 2 is that prior art is used current-limiting apparatus, comes the structural representation of the single storage unit in the operating flash memory array.As shown in Figure 2, flash memory device comprises memory cell array 100.Each storage unit typically contains source electrode, drain and gate.Array 100 more comprises multiple bit lines 102, BL0 for example, and BL1 ... BLm, and many word lines 103, word line WL0 for example, WL1 ... WLn.Bit line BL0-BLm is connected with bit line drive circuit 105, and word line WL0-WLn is connected with word line driving circuit 106, and high-pressure system 107 is bit line drive circuit 105, needed voltage when word line driving circuit 106 and current-limiting apparatus 108 provide memory cell operation.The voltage that high-pressure system 107 produces is connected to the power supply signal end of word line driving circuit and bit line drive circuit, and the voltage of selecting high-pressure system 107 to produce by word line and bit line is applied in one or more of bit line BL0-BLm.The source line 104 of storage array 100 links together, and current-limiting apparatus 108 is connected between array source line 104 and ground.
Fig. 3 is the schematic diagram of memory cell array 100 in Fig. 2.As shown in Figure 3, array 100 contains a plurality of storage unit 115 that are arranged in row and row.Word line WL0 wherein, WL1 ... the total n+1 of WLn one is capable, and bit line BL0, BL1 ... BLm has the m+1 row altogether.In storage unit, 115 and 116 separately drain electrodes are coupled in together, are connected to bit line BL0.The storage unit that connects other row with same method forms word line BL1-BLm, and wherein the source electrode of all storage unit links together.
In Fig. 3, unit 115 is the selected storage unit of doing sequencing.Apply higher biased to bit line BL0 and word line WL0, and apply low voltage to selected word line WL1-WLn with bit line BL1-BLm, operate selecteed unit 115.These bias voltages can be, for example, 10V, 5V, 0V, 0V is applied to respectively word line WL0, bit line BL0, WL1-WLn, BL1-BLm.As shown in Figure 3, transmit relevant voltage to word line driving circuit 106 and bit line drive circuit 105 by high-pressure system 107, then put on respectively word line WL0-WLn, bit line BL0-BLm by word line driving circuit 106 and bit line drive circuit 105.Under operator scheme, word line WL0 provides the control grid of voltage to selecteed unit 115, and is connected with WL0 but the grid of non-selected storage unit, with the storage unit 115 that promotes that electronic injection is selected.
For example 5V is biased into bit line BL0, and 10V is biased into word line WL0, as the required voltage of operating unit 115.Since the drain electrode of non-selected unit, all the drain electrode with selecteed unit 115 is connected, and those non-selected unit 116 also can be received the voltage of bit line BL0 in their drain electrodes separately.Put on the position voltage that non-selected storage unit 116 drains separately, increased draining to source voltage of each unit in non-selected storage unit 116, this drains can increase the leakage current of non-selected unit 116 to the value of source voltage.But according to described specific embodiment, current-limiting apparatus 108, size that just can this leakage current of current limliting.As shown in Figure 3, along with applying of drain-to-source voltage, each unit in non-selected storage unit 116 produces leakage current Ioff, and it flows into from drain electrode, and flows out from the source electrode of each non-selected storage unit 116.The summation of these Ioff electric currents, and the leakage current of the selecteed unit 115 of flowing through are together by array source line 104.Array source line 104 passes through current-limiting apparatus 108 again, thereby has limited the summation of leakage current, makes it be no more than desired preset value.
In realizing process of the present invention, the applicant recognizes that there is following defective in prior art: 1, the current-limiting apparatus of prior art is integrated in the middle of array, has taken a large amount of areas; 2, existing current-limiting apparatus is affected by the external conditions such as temperature, causes the current limliting out of true.
Summary of the invention
The technical matters that (one) will solve
For solving above-mentioned one or more problems, the invention provides a kind of flash memory current-limiting apparatus and use the flash memory of this device, with the area of conserve memory array, make current limliting can accurately reach setting value.
(2) technical scheme
According to an aspect of the present invention, provide a kind of flash memory current-limiting apparatus.This flash memory current-limiting apparatus is positioned at outside the memory cell array of flash memory, comprise: current limliting unit, transfer tube and reference current generation module, wherein, transfer tube is PMOS pipe (MP0), its grid end is connected to voltage control signal, drain terminal is connected to the needed voltage PHV of storage unit source erase operation in memory cell array, and source is connected to the source line in storage unit; The source of PMOS pipe (MP0) and the source line of storage unit are jointly as an input end of current limliting unit, and the reference current that the reference current generation module produces is as another input end of current limliting unit; If the electric current of storage unit source line does not surpass the reference current that the reference current generation module produces, current limliting unit cut-off; If the reference current that the electric current of the source line of storage unit produces greater than the reference current generation module, electric current arrives ground by the current limliting cell discharge.
According to another aspect of the present invention, also provide a kind of flash memory.This flash memory comprises storage unit and above-mentioned current-limiting apparatus, and wherein, storage unit contains source electrode, drain electrode and control grid; Each word line is the row in the corresponding stored unit respectively, and the grid of storage unit corresponds respectively to the row in this storage unit; Each bit lines is the delegation in the corresponding stored unit respectively, and the drain electrode of storage unit corresponds respectively to the delegation in this storage unit; The source electrode of each storage unit shares a source line, and this source line is connected with current limliting unit and transfer tube.
(3) beneficial effect
Flash memory current-limiting apparatus of the present invention and the flash memory of using this device have following beneficial effect:
(1) in the present invention, because current-limiting apparatus need not be integrated in the middle of array, therefore can save a large amount of chip areas;
(2) in the present invention, because current mirroring circuit is subjected to the impact of process conditions less, the electric current that the outside provides does not have much difference with electric current by the current mirror mirror image, make electric current and the outside electric current that provides in storage unit mutually can accurate comparison, thereby accurately limit leakage current be no more than some values.
Description of drawings
Fig. 1 is the structural representation of prior art flash memory current limliting scheme;
Fig. 2 is that prior art is used current-limiting apparatus, comes the structural representation of the single storage unit in the operating flash memory array;
Fig. 3 is the schematic diagram of memory cell array 100 in Fig. 2;
The schematic diagram of Fig. 4 embodiment of the present invention flash memory current-limiting apparatus;
The schematic diagram in time sequential routine during the non-current limliting of Fig. 5 embodiment of the present invention flash memory current-limiting apparatus;
The schematic diagram in time sequential routine when Fig. 6 is the current limliting of embodiment of the present invention flash memory current-limiting apparatus.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The invention provides a kind of flash memory current-limiting apparatus.This flash memory current-limiting apparatus comprises: transfer tube, reference current generation module and current limliting unit.Wherein, transfer tube is PMOS pipe (MP0), and its grid end connects a voltage control signal, and drain terminal is connected to the needed voltage PHV of storage unit source erase operation in memory cell array, and source is connected to the source line in storage unit in memory cell array; The source of PMOS pipe (MP0) and the source line of storage unit are jointly as an input end of current limliting unit, and the reference current that the reference current generation module produces is as another input end of current limliting unit; The output head grounding of current limliting unit, during the reference current that produces greater than the reference current generation module at the electric current of the source of storage unit line, electric current by current limliting unit vent discharge to ground; If when the electric current of the source of storage unit line surpasses the reference current of reference current generation module generation, current limliting unit cut-off.
The schematic diagram of Fig. 4 embodiment of the present invention flash memory current-limiting apparatus.As shown in Figure 4, current-limiting apparatus 108 contains current limiting transistor MN0-MN3 and PMOS transfer tube MP0, and wherein, the drain electrode of transistor MN2 is connected to array source line 104, and the drain electrode of transistor MN0 is connected to reference current generating circuit 110.The control grid of transistor MN0 and MN3 meets respectively control signal I_EN and Vbias.The source electrode of the drain electrode of transistor MN0 and transistor MN3 is connected with the grid of transistor MN1, MN2.The source electrode of transistor MP0 is connected to the drain electrode of source line 104 and the transistor MN2 of array, and grid meets control signal Vbias1, and drain electrode meets voltage PHV.Current-limiting apparatus 108 is used for limiting the summation of array source current in a preset value.Because the summation of source current is limited in a preset value, therefore reduced the design difficulty of external high pressure system.
In operating process, the signal controlling logic of current-limiting apparatus 108 as shown in Figure 5 when non-current limliting.At t0 constantly, control signal I_EN is connected on line 112, and control signal Vbias is connected on line 113, and control signal Vbias1 is that low level is connected on line 114, at t4 constantly, and finishing control.The voltage schematic diagram of VSL corresponding stored array source electrode 104 wherein, in t1 MP0 conducting constantly, PHV voltage is sent to storage array source electrode 104; In t4 MP0 cut-off constantly, voltage VSL becomes V1 at storage array source electrode 104.
In operating process, the signal controlling logic of current-limiting apparatus 108 as shown in Figure 6 when current limliting.At t0 constantly, the voltage of control signal I_EN is that supply voltage VCC is connected on line 112; The voltage of control signal Vbias is that supply voltage VCC is connected on line 113; The voltage of control signal Vbias1 is that high level PHV makes the MP0 cut-off, is connected to simultaneously on line 114.At t6 constantly, control signal I_EN, Vbias become the low level finishing control.The current diagram of ISL corresponding stored array source electrode 107 wherein, supposing increases at t3 constantly because certain operator scheme makes current IS L, when total leakage current surpasses Imax, due to current-limiting apparatus 108, make current IS L pass through the MN2 tube discharge to ground, thereby current IS L is dropped to below electric current preset value Imax constantly at t4.When supposing leakage current ISL total under certain operator scheme not greater than pre-market value Imax, at this moment the MN2 in current-limiting apparatus 108 can not make current IS L pass through the MN2 tube discharge to ground.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (7)
1. a flash memory current-limiting apparatus, is characterized in that, this flash memory current-limiting apparatus is positioned at outside the memory cell array of flash memory, comprising: transfer tube, reference current generation module and current limliting unit, wherein,
Described transfer tube is PMOS pipe (MP0), and its grid end is connected to voltage control signal, and drain terminal is connected to the needed voltage PHV of storage unit source erase operation in memory cell array, and source is connected to the source line in described storage unit;
The source of described PMOS pipe (MP0) and the source line of described storage unit are jointly as an input end of described current limliting unit, and the reference current that the reference current generation module produces is as another input end of described current limliting unit;
The output head grounding of described current limliting unit, if the electric current of described storage unit source line surpasses the reference current that described reference current generation module produces, current limliting unit cut-off; If the reference current that the electric current of the source line of described storage unit produces greater than described reference current generation module, electric current arrives ground by described current limliting cell discharge.
2. flash memory current-limiting apparatus according to claim 1, is characterized in that, described reference current generation module produces reference current by current mirror mirror image foreign current.
3. flash memory current-limiting apparatus according to claim 1, it is characterized in that, described current limliting unit comprises a NMOS pipe (MN0), the 2nd NMOS pipe (MN1), the 3rd NMOS pipe (MN2) and the 4th NMOS pipe (MN3), wherein:
The drain electrode of the one NMOS pipe (MN0) is connected to the reference current that the reference current generation module produces, and controls grid and meets the first control signal I_EN, and source electrode is received the drain electrode of the 2nd NMOS pipe (MN1);
The 2nd NMOS pipe (MN1) and the 3rd NMOS pipe (MN2) form a current mirroring circuit, the gate interconnection of the grid of the 2nd NMOS pipe (MN1) and the 3rd NMOS pipe (MN2), and be connected with the source electrode of a NMOS pipe (MN0);
The drain electrode of the 3rd NMOS pipe (MN2) is connected to source in storage unit and the source electrode of PMOS transfer tube (MP0), and the grid of the 3rd NMOS pipe (MN2) and the 2nd NMOS manage the gate interconnection of (MN1), source ground;
The drain terminal of the 4th NMOS pipe (MN3) is connected to the grid of the 3rd NMOS pipe (MN2) and the 2nd NMOS pipe (MN1); Its source ground, it is controlled grid and meets the second control signal Vbias;
The control grid of described PMOS pipe (MP0) meets the 3rd control signal Vbias1, and source electrode connects high voltage P HV, and the source line of memory cell array is received in drain electrode;
If the electric current of described storage unit source line does not surpass the reference current that described reference current generation module produces, the 3rd NMOS pipe (MN2) cut-off; If the reference current that the electric current of the source line of described storage unit produces greater than described reference current generation module, electric current is managed (MN2) by the 3rd NMOS and is discharged into ground.
4. flash memory current-limiting apparatus according to claim 3, is characterized in that, when the source line to described storage unit carries out the current limliting operation,
Described the first control signal I_EN is connected to supply voltage; Described the second control signal Vbias is connected to ground level; Described the 3rd control signal Vbias1 is connected to high voltage P HV, makes PMOS transfer tube (MP0) cut-off.
5. flash memory current-limiting apparatus according to claim 3, is characterized in that, when the source line of described storage unit not being carried out the current limliting operation,
Described the first control signal I_EN is connected to ground voltage; Described the second control signal Vbias is connected to supply voltage; Described the 3rd control signal Vbias1 is connected to ground level, makes PMOS transfer tube (MP0) conducting.
6. flash memory current-limiting apparatus according to claim 3, is characterized in that,
When carrying out erase operation, the 4th NMOS pipe (MN3) conducting, the 3rd NMOS pipe (MN2) cut-off is by the source of NMOS pipe (MN0) transmission PHV voltage to storage unit;
When programme, during read operation, the 4th NMOS pipe (MN3) cut-off, the 3rd NMOS pipe (MN2) conducting, when total leakage current surpassed preset value, electric current manage (MN2) through the 3rd NMOS and is flowed to ground.
7. a flash memory, is characterized in that, comprises the described current-limiting apparatus of any one in storage unit and claim 1 to 6,
Storage unit contains source electrode, drain electrode and control grid;
Each word line is the row in the corresponding stored unit respectively, and the grid of storage unit corresponds respectively to the row in this storage unit;
Each bit lines is the delegation in the corresponding stored unit respectively, and the drain electrode of storage unit corresponds respectively to the delegation in this storage unit;
The source electrode of each storage unit shares a source line, and this source line is connected with described current limliting unit and transfer tube.
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| CN2011103437399A CN103093811A (en) | 2011-11-03 | 2011-11-03 | Flash memory current-limiting device and flash memory with the flash memory current-limiting device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104952478A (en) * | 2014-03-25 | 2015-09-30 | 三星电子株式会社 | Nonvolatile memory device and storage device with nonvolatile memory device |
| CN106169302A (en) * | 2015-05-18 | 2016-11-30 | 三星电子株式会社 | Storage arrangement and the electronic installation including this storage arrangement |
| CN112133347A (en) * | 2020-09-11 | 2020-12-25 | 中国科学院微电子研究所 | Storage unit based on 7T1C structure, operation method thereof and memory |
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| CN1897160A (en) * | 2005-07-15 | 2007-01-17 | 旺宏电子股份有限公司 | Semiconductor device including memory cells and current limiter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104952478A (en) * | 2014-03-25 | 2015-09-30 | 三星电子株式会社 | Nonvolatile memory device and storage device with nonvolatile memory device |
| CN104952478B (en) * | 2014-03-25 | 2019-04-02 | 三星电子株式会社 | Nonvolatile memory and storage device with the nonvolatile memory |
| CN106169302A (en) * | 2015-05-18 | 2016-11-30 | 三星电子株式会社 | Storage arrangement and the electronic installation including this storage arrangement |
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| CN112133347A (en) * | 2020-09-11 | 2020-12-25 | 中国科学院微电子研究所 | Storage unit based on 7T1C structure, operation method thereof and memory |
| CN112133347B (en) * | 2020-09-11 | 2023-08-15 | 中国科学院微电子研究所 | Memory unit based on 7T1C structure, operation method thereof and memory |
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Application publication date: 20130508 |