JP5308721B2 - Level shift circuit - Google Patents

Description

  The present invention relates to a level shift circuit that switches an input signal to a high voltage and outputs it.

  Conventionally, flash memories have become widespread. Data erasing (erasing) in the flash memory is realized by applying a high voltage HV to the word line (WL) and extracting electrons held in the floating gate (FG) of the memory.

  For this reason, when erasing data, it is necessary to apply a high voltage HV to the word line, which requires a level shift circuit.

  Here, when the word line is selected according to the address, the corresponding voltage is set, and when the word line is not selected, the word line is set to the negative power supply voltage Vss. Therefore, when erasing data, the selected word line is set to the high voltage HV and the unselected word line is set to Vss. Therefore, the level shift circuit needs to switch its output to HV or Vss. For this purpose, the level shift circuit normally arranges a p-type transistor and an n-type transistor in series between HV and Vss and sets the intermediate point as an output end, turns on the p-type transistor and outputs HV from the output end, The n-type transistor is turned on and Vss is output from the output terminal.

  Therefore, in the level shift circuit, when the p-type transistor is turned off, a voltage of HV-Vss is applied between the source and drain of the p-type transistor.

JP 11-328985 A

  Here, in semiconductor devices such as LSIs, miniaturization is progressing, and it is difficult to reduce the cut current when the p-type transistor is off. On the other hand, HV is generated by a charge pump circuit or the like in an LSI, but there is a problem that the area becomes large in order to increase the current capability of the charge pump circuit.

  On the other hand, if the HV is reduced, the cut current can be reduced accordingly. However, since the data erasure of the flash memory becomes inefficient, there is a demand for increasing the HV as much as possible.

The present invention relates to a switch for switching and outputting either a high-level positive power supply voltage HV or a normal positive power supply voltage Vcc, first and second p-type transistors receiving an output from the switch at one end, and first and second p-type ends at one end First and second n-type transistors connected to the other end of the p-type transistor and supplied with the variable negative power supply voltage ZVss at the other end. The other end of the first p-type transistor is connected to the control end of the second p-type transistor. The other end of the second p-type transistor is connected to the control end of the first p-type transistor, and the variable negative power supply voltage ZVss is determined by the normal negative power supply voltage Vss and the first n-type transistor being sufficiently on. It is possible to change to a relaxed negative power supply voltage α that is higher than the normal negative power supply voltage Vss within a range that can be maintained. One end of the 2p-type transistor in a state of normally supplying a positive power supply voltage Vcc, supplied to the normal negative power supply voltage Vss to the control terminal of the 2n-type transistor supplying the normal positive supply voltage Vcc to the control terminal of the 1n-type transistor Thus, the normal power supply voltage Vcc is output from the connection portion of the second p-type transistor and the second n-type transistor, and then the high-level positive power supply voltage HV is supplied to one end of the first and second p-type transistors by the switch. in the variable negative by a 2p-type transistor and outputs a high level positive supply voltage H V from the connecting portion of the 2n transistors, sometimes it outputs the high level positive supply voltage HV, the negative power supply voltage changing means The power supply voltage ZVss is set to a relaxed negative power supply voltage α .

  Preferably, a third n-type transistor is provided between the first n-type transistor and the first p-type transistor, and a fourth n-type transistor is provided between the second n-type transistor and the second p-type transistor.

  According to the present invention, when the high-level positive power supply voltage HV is output, the variable negative power supply voltage ZVss is set higher than the negative power supply voltage Vss within a range in which the first n-type transistor can be sufficiently turned on. Therefore, the voltage on the lower side of the first p-type transistor is increased, the voltage applied to the first p-type transistor that is turned off can be reduced, and the cut current flowing therethrough can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows the configuration of the level shift circuit according to the embodiment. Upper power supply line 10 is connected to either high voltage HV or power supply voltage Vcc via switch 12. That is, the upper power supply line 10 is connected to HV at the time of data erasing (erasing) and to Vcc at a normal time such as at the time of reading. Note that HV is an output of a charge pump circuit provided in the same LSI.

  The p-type transistor 14 has a source connected to the upper power supply line 10 and a drain connected to the drain of the n-type transistor 16. The source of the n-type transistor 16 is connected to the drain of the n-type transistor 18, and the source of the n-type transistor 18 is connected to the lower power supply line ZVss.

  Similarly, the p-type transistor 20 has a source connected to the upper power supply line 10 and a drain connected to the drain of the n-type transistor 22. The source of the n-type transistor 22 is connected to the drain of the n-type transistor 24, and the source of the n-type transistor 24 is connected to the lower power supply line ZVss.

  The gate of the p-type transistor 14 is connected to the drain of the p-type transistor 20, and the gate of the p-type transistor 20 is connected to the drain of the p-type transistor 14. Since the gates of the n-type transistors 16 and 22 are connected to the power supply Vcc, both the transistors 16 and 22 are always on. The input IN is input to the gate of the n-type transistor 18, and the input IN is inverted by the inverter 26 and input to the gate of the n-type transistor 24. A connection point between the p-type transistor 20 and the n-type transistor 22 serves as an output terminal, from which an output OUT is output.

The output of the address decoder is supplied to the input IN, and the H level (Vcc) is supplied when the word line is selected, and the L level (Vss = 0 V) is supplied when the word line is not selected. In this embodiment, the voltage of the lower power supply line ZVss is variable. That is, ZVss can be changed from Vss = 0V to αV. Vss = 0V is normally called a negative power supply voltage, and Vss = αV is called a relaxed negative power supply voltage.

  As shown in the figure, the substrate potential of the p-type transistor is Vcc, and the substrate potential of the n-type transistor is Vss.

  The erase operation of such an embodiment will be described with reference to FIG. First, in a state where erasing is not performed, the signal ERASE is at L level, and the upper power supply line 10 is at Vcc. Further, IN is at the L level, and ZVss = Vss. In this state, the n-type transistor 18 is off, the n-type transistor 24 is on, the p-type transistor 14 is on, and the p-type transistor 20 is off. Therefore, the output OUT is Vss.

  The input IN changes from Vss to Vcc according to the output of the address decoder. As a result, the n-type transistor 18 is turned on, the gate of the p-type transistor 20 becomes Vss, and the p-type transistor 20 is turned on. On the other hand, the n-type transistor 24 is turned off because the input IN is supplied to its gate via the inverter 26. At this stage, Vcc is supplied to the upper power supply line 10, and therefore the output OUT becomes Vcc. Note that the p-type transistor 14 is off because Vcc is supplied to the gate.

  Next, when the signal ERASE becomes H level (for example, Vcc), the switch 12 selects HV. As a result, the voltage of the upper power supply line 10 rises to HV (12 V), and the output OUT rises to HV accordingly.

  After such a voltage change, in this embodiment, ZVss increases from Vss to αV. As a result, the source potential of the n-type transistor 18 changes from Vss to αV. However, this αV is set to a voltage at which the n-type transistor 18 is substantially fully on. Therefore, the n-type transistor 18 remains fully on, and the drain voltage of the p-type transistor 14 becomes αV. Therefore, the source-drain voltage of the p-type transistor 14 is HV−αV, which is decreased by αV. For example, when Vcc = 3V, α = 1V, HV = 12V, and Vss = 0V, the source-drain voltage of the p-type transistor 14 is only 12V, but the cut current is predetermined. If the predetermined voltage is 11 V, it can be greatly reduced. Also, if the predetermined voltage is 12V, HV can be set to 13V, thereby increasing the erase efficiency.

  When a predetermined erase time has elapsed, the signal ERASE is returned to the L level (Vss) by the timer, whereby HV = Vcc and OUT = Vcc. Further, when this ERASE receives the L level, the input IN = Vss and ZVss = Vss. Therefore, the n-type transistor 18 is off, the n-type transistor 24 is on, the p-type transistor 14 is on, the p-type transistor 20 is off, and the output OUT = Vss.

  As described above, according to the present embodiment, ZVss becomes αV during the HV output period, and the source-drain voltage αV of the p-type transistor 14 is reduced, so that the cut current can be reduced. As shown in FIG. 2, ZVss becomes α after the output becomes HV. However, since the period during which HV is applied to the p-type transistor 14 is short, the increase in the cut current during that period is This amount is almost negligible compared to the cut current for the entire erase period.

  In order to turn on the n-type transistor 18, the gate-source voltage needs to be equal to or higher than the threshold voltage. Therefore, when the gate voltage is Vcc = 3V and the threshold voltage is 0.7V, the source voltage ZVss needs to be 2.3V or less. Here, the n-type transistor 18 needs to be substantially fully turned on. In practice, it is preferable that α = 1V or so.

  In this embodiment, n-type transistors 16 and 22 are provided. Although these n-type transistors 16 and 18 are always on, the voltage between the source and the drain when the n-type transistors 16 and 22 are off is relaxed by these voltage drops. In the present embodiment, by setting ZVss to αV, the source-drain voltage of the n-type transistors 16 and 22 can be further relaxed. Furthermore, the effect of relaxing the voltage between the gate and the substrate can be obtained by using ZVss. The lifetime of the transistor is limited by the lifetime of the gate oxide film. It is known that the lifetime of the gate oxide film is caused by a potential difference between the gate voltage and the substrate as a temporal breakdown (TDDB) of the insulating film. By reducing this potential difference, the lifetime of the transistor can be extended. In the present embodiment, by increasing the gate potential of the p-type (p-channel) transistor from Vss to α by the potential of ZVss, the potential difference between the gate and the substrate for α can be relaxed, and the lifetime of the transistor can be extended. There is.

  The n-type transistors 16 and 22 can be omitted, or can be two or more.

  FIG. 3 shows another embodiment. In this example, a p-type transistor 30 is provided.

  That is, the drain of the p-type transistor 30 whose source is connected to Vcc is connected to the drain of the n-type transistor 18 whose input IN is input to the gate. The input IN is also input to the gate of the p-type transistor 30, and the connection point between the p-type transistor 30 and the n-type transistor 18 is connected to the source of the n-type transistor 16. The source of the n-type transistor 18 and the source of the n-type transistor 24 are connected to ZVss.

  The input IN is inverted by the inverter 26 and supplied to the gate of the n-type transistor 24. Therefore, the logic itself is basically the same as in FIG.

  That is, when erasing is performed, the input IN becomes H level, the n-type transistor 18 is turned on, and the p-type transistor 30 is turned off. Since the n-type transistor 18 is turned on, the p-type transistor 20 is turned on, the p-type transistor 14 is turned off, and the output is HV. Further, the n-type transistor 18 is on and the n-type transistor 24 is off.

  As ZVss increases to αV, the drain voltage of the p-type transistor 14 increases by αV via the n-type transistor 18 and the n-type transistor 16, and the source-drain voltage of the p-type transistor 14 decreases. Is done.

  Here, FIG. 4 shows a configuration for controlling the potential of ZVss. The other end of the resistor R having one end connected to Vcc is connected to the cathode of the Zener diode D, and the anode of the Zener diode D is connected to Vss. As a result, a voltage α determined by the breakdown voltage of the Zener diode D is obtained at the connection portion between the cathode of the Zener diode D and the resistor R.

  A connection portion between the cathode of the Zener diode D and the resistor R is connected to ZVss through the n-type transistor 40, and ZVss is also connected to Vss by the n-type transistor 42. A ZVss_ON signal is supplied to the gates of the n-type transistors 40 and 42, and ZVss_ON is inverted and supplied to the gate of the n-type transistor 42 by the inverter 44.

  Therefore, when the signal ZVss is at L level, ZVss = Vss. When ZVss is at H level, ZVss = α. In this manner, ZVss_ON can be changed from Vss to α by setting ZVss_ON to the H level at an appropriate timing.

It is a figure which shows the structure of embodiment. It is a timing chart explaining operation. It is a figure which shows the structure of other embodiment. It is a figure which shows the structure for control of ZVss.

Explanation of symbols

  10 upper power line, 12 switches, 14, 20, 30 p-type transistors, 16, 18, 22, 24, 40, 42 n-type transistors, 26, 44 inverters.

Claims (2)

A switch for switching and outputting either the high-level positive power supply voltage HV or the normal positive power supply voltage Vcc;
First and second p-type transistors receiving an output from the switch at one end;
First and second n-type transistors each having one end connected to the other ends of the first and second p-type transistors and the other end supplied with a variable negative power supply voltage ZVss;
Including
The other end of the 1p-type transistor is connected to the control terminal of the 2p-type transistor, the other end of the 2p-type transistor is connected to a control terminal of the 1p-type transistor,
The variable negative power supply voltage ZVss can be changed to a normal negative power supply voltage Vss and a relaxed negative power supply voltage α higher than the normal negative power supply voltage Vss within a range in which the first n-type transistor can be kept in a sufficiently on state. ,
While the normal positive power supply voltage Vcc is supplied to one end of the first and second p-type transistors by the switch, the normal positive power supply voltage Vcc is supplied to the control end of the first n-type transistor and the control end of the second n-type transistor is supplied . By supplying the normal negative power supply voltage Vss to the normal power supply voltage Vcc from the connection portion of the second p-type transistor and the second n-type transistor,
Subsequent said switch, by supplying the high-level positive supply voltage HV to one end of the first and second 2p-type transistor, and outputs a high level positive supply voltage H V from the 2p-type transistor and the connection portions of the 2n transistors ,
Sometimes and outputs the high level positive supply voltage HV, the level shift circuit, characterized in that said variable negative supply voltage ZVss mitigation negative supply voltage α by the negative power supply voltage changing means. The level shift circuit according to claim 1,
3. A level shift circuit, wherein a third n-type transistor is provided between the first n-type transistor and the first p-type transistor, and a fourth n-type transistor is provided between the second n-type transistor and the second p-type transistor.

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