KR100560769B1 - High voltage switch pump circuit - Google Patents

Abstract

A word line connected to a unit cell of a memory block, the high voltage switching pump circuit for pumping and delivering a high voltage according to an operation mode provided by a high voltage generation circuit, receives a memory block selection signal B_sel and a clock signal CLK to receive a clock. Connected to the output of the first pumping circuit and the first pumping circuit for raising the output level to a first level higher than the power supply voltage level in accordance with the transition of the logic level of the signal CLK, but using a capacitor coupling than the first level. And a second pumping circuit consisting of a MOS transistor for generating a high second level of high voltage.

High Voltage, Word Line, Pump Pump, Coupling Ratio, Capacitor, Clock Signal

Description

High voltage switch pump circuit

1 shows a high voltage pumping circuit used in a typical flash EEPROM device.

2 shows an example of a high voltage pumping circuit according to the present invention.

3 is a timing diagram and an output level of a control signal of the high voltage pumping circuit of FIG. 2.

The present invention relates to a nonvolatile memory device, and more particularly, to a high voltage pumping circuit for supplying a voltage suitable for a program / erase / read operation to a word line connected to a cell of the nonvolatile memory device.

Generally, semiconductor memory devices are classified into volatile memory devices in which stored information is lost when power supply is interrupted, and nonvolatile memory devices in which information is continuously maintained even when power supply is interrupted. Nonvolatile memory devices include erasable programmable read only memory (EPROM), electrically EPROM (EPEPROM), and flash EEPROM (Flash EEPROM), among which the advantages of EPROM can reduce the cell area and the electrical power of stored information. With all the advantages of EEPROM, which can be erased, the demand for flash EEPROM is increasing.

  Flash EEPROM devices are classified into NAND-type flash EEPROM devices and NOR-type flash EEPROM devices according to the arrangement of unit cells. Such flash EEPROM devices include a cell array consisting of a plurality of memory blocks, a row selection circuit, and a sensing and latching circuit. It includes. The memory block includes a plurality of unit cells connected to the bit line and the word line. However, in order to program information to, remove information from, or read information from such memory cells, a corresponding voltage, for example, a programming voltage, an erase voltage, or a read voltage, must be transferred through a row selection circuit to a word line connected to a selected unit cell. do. However, since these voltages are higher voltages than the power supply voltage, the row selection circuit requires a circuit device for switching the high voltage in order to supply the high voltage higher than the power supply voltage to the word line. As an example of such a circuit, a switch pump scheme is employed. Some used.

An example of a high voltage switching device using a switch pump scheme is shown in FIG. Referring to FIG. 1, the high voltage switching device includes an NMOS transistor M1 for precharging a node Sel, and a positive feedback loop 2 for increasing a voltage level of the node Sel according to a clock signal CLK. NMOS transistors M2 and M3, one capacitor C1, and a pass NMOS transistor M4 for connecting the high voltage of the node Sel switched to a predetermined level to the selected word line. The transistor M2 is composed of a native NMOS transistor to transfer voltage loss to Vpp, and Vpp means a program voltage in a program mode, an erase voltage in an erase mode, and a read voltage in a read mode. Hereinafter, the program mode will be described as an example. In this case, Vpp means a program voltage Vpgm.

When the memory block selection signal B_sel becomes a logic " high " and the power supply voltage Vcc is applied, the node sel is charged to VCC-Vt (M1) through the transistor M1. The gate of the transistor M3 is connected to the node sel and is turned on. The Vpp supplied from the high voltage generator (not shown) is transferred to the node A through the transistor M3 so that the node A is referred to as Vcc-Vt (M1) -Vt (M3) (this is called a precharge voltage Vprecharge). .) Here, Vt (M1), Vt (M2), and Vt (M3) represent threshold voltages of the transistors M1, M2, and M3, and the memory block selection signal B_sel is logic " high during programming operations. Is a control signal.

If the clock signal CLK transitions from a logic "high" to a logic "low" during a programming operation, the output of the NAND gate 11 changes from a logic "low" to a logic "high" and thus charges the capacitor C1. do. Therefore, the voltage level of the node A is increased. At this time, if the threshold voltage Vt (M2) of the transistor M2 is smaller than the voltage difference between the node A and the node sel, the charge of the node A is transferred to the node sel through the transistor M2. Thus, the voltage level of the node sel is increased. The rising voltage of the node sel gates the transistor M3 to a higher voltage so that the voltage level of the node A further rises. If the voltage rise process is repeated such that the voltage of the node sel is equal to or more than the sum of the program voltage and the threshold voltage of the pass transistor M4, the pass transistor M4 having the gate connected to the node Vsel is turned on, and Vpp is turned on. Is supplied to the selected word line.

As can be seen from the above description, the voltage level of the node Vsel is influenced by the power supply voltage Vcc, the threshold voltage of the transistor M2 and the threshold voltage of the transistor M3. That is, since the high voltage switching efficiency depends on Vcc-Vt (M2) -Vt (M3), in order to form a positive feedback circuit for voltage pumping, it must be Vcc> Vt (M2) + Vt (M3).

Therefore, the above-described high voltage pumping circuit has a problem that is not suitable for a flash EEPROM device using a low power supply voltage (for example, 3V, 2,65V, 18V or less depending on the capacity of the memory device, etc.). In addition, due to the body effect, the threshold voltages of the NMOS transistors M1, M2, M3, and M4 increase, resulting in a loss of Vpp delivered to the word line.

Accordingly, an object of the present invention is to provide a high voltage switching circuit of a nonvolatile memory device capable of delivering a program / erase / read voltage to a selected word line without loss while using a low power supply voltage.

In order to achieve the above object, a high voltage pumping circuit for pumping and delivering a first high voltage according to an operation mode provided by a high voltage generating circuit to a word line connected to a plurality of cells of a memory cell array, the control signal indicating that the program operation And an output level connected to a clock signal and a first high voltage of the high voltage generation circuit, by performing voltage pumping according to a logic level transition of the clock signal when a control signal indicating that the program operation of a power supply voltage level is enabled is enabled. A first pumping circuit for pumping a to a voltage having a first level above the power supply voltage level; And a second high voltage connected to an output terminal of the first pumping circuit and having the same level as the first high voltage of the high voltage generating circuit and being shifted by a predetermined interval after applying the voltage of the first high voltage. And a second pumping circuit for outputting a voltage at a level higher than the voltage of. Here, the second pumping circuit is coupled to the output terminal of the first pumping circuit in the rising period of the second high voltage to charge the charge by the second high voltage to increase the voltage level of the output terminal of the first pumping circuit, When the second high voltage rises, the MOS transistor transfers the output voltage of the first pumping circuit which is raised to the output terminal of the second pumping circuit.

 And a third pumping circuit connected to an output terminal of the second pumping circuit, the third pumping circuit having the same level as the first high voltage and receiving a third high voltage shifted by a predetermined interval after the application of the second high voltage. The third pumping circuit is coupled to the output terminal of the second pumping circuit in the rising period of the third high voltage to charge the charge by the third high voltage to increase the voltage level of the output terminal of the second pumping circuit, When the third high voltage rises, the MOS transistor transfers the output voltage of the level-up second pumping circuit to the output terminal of the third pumping circuit.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 illustrates an example of a high voltage pumping circuit according to an exemplary embodiment of the present invention, and FIG. 3 illustrates a timing diagram and an output level of a control signal of the high voltage switching circuit of FIG. 2. The same reference numerals are used for the same parts as the elements of FIG.

The high voltage pumping circuit according to an embodiment of the present invention receives a memory block selection signal B_sel and a clock signal CLK that are logic "high" of a power supply voltage level indicating that a program operation is performed, and thus a logic level of the clock signal CLK. Connected to an output of the first pumping circuit 10 and the first pumping circuit 10 for raising the output level to a first level higher than the power supply voltage level according to the transition of the first level using a capacitor coupling. And a second pumping circuit 20 for generating a high second level of high voltage. The high voltage pumping circuit further includes stabilization circuits 30 and 40 for maintaining an appropriate level, such as suppressing excessive rise of the first and second levels.

The first pumping circuit 10 includes an input stage, an output stage, and a precharging unit for precharging an output stage and a pumping unit connected in a cascade form so that the input stage and the output stage form a positive feedback loop. An input terminal is connected to an output terminal of the NAND gate 11 and the NAND 11 that receives a memory block selection signal B_sel and a clock signal CLK and outputs an operation result reflecting a transition of a clock signal during a program operation. And a capacitor C1 representing a potential level that varies with the clock signal transition, and the precharging unit connects the NMOS transistor M1 connected between the memory block select signal line B_sel and the output terminal Node. Include. The pumping unit includes two NMOS transistors M2 and M3. The output terminal of the first NMOS transistor M2 is connected to the gate of the second NMOS transistor M3 at the node Sel, and the second NMOS transistor M3. Is connected to the gate of the first NMOS transistor M2 at node A. The first NMOS transistor M2 forms a source-drain path between the input terminal (node A) and the output terminal (node Selp), and the second NMOS transistor M3 forms a source-drain between the high voltage and the input terminal (node A). It is intended to form a passage.

On the other hand, the first pumping circuit 10 has been described by way of example substantially the same as the high voltage pumping circuit of Figure 1 for convenience of description. However, the first pumping circuit 10 used in the high voltage pumping circuit according to the present invention is not limited thereto, and the capacitor C1 and the two capacitors C1 and the output terminal are configured within the range in which the input terminal and the output terminal form a positive feedback loop as described above. Various circuits in which the connection relationship between the NMOS transistors M2 and M3 are modified can also be used.

The second pumping circuit 20 performs the voltage pumping including the gate-capacitor. Specifically, the second pumping circuit 20 performs the voltage pumping process in two steps. Here, the gate-capacitor means a semiconductor device that operates as a capacitor in the rising period of the applied high voltage, and acts as a fast transistor when the rising is completed, and transfers the charged charge in the high voltage rising period. In this embodiment, one NMOS transistor M6 and M8 implements a semiconductor device of a gate capacitor, and one voltage pumping process is performed through each NMOS transistor. In this embodiment, one NMOS transistor is used as the gate-capacitor. However, the configuration of the second pumping circuit is not limited thereto, and various semiconductor devices or logics satisfying the above-described operating conditions may be used.

Specifically, the gate of the NMOS transistor M6 receives the voltage of the node Sel, which is the output terminal of the first pumping circuit 10, and the source has the same voltage level as Vpp, which is the output of the high voltage generator 12, but Vpp. After a predetermined time has elapsed after the rising point of the logic is "high" is connected to Vpp2, the drain is connected to the node (selp) representing the primary pumping result of the second pumping circuit. Here, Vpp2 is provided from the output terminal of the first shift unit 13 connected to the output terminal of the high voltage generator 12, and a specific configuration of the first shift unit 13 may be known.

The gate of the NMOS transistor M8 is connected to the node Selp indicating the first pumping result, and the source of the NMOS transistor M8 has the same voltage level as that of Vpp or Vpp2, but after a rising time of Vpp2. After this elapses, it is connected to Vpp3, which rises to logic " high ", and the drain is connected to the output Vout of the high voltage pumping circuit connected to the word line. Similarly, Vpp3 is provided from the second shift part 14 connected to the output end of the first shift part 13 connected to the output end of the high voltage generator 12, and the specific configuration of the second shift part 14 is known. Can be used.

The stabilization circuits 30 and 40 have a gate connected to the node Sel to suppress an excessive increase in the voltage level (first level) of the node Sel, and a source-drain path is provided between the node Sel and Vpp. A gate is connected to the node Selp and the source-drain path is connected between the node Selp and Vpp to suppress an excessive increase in the NMOS transistor M5 and the voltage level (second level) of the node Selp. It includes an NMOS transistor (M4) to form a. The NMOS transistor M4 also serves as a pumping element for raising the voltage level of the node Selp by Vpp3 and also serves as a pass transistor for supplying the pumping voltage raised to a predetermined level to the word line. Meanwhile, the non-described NMOS transistor M7 represents a selection state of the memory block, and forms a source-drain path between the node Selp and the memory block selection signal B Sel line and applies a Vcc voltage to the gate. It is.

 Referring now to Figures 2 and 3, look at the operation of the high voltage pumping circuit according to the present invention.

First, when the memory block selection signal B_sel becomes a logic " high " of Vcc, the voltage of the node Sel which is an output terminal of the first pumping circuit 10 becomes Vcc-Vt (M1) through the NMOS transistor M1. . The NMOS transistor M3 having the gate connected to the node Sel is turned on to supply charge from the Vpp voltage, and the voltage level of the node A is precharged to Vsel-Vt (M3).

In this state, when the clock signal CLK changes from a logic "high" to a "low", the output of the NAND gate 11 transitions from a logic "low" to "high", and the capacitor C1 is charged with a charge so that the node A ) Will rise. At this time, when the threshold voltage of the NMOS transistor M2 is smaller than the voltage difference between the node A which is the input terminal of the first pumping circuit 10 and the node Sel which is the output terminal, the charge is transferred from the node A to the node Sel. As a result, the voltage level Vsel of the node Sel increases. Since the voltage Vsel of the node Sel, which has been raised, is applied to the gate of the NMOS transistor M3, the voltage of the node A is raised to a higher level. In other words, the node Sel, the NMOS transistor M3, the node A, and the NMOS transistor M2 form a positive feedback loop. When the clock signal CLK transitions from logic "low" to logic "high", the elevated voltage of the node Sel is applied to the gate of the NMOS transistor M6, and the NMOS transistor M3 is turned off. The voltage of the node Sel is increased by the repetition of the "high-low" transition and the "low-high" transition of the aforementioned clock signal.

When the voltage level of the node Sel is excessively exceeded Vpp by the above-described process, the charge is transferred from the node Sel to Vpp through the NMOS transistor M5 of the stabilization circuit, and thus the voltage level of the node SelP. Lowers stably. The voltage of the node Sel by the first pumping circuit 10 in which the positive feedback loop is formed is indicated by " I " in the lower graph representing Vout.

Next, the voltage of the node Sel raised by the first pumping circuit 10 is input to the subsequent second pumping circuit 20 and pumped again by.

In detail, Vpp2 is grounded while the voltage level of the node Sel reaches a predetermined level, and starts to rise after reaching the predetermined level. That is, in the NMOS transistor M6, the NMOS transistor M6 is the one electrode of the capacitor until the voltage difference of the gate due to the source caused by Vpp2 and the voltage level of the node Sel is greater than the threshold voltage of the NMOS transistor M6. Will only work. Therefore, during this period, the potential of the node Sel connected to the gate of the NMOS transistor M6 rises as follows.

Vsel (n) = a * Vsel (n-1)

Here, a denotes the coupling ratio at the node sel by the NMOS transistor M6, and Vsel (n-1) is before Vpp2 and the NMOS transistor M6 are affected, that is, Vpp2 is in the ground state. It is the voltage of the node Sel, and Vsel (n) represents the voltage of the node Sel after being influenced by Vpp2 and the NMOS transistor M6. When Vpp2 is completed, the NMOS transistor M6 is turned on and the voltage level of the node Sel thus raised is the node which is the primary pumping output terminal of the second pumping circuit 20 without losing the threshold voltage of the NMOS transistor M6. Will be passed to (Selp). That is, when the rising of Vpp2 is completed, the NMOS transistor M6 operates as a fast transistor. The voltage rise of the node Selp at this time is indicated by " II " in the lower graph showing Vout of FIG.

Depending on the level of Vpp required in the flash EEPROM device, the node (Selp) can be directly connected to the word line. If higher Vpp is required, the pumping operation by capacitor coupling is further performed as shown in FIG. You can do that.

That is, the NMOS transistor M8 having a gate connected to the node Selp is driven by Vpp3, which is grounded while the voltage level of the node Selp reaches a predetermined level and is applied and starts to rise after reaching the predetermined level. Until the voltage difference between Vpp3 and the node Selp becomes greater than the threshold voltage of the NMOS transistor M8, the capacitor operates as a capacitor and the charge caused by Vpp3 increases the voltage of the node Selp. That is, the potential of the node Selp connected to the gate of the NMOS transistor M8 rises to Vselp (n) = a '* Vselp (n-1).

Here, a 'denotes a coupling ratio at the node selp by the NMOS transistor M8, and Vselp (n-1) is a voltage of the node Selp before being affected by Vpp3 and the NMOS transistor M8. Vselp (n) represents the voltage of the node Selp after being influenced by Vpp3 and the NMOS transistor M8. When the rising of Vpp3 is completed, the NMOS transistor M8 operates as a fast transistor so that the elevated voltage level of the node Selp is transferred to the output terminal Vout without losing the threshold voltage of the NMOS transistor M8. The voltage increase at this time is indicated by "III" in the lower graph indicating Vout.

Similarly, if the voltage level of Vout does not reach the high voltage level delivered to the word line, it will receive Vout as a gate and have the same voltage level as Vpp, but will rise to logic "high" after a certain period of time after the rise of Vpp3. An additional NMOS transistor with a source connected to Vpp4 can also be used to obtain a higher voltage.

On the other hand, since the pumping by the second pumping circuit 20 is not affected by the memory block selection signal B_sel and the clock signal CLK, the memory block selection signal B_sel is dis- played in the operation period of the second pumping circuit. It is also possible that there is no enable or transition of the clock signal CLK. However, the memory block selection signal B_sel connected to the NMOS transistor M2 indicating the memory block selection state should be enabled.

According to the above description, the high voltage pumping circuit according to the present invention can be obtained from a conventional high voltage switching pumping circuit by performing voltage pumping once again using a capacitor coupling after performing a voltage pumping process according to a clock signal transition. It is possible to obtain a voltage higher than the voltage present. On the other hand, this means that even if the level of Vcc used in the flash EEPROM device is further lowered, it can generate the high voltage program voltage, erase voltage or read voltage required by the flash EEPROM device.

In realizing the pumping operation by the capacitor coupling, since the MOS transistors M6 and M8 having a relatively small area in layout are used without using a capacitor, the area occupied by the high voltage switching pumping circuit in the flash EEPROM device is used. There is also the advantage of suppressing the increase.

Claims (8)

A word line connected to a plurality of cells of a memory cell array, the high voltage pumping circuit for pumping and delivering a first high voltage according to an operation mode provided in a high voltage generating circuit, When a control signal indicating that the program is in operation and a control signal connected to a clock signal and the first high voltage of the high voltage generation circuit and the control signal indicating that the program operation of the power supply voltage level is enabled are generated according to the logic level transition of the clock signal. A first pumping circuit for pumping an output level to a voltage having a first level above the power supply voltage level by voltage pumping; And It is connected to the output terminal of the first pumping circuit, has the same level as the first high voltage of the high voltage generating circuit and is applied with a second high voltage shifted by a predetermined interval after the voltage of the first high voltage is applied to A second pumping circuit for outputting a voltage at a level higher than the voltage; The second pumping circuit is coupled to an output terminal of the first pumping circuit in the rising period of the second high voltage to charge the charge by the second high voltage to increase the voltage level of the output terminal of the first pumping circuit, And a MOS transistor configured to transfer the output voltage of the first pumping circuit, which is raised in level, to the output terminal of the second pumping circuit when the second high voltage is completed. 2. The method of claim 1, further comprising: a third high voltage connected to an output terminal of the second pumping circuit, the third high voltage being equal to the first high voltage of the high voltage generating circuit and shifted by a predetermined interval after the second high voltage is applied; And a third pumping circuit, wherein the third pumping circuit is coupled to an output terminal of the second pumping circuit in the rising period of the third high voltage to charge the electric charge by the third high voltage to the second pumping circuit. And a MOS transistor for raising the voltage level of the output stage and transferring the output voltage of the second pumping circuit, which has been raised, to the output terminal of the third pumping circuit when the third high voltage is completed. delete The first pumping voltage stabilizing transistor and the first high voltage and the first pumping voltage connected to the output terminal of the first high voltage and the first pumping circuit for stabilizing the output level of the first pumping circuit; And a second pumping voltage stabilizing transistor connected to an output end of the second pumping circuit to stabilize the output level of the second pumping circuit. The method of claim 1, wherein the first pumping circuit is configured to precharge an initial potential level of an input terminal, an output terminal, and an output terminal having a control signal indicating that the program operation is performed and a potential level that changes in response to the clock signal. And a pumping unit connected in a cascade form such that the input stage and the output stage form a positive feedback loop. The NAND gate of claim 5, wherein the input terminal receives a control signal indicating the program operation and the clock signal, and has one end connected to a NAND gate and an output of the NAND gate for outputting an operation result according to the transition of the clock signal. A high voltage pumping circuit comprising a capacitor that shows a potential level that varies with signal transition. 6. The high voltage pumping circuit of claim 5, wherein the precharging unit comprises an NMOS transistor connected between the control signal indicating that the program is in operation and the output terminal. The method of claim 5, wherein the pumping unit is composed of a first and a second NMOS transistor, the output of the first NMOS transistor is connected to the gate of the second NMOS transistor, the output of the second NMOS transistor is the first Coupled to a gate of an NMOS transistor, the first NMOS transistor forms a source-drain path between the input terminal and the output terminal, and the second NMOS transistor forms a source-drain path between the high voltage and the input terminal. High voltage pumping circuit.

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