CN108986866A - A kind of reading high-voltage transmission circuit - Google Patents
A kind of reading high-voltage transmission circuit Download PDFInfo
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- CN108986866A CN108986866A CN201810800624.XA CN201810800624A CN108986866A CN 108986866 A CN108986866 A CN 108986866A CN 201810800624 A CN201810800624 A CN 201810800624A CN 108986866 A CN108986866 A CN 108986866A
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- Prior art keywords
- high pressure
- nmos tube
- enabling signal
- reading
- voltage
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Abstract
The invention discloses a kind of reading high-voltage transmission circuits, comprising: logic circuit, for that will wipe enabling signal ERASE, programming enabling signal PROG will be converted to high pressure enabling signal EPEN and reads enabling signal EN；Control circuit, for high pressure enabling signal EPEN and reading enabling signal EN to be converted to high-voltage transmission control signal Vgate；Transmission circuit, high pressure ZVDDL node is transmitted to for high pressure VD25 will to be read when reading under the control of high-voltage transmission control signal Vgate, and the connection read high pressure VD25 and export high pressure ZVDDL node is disconnected when erasing and programming, the present invention can reduce voltage drop, accelerate the speed of high-voltage transmission, final word line voltage of accelerating establishes speed.
Description
Technical field
The present invention relates to memory technology fields, more particularly to a kind of reading high-voltage transmission circuit.
Background technique
In general, gate-division type flash memory adds 2.5V high pressure in read operation in wordline；Add 1.5V voltage when programming in wordline；
When erasable in wordline plus 12V high pressure, during high speed design, 5V can be introduced to accelerate reading rate, when carrying out read operation, word
Line voltage, which establishes speed, will affect final reading speed.
Fig. 1 is the circuit structure diagram of traditional reading high-voltage transmission circuit.As shown in Figure 1, the source electrode and substrate of PMOS tube P1
It connecing and reads high pressure VD25, the drain electrode of PMOS tube P1 connects the source electrode of PMOS tube P2, and the drain electrode of PMOS tube P2 and substrate meet high pressure ZVDDL,
The grid of PMOS tube P1 meets the first enabling signal EN1, and the grid of PMOS tube P2 meets the second enabling signal EN2, the reading high-voltage transmission
Circuit avoids the influence of bulk effect by two PMOS tube P1 and P2 series connection.Specifically,
When read operation, the first enabling signal EN1, the second enabling signal EN2 are 0, and PMOS tube P1 and P2 are both turned on, ZVDDL
=VD25；When programming or erasing operation, the first enabling signal EN1=2.5V, the second enabling signal EN2=ZVDDL, PMOS tube P1
It is turned off with P2, the path can be turned off.
However, parasitic capacitance-resistance RC is larger, causes transmission speed partially slow in the prior art since two metal-oxide-semiconductors are connected.
Summary of the invention
In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide a kind of reading high-voltage transmission circuit,
To reduce voltage drop, accelerate the speed of high-voltage transmission, when finally accelerating word line voltage and establish speed, and preventing erasing operation
ZVDDL overcharges VD25, plays a protective role.
In view of the above and other objects, the present invention proposes a kind of reading high-voltage transmission circuit, comprising:
Logic circuit, for that will wipe enabling signal ERASE, programming enabling signal PROG will be converted to high pressure enabling signal
EPEN and reading enabling signal EN；
Control circuit, for high pressure enabling signal EPEN and reading enabling signal EN to be converted to high-voltage transmission control letter
Number Vgate；
Transmission circuit, for high pressure VD25 transmission will to be read when reading under the control of high-voltage transmission control signal Vgate
To high pressure ZVDDL node, and the connection read high pressure VD25 and export high pressure ZVDDL node is disconnected when erasing and programming.
Preferably, the transmission circuit is transmitted using NMOS tube, is controlled signal Vgate using high-voltage transmission and is read behaviour to control
The transmission of wordline high pressure when making.
Preferably, the logic circuit includes nor gate, the first level displacement shifter and second electrical level shifter, the erasing
Enabling signal ERASE and programming enabling signal PROG is connected to two input terminals of the nor gate, the output of the nor gate
End is connected to the grant input EN1 of first level displacement shifter, and high pressure ZVDD is connected to first level displacement shifter
Output, that is, high pressure enabling signal EPEN of high voltage input terminal HVIN, first level displacement shifter are connected to the control circuit,
Erasing enabling signal ERASE is connected to the grant input EN2 of the second electrical level shifter, and reading high pressure VD25 is connected to described
The high voltage input terminal HVIN of second electrical level shifter, the output of the second electrical level shifter are read enabling signal EN and are connected to
The control circuit.
Preferably, the control circuit includes the first PMOS tube P1, the first NMOS tube N1 and the second PMOS tube P2 and the
Two NMOS tube N2, the high pressure enabling signal EPEN are connected to the grid of the first PMOS tube P1 and the grid of the first NMOS tube N1
Pole, the reading enabling signal EN are connected to the grid of the second PMOS tube P2 and the grid of the second NMOS tube N2；Read high pressure
VD25 is connected to the source electrode of the second PMOS tube P2, the source electrode ground connection of the second NMOS tube N2, the drain electrode of the second PMOS tube P2 with
The drain electrode of second NMOS tube N2 and the source electrode of the first NMOS tube N1 are connected to form and read voltage Vs node, and high pressure ZVDD is connected to institute
State the source electrode of the first PMOS tube P1, the drain electrode and the drain electrode and the transmission circuit phase of the first NMOS tube N1 of the first PMOS tube P1
Even composition high-voltage transmission controls signal Vgate node.
Preferably, the transmission circuit includes NMOS tube N0, the drain electrode of the first PMOS tube P1 and the first NMOS tube N1
Drain electrode and the grid of the NMOS tube N0 be connected to form high-voltage transmission control signal Vgate node；High pressure VD25 is read to connect
It is connected to the drain electrode of the NMOS tube N0, the source electrode of the NMOS tube N0 is connected to output high pressure ZVDDL node.
Preferably, the transmission circuit is using high-voltage transmission control signal Vgate come wordline high pressure when controlling read operation
Transmission, when read operation, the high-voltage transmission controlled signal Vgate >=VD25+Vth.
Preferably, when read operation, the reading enabling signal EN of the second electrical level shifter output makes the second NMOS tube
N2 conducting, meanwhile, the first PMOS tube P1 is connected in the high pressure enabling signal EPEN of the first level displacement shifter output, and high pressure passes
The NMOS tube N0 is connected in defeated control signal Vgate=ZVDD, the internal high pressure ZVDD >=VD25+Vth.
Preferably, when programming, the reading enabling signal of the second electrical level shifter output makes second NMOS tube
N2 conducting, meanwhile, the first NMOS tube N1 is connected in the high pressure enabling signal EPEN of the first level displacement shifter output, and high pressure passes
Defeated control signal Vgate=Vs=0 ends the NMOS tube N0.
Preferably, when erasing, the reading enabling signal EN of the second electrical level shifter output makes the second PMOS tube P2
Conducting, meanwhile, the first NMOS tube N1 is connected in the high pressure enabling signal EPEN of the first level displacement shifter output, high-voltage transmission
Control signal Vgate=Vs=VD25 ends the NMOS tube N0.
Preferably, at the end of erasing operation, high pressure ZVDD can be discharged to Vgate when read operation, wherein and Vgate >=
VD25+Vth exports high pressure ZVDDL=ZVDD at this time；When entering standby mode, NMOS tube N0 conducting, due to the threshold of NMOS
The voltage value that high pressure VD25 can be limited in Vgate-Vth is read in threshold voltage loss, eliminates output high pressure ZVDDL to reading high pressure
The coupling of VD25 protects reading high pressure VD25 to be not coupled to high voltage.
Compared with prior art, a kind of reading high-voltage transmission circuit of the present invention is passed by being transmitted using NMOS tube using high pressure
Defeated control signal Vgate (Vgate >=VD25+Vth, the present invention select 5V) come the transmission of wordline high pressure when controlling read operation, with
Reach reduction voltage drop, accelerates the speed of high-voltage transmission, the final purpose accelerated word line voltage and establish speed, meanwhile, this hair
It is bright to prevent ZVDDL when erasing operation from overcharging to high pressure VD25 is read, it plays a protective role.
Detailed description of the invention
Fig. 1 is the circuit structure diagram of traditional reading high-voltage transmission circuit；
Fig. 2 is a kind of structural schematic diagram for reading high-voltage transmission circuit of the present invention；
Fig. 3 is the reading high-voltage transmission circuit of the prior art and the simulation result of the present invention read when high-voltage transmission circuit is read
Comparison diagram.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under spirit of the invention.
Fig. 2 is a kind of structural schematic diagram for reading high-voltage transmission circuit of the present invention.As shown in Fig. 2, a kind of reading high pressure of the present invention
Transmission circuit, comprising: logic circuit 10, control circuit 20 and transmission circuit 30.
Wherein, logic circuit 10 is made of nor gate NOR1, the first level displacement shifter LS1 and second electrical level shifter LS2,
For that will wipe enabling signal ERASE, programming enabling signal PROG is converted to high pressure enabling signal EPEN and reads enabling signal
EN；Control circuit 20 is made of PMOS tube P1, NMOS tube N1 and PMOS tube P2 and NMOS tube N2, is used for high pressure enabling signal
EPEN and the high-voltage transmission that is converted to for reading enabling signal EN control signal Vgate；Transmission circuit 30 is made of NMOS tube N0, is used
High pressure VD25 will be read when reading under the control in high-voltage transmission control signal Vgate and is transmitted to high pressure ZVDDL node, and in
The connection read high pressure VD25 and export high pressure ZVDDL node is disconnected when erasing and programming.
Erasing enabling signal ERASE and programming enabling signal PROG is connected to two input terminals or non-of nor gate NOR1
The output end of door NOR1 is connected to the grant input EN1 of the first level displacement shifter LS1, and high pressure ZVDD is connected to the first level position
Output, that is, high pressure enabling signal the EPEN for moving the high voltage input terminal HVIN, the first level displacement shifter LS1 of device LS1 is connected to PMOS tube
The grid of P1 and the grid of NMOS tube N1；Erasing enabling signal ERASE is additionally coupled to the license input of second electrical level shifter LS2
EN2 is held, reads the high voltage input terminal HVIN that high pressure VD25 is connected to second electrical level shifter LS2, second electrical level shifter LS2's is defeated
Enabling signal EN is read out is connected to the grid of PMOS tube P2 and the grid of NMOS tube N2；It reads high pressure VD25 and is connected to PMOS tube
The source electrode of P2, the source electrode ground connection of NMOS tube N2, the source electrode phase of the drain electrode of PMOS tube P2 and the drain electrode of NMOS tube N2 and NMOS tube N1
Even composition reads voltage Vs node, and high pressure ZVDD is connected to the source electrode of PMOS tube P1, and the drain electrode of PMOS tube P1 is with NMOS tube N1's
The grid of drain electrode and NMOS tube N0 are connected to form high-voltage transmission control signal Vgate node；It reads high pressure VD25 and is connected to NMOS tube
The drain electrode of N0, the source electrode of NMOS tube N0 are connected to output high pressure ZVDDL node.
Illustrate the course of work of the invention below in conjunction with table 1: in the specific embodiment of the invention, the present invention is by NMOS tube
Transmission, using high-voltage transmission control signal Vgate come the transmission of wordline high pressure when controlling read operation, working voltage meter such as 1 institute of table
Show:
Table 1
| Operation | VD25 | ZVDD | Vs | EPEN | Vgate | ZVDDL |
| Read | 2.5V | 5V | 0V | 0V | 5V | 2.5V |
| Program | 2.5V | 8V | 0V | 8V | 0V | 1.5V |
| Erase | 2.5V | 12V | 2.5V | 12V | 2.5V | 12V |
When read operation, high pressure VD25=2.5V, the reading of internal high pressure ZVDD=5V, second electrical level shifter LS2 output are read
Enabling signal EN=VD25=2.5V is taken, voltage Vs=0V is read in NMOS tube N2 conducting, meanwhile, the first level displacement shifter LS1 is defeated
High pressure enabling signal EPEN=0V, PMOS tube P1 conducting out, it is (described internal high that high-voltage transmission controls signal Vgate=ZVDD
ZVDD >=VD25+Vth is pressed, wherein Vth is the threshold value of the NMOS tube N0, preferably, the ZVDD in the specific embodiment of the invention
=5V), NMOS tube N0 conducting exports high pressure ZVDDL=VD25=2.5V.
When programming, high pressure VD25=2.5V, the reading of internal high pressure ZVDD=8V, second electrical level shifter LS2 output are read
Voltage Vs=0V is read in enabling signal EN=VD25=2.5V, NMOS tube N2 conducting, meanwhile, the first level displacement shifter LS1 output
High pressure enabling signal EPEN=8V, NMOS tube N1 conducting, high-voltage transmission controls signal Vgate=Vs=0V, and NMOS tube N0 is cut
Only, high pressure ZVDDL=1.5V is exported.
When erasing, high pressure VD25=2.5V, the reading of internal high pressure ZVDD=12V, second electrical level shifter LS2 output are read
Voltage Vs=VD25=2.5V is read in enabling signal EN=0V, PMOS tube P2 conducting, meanwhile, the first level displacement shifter LS1 output
High pressure enabling signal EPEN=12V, NMOS tube N1 conducting, high-voltage transmission controls signal Vgate=Vs=2.5V, NMOS tube N0
Cut-off, exports high pressure ZVDDL=ZVDD=12V, and high-voltage transmission controls signal Vgate=2.5V to reduce NMOS tube N0's
GIDL (Gated-Induce Drain Leakage, grid induced drain leakage current) effect.
At the end of erasing operation, high pressure ZVDD can be discharged to Vgate when read operation, i.e. Vgate >=VD25+Vth, this
When export high pressure ZVDDL=ZVDD；When entering standby (standby) mode, NMOS tube N0 conducting, due to the threshold value of NMOS
The loss of voltage reads the voltage value that high pressure VD25 can be limited in Vgate-Vth, eliminates output high pressure ZVDDL to reading high pressure
The coupling of VD25 protects reading high pressure VD25 to be not coupled to high voltage.
The present invention carries out high pressure with NMOS tube N0 and reads transmission, and high-voltage transmission controls signal Vgate >=VD25+ when reading
Vth, Vth are that the threshold value of NMOS tube N0 preferably, the present invention selects Vgate=5V considers the loss of threshold voltage, VD25≤
Vgate-Vth plays a protective effect.
Fig. 3 is the reading high-voltage transmission circuit of the prior art and the simulation result of the present invention read when high-voltage transmission circuit is read
Comparison diagram.As shown in figure 3,
When SS process corner (SS corner, Slow NMOS Slow PMOS), high pressure VD25=2.4V is read；
Output high pressure ZVDDL overturning moment pressure drop is reduced to 0.29V (2.4-2.11) from 0.808V (2.4-1.592), such as
Shown in table 2, ZVDDL_post is present invention output high pressure ZVDDL simulation value, and ZVDDL_pre is that the prior art exports high pressure
ZVDDL simulation value；
Table 2
| VD25 | ZVDDL_post | ZVDDL_pre | |
| 2.4 | 2.11 | 1.592 | |
| Delta | -0.29 | -0.808 |
The rate of climb is reduced to 3.8ns (13%) from 4.367ns, as shown in figure 3, v (zvdd) ss01.tr0 is the present invention
High input voltage (voltage 4.99V at cursor), v (zvdd) ss00.tr0 are prior art high input voltage (voltage at dotted line
4.979V), the two is substantially overlapping, intermediate node v (zvdd2) ss01.tr0 of the present invention and the intermediate node v of the prior art
(zvdd2) ss00.tr0 also coincide substantially, and output high pressure v (zvdd1) ss01.tr0 (2.175) of the present invention is (defeated at dotted line
High pressure overturns moment out) it is apparently higher than output high pressure v (zvdd1) ss00.tr0 (1.592), v (wl [0]) of the prior art
Ss01.tr0 is the output high pressure ascending curve that the present invention is selected wordline wl [0] when reading, and v (wl [0]) ss01.tr0 is to read
The prior art is selected the output high pressure ascending curve of wordline wl [0] when taking, and the present invention's is selected on the voltage of wordline wl [0]
It is raised to the voltage (time-consuming 4.367nS) that setting voltage (time-consuming 3.8nS) is significantly faster than that selected wordline wl [0] of the prior art.
As it can be seen that a kind of reading high-voltage transmission circuit of the present invention controls signal by transmitting using NMOS tube, using high-voltage transmission
Vgate (Vgate >=VD25+Vth, the present invention select 5V) reduces electricity come the transmission of wordline high pressure when controlling read operation to reach
Pressure drop is pressed, the speed of high-voltage transmission is accelerated, the final purpose accelerated word line voltage and establish speed, meanwhile, the present invention can prevent from wiping
ZVDDL is overcharged to high pressure VD25 is read when except operation, is played a protective role.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (10)
1. a kind of reading high-voltage transmission circuit, comprising:
Logic circuit, for will wipe enabling signal ERASE, programming enabling signal PROG be converted to high pressure enabling signal EPEN and
Read enabling signal EN；
Control circuit, for high pressure enabling signal EPEN and reading enabling signal EN to be converted to high-voltage transmission control signal
Vgate；
Transmission circuit, it is supreme for high pressure VD25 transmission will to be read when reading under the control of high-voltage transmission control signal Vgate
ZVDDL node is pressed, and disconnects the connection read high pressure VD25 and export high pressure ZVDDL node when erasing and programming.
2. a kind of reading high-voltage transmission circuit as described in claim 1, it is characterised in that: the logic circuit include nor gate,
First level displacement shifter and second electrical level shifter, the erasing enabling signal ERASE and programming enabling signal PROG are connected to
Two input terminals of the nor gate, the output end of the nor gate are connected to the grant input of first level displacement shifter
EN1, high pressure ZVDD are connected to the high voltage input terminal HVIN of first level displacement shifter, the output of first level displacement shifter
That is high pressure enabling signal EPEN is connected to the control circuit, and erasing enabling signal ERASE is connected to the second electrical level displacement
The grant input EN2 of device, reads the high voltage input terminal HVIN that high pressure VD25 is connected to the second electrical level shifter, and described second
The output of level displacement shifter reads enabling signal EN and is connected to the control circuit.
3. a kind of reading high-voltage transmission circuit as claimed in claim 2, it is characterised in that: the control circuit includes the first PMOS
Pipe P1, the first NMOS tube N1 and the second PMOS tube P2 and the second NMOS tube N2, the high pressure enabling signal EPEN are connected to institute
The grid of the first PMOS tube P1 and the grid of the first NMOS tube N1 are stated, the reading enabling signal EN is connected to the 2nd PMOS
The grid of the grid of pipe P2 and the second NMOS tube N2；Read the source electrode that high pressure VD25 is connected to the second PMOS tube P2, the second NMOS tube
The source electrode of N2 is grounded, drain electrode and the drain electrode of the second NMOS tube N2 and the source electrode phase of the first NMOS tube N1 of the second PMOS tube P2
Even composition reads voltage Vs node, and high pressure ZVDD is connected to the source electrode of the first PMOS tube P1, the drain electrode of the first PMOS tube P1
Drain electrode and the transmission circuit with the first NMOS tube N1 are connected to form high-voltage transmission control signal Vgate node.
4. a kind of reading high-voltage transmission circuit as claimed in claim 3, it is characterised in that: the transmission circuit includes NMOS tube
The grid of the drain electrode of N0, the first PMOS tube P1 and the drain electrode of the first NMOS tube N1 and the NMOS tube N0 is connected to form described
High-voltage transmission controls signal Vgate node；Read the drain electrode that high pressure VD25 is connected to the NMOS tube N0, the source of the NMOS tube N0
Pole is connected to output high pressure ZVDDL node.
5. a kind of reading high-voltage transmission circuit as claimed in claim 4, it is characterised in that: the transmission circuit utilizes high-voltage transmission
Signal Vgate is controlled come the transmission of wordline high pressure when controlling read operation, when read operation the high-voltage transmission control signal Vgate >=
VD25+Vth, wherein Vth is the threshold value of the NMOS tube N0.
6. a kind of reading high-voltage transmission circuit as claimed in claim 4, it is characterised in that: when read operation, the second electrical level
The second NMOS tube N2 is connected in the reading enabling signal EN of shifter output, meanwhile, the height of the first level displacement shifter output
The first PMOS tube P1 is connected in pressure enabling signal EPEN, and high-voltage transmission control signal Vgate=ZVDD leads the NMOS tube N0
Logical, the internal high pressure ZVDD >=VD25+Vth, wherein Vth is the threshold value of the NMOS tube N0.
7. a kind of reading high-voltage transmission circuit as claimed in claim 4, it is characterised in that: when programming, the second electrical level position
The second NMOS tube N2 is connected in the reading enabling signal for moving device output, meanwhile, the height of the first level displacement shifter output
The first NMOS tube N1 is connected in pressure enabling signal EPEN, and high-voltage transmission control signal Vgate=Vs=0 cuts the NMOS tube N0
Only.
8. a kind of reading high-voltage transmission circuit as claimed in claim 4, it is characterised in that: when erasing, the second electrical level position
The second PMOS tube P2 is connected in the reading enabling signal EN for moving device output, meanwhile, the high pressure of the first level displacement shifter output
The first NMOS tube N1 is connected in enabling signal EPEN, and high-voltage transmission control signal Vgate=Vs=VD25 makes the NMOS tube N0
Cut-off.
9. a kind of reading high-voltage transmission circuit as claimed in claim 4, it is characterised in that: when erasing, the NMOS tube N0 grid
Pole tension and drain voltage, which are equal to, reads high pressure VD25, eliminates the grid induced drain leakage current of the NMOS tube N0.
10. a kind of reading high-voltage transmission circuit as claimed in claim 4, it is characterised in that: at the end of erasing operation, high pressure
ZVDD can be discharged to Vgate when read operation, wherein Vgate >=VD25+Vth, export high pressure ZVDDL=ZVDD at this time；Into
When entering to standby mode, NMOS tube N0 conducting reads high pressure VD25 and is limited in Vgate- since the threshold voltage of NMOS loses
The voltage value of Vth, eliminate output high pressure ZVDDL to read high pressure VD25 coupling, protection read high pressure VD25 be not coupled to
High voltage.
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| CN201810800624.XA CN108986866B (en) | 2018-07-20 | 2018-07-20 | Read high voltage transmission circuit |
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|---|---|---|---|
| CN201810800624.XA CN108986866B (en) | 2018-07-20 | 2018-07-20 | Read high voltage transmission circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111367341A (en) * | 2018-12-26 | 2020-07-03 | 北京兆易创新科技股份有限公司 | Reference voltage generating circuit and NAND chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111367341A (en) * | 2018-12-26 | 2020-07-03 | 北京兆易创新科技股份有限公司 | Reference voltage generating circuit and NAND chip |
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| CN108986866B (en) | 2020-12-11 |
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