CN102867535A - Storage device and word line voltage generating circuit thereof - Google Patents
Storage device and word line voltage generating circuit thereof Download PDFInfo
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- CN102867535A CN102867535A CN2012103668608A CN201210366860A CN102867535A CN 102867535 A CN102867535 A CN 102867535A CN 2012103668608 A CN2012103668608 A CN 2012103668608A CN 201210366860 A CN201210366860 A CN 201210366860A CN 102867535 A CN102867535 A CN 102867535A
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Abstract
The invention discloses a storage device and a word line voltage generating circuit of the storage device. The circuit comprises a word line power voltage generating circuit, a read-write control switching unit, a preliminary decoder, a row decoder, a high-voltage generating module and a normal voltage generating module, wherein the high-voltage generating module is connected to a control pulse and high voltage and is connected to an input end of the preliminary decoder, so that when the control pulse is high, the high voltage serves as output voltage of the high-voltage generating module to be provided for the preliminary decoder, and a rising edge of an address driving signal output by the preliminary decoder is reduced; the normal voltage generating module is connected to the control pulse and the read-write control switching unit and is connected to an input end of the preliminary decoder, so that when the control pulse is low, the read-write control voltage serves as output voltage of the normal voltage generating module to be provided for the preliminary decoder. The problem that the word line voltage slowly rises so as to influence the read-write speed of the storage unit because the preliminary decoder is insufficient is pushing can be solved.
Description
Technical field
The present invention relates to a kind of storer and word line voltage thereof and produce circuit, particularly relate to a kind of read-write operation word line voltage storer and word line voltage generation circuit thereof of Time Created accelerated.
Background technology
Storage unit is carried out fast reading and writing, is pursuing a goal of high-speed memory chip (such as flash etc.) always.Read-write operation word line voltage on the word line of storage unit is the key factor of restriction read or write speed Time Created, and therefore, for storer, it is particularly important that word line voltage produces circuit.
Fig. 1 is a kind of structural representation with storer of word line voltage generator in the prior art.As shown in Figure 1, this storer comprises that word line voltage produces circuit 10, storage array 11 and word line, wherein the word line links to each other with storage array 11, be used under word line voltage produces the support of the read-write operation word line voltage that circuit 10 produces, reading the data of storage array 11 or to storage array 11 data writings, in the prior art, word line voltage produces circuit 10 and comprises word line circuit for generating source voltage 101, read-write control switch unit 102, pre-decode device 103 and row decoding unit 104, word line circuit for generating source voltage 101 is for generation of total word line supply voltage, it comprises charge pump 1, earth detector, charge pump 2, voltage stabilizer and switch NMOS pipe N1, charge pump 1 produces voltage Vpwl and is connected to switch NMOS pipe N1 drain electrode, charge pump 2 and a reference voltage Vref are connected to two input ends of voltage stabilizer, output reference voltage Vclamp is to switch NMOS pipe base stage, the word line supply voltage ZVDD_P total by the source electrode output of switch NMOS pipe N1 controls switch unit 102, two termination earth detectors of charge pump 1 to reading and writing; Read-write control switch unit 102 is exported read-write control voltage ZVDD to pre-decode device 103 under the control of read-write control signal; Pre-decode device 103 is ground connection location signal A＜x:0 under read-write control voltage ZVDD effect 〉, produce the address and drive signal XPZ＜m:0 to row decoding unit 104; Row decoding unit 104 drives signal XPZ＜m:0 at read-write control voltage ZVDD and address〉generation read-write operation word line voltage WL＜m:0 〉.Fig. 2 is the physical circuit schematic diagram of row decoding unit in the prior art.As shown in Figure 2, input termination read-write control voltage ZVDD and the address XPA＜m:0 of block selection circuit 〉, signal SEL and anti-phase selection signal SELb are selected in output, and PMOS pipe P1 and NMOS pipe N2 parallel connection meet NMOS pipe N3 again, wherein anti-phase selection signal SELb connects the grid of PMOS pipe P1 and NMOS pipe N 3, select signal SEL to connect the grid that NMOS manages N2, when SEL is high, all conductings of N2, P1, this moment, SELb was low, the N3 pipe is obstructed, and like this, XPZ (m:0) is sent to WL (m:0); Otherwise N3 manages conducting, N2, P1 are obstructed, XPZ (m:0) can not reach WL (m:0), WL (m:0) is grounded, it should be noted that at this, the row decoding unit has a lot of branch roads, the appearance that namely has a lot of three pipes (P1/N2/N3) to be connected together in fact, bus situation altogether m+1 NP pipe parallel connection connects the N pipe again, does not repeat them here.
Fig. 3 is the sequential chart of each signal in the prior art.As seen because the pre-decode device promotes deficiency, the rising edge of address driving signal XPZ (m:0) rises very slow, thereby causes read-write operation word line voltage WL (m:0) to rise slowly, affects the read or write speed of storage unit.
Summary of the invention
The deficiency that exists for overcoming above-mentioned prior art, the present invention's purpose is to provide a kind of storer and word line voltage thereof to produce circuit, it can the Rapid Establishment word line voltage, avoids increasing promoting circuit size and solving again because promoting deficiency and cause word line voltage to rise slowly to affect the problem of storage unit read or write speed.
For reaching above-mentioned and other purpose, the invention provides a kind of word line voltage and produce circuit, to produce the read-write operation word line voltage on the storage unit word line, comprise word line circuit for generating source voltage, read-write control switch unit, pre-decode device and line decoder, in addition, this word line voltage generation circuit also comprises:
The high voltage generation module, be connected in a gating pulse and high voltage, and be connected to the input end of this pre-decode device, this high voltage is offered this pre-decode device as the output voltage of this high voltage generation module in this gating pulse when high, drive the rising edge of signal with the address of reducing this pre-decode device output; And
The normal voltage generation module, be connected in this gating pulse and this read-write control switch unit, and be connected to the input end of this pre-decode device, control voltage and offer this pre-decode device as the output voltage of this normal voltage generation module will read and write read-write that the control switch unit exports when low in this gating pulse.
Further, this high voltage generation module comprises the first level shifter, the second electrical level shift unit, the one PMOS pipe and the 2nd PMOS pipe, wherein this first level shifter one is inputted this gating pulse of termination, another this high voltage of input termination, the voltage of this gating pulse of input termination of this second electrical level shift unit and the output of this high voltage generation module, the one PMOS pipe source electrode connects this high voltage, grid connects this first level shifter, drain electrode and the interconnection of the 2nd PMOS pipe source electrode, this the second gate pmos utmost point connects this second electrical level shift unit, and drain electrode links to each other with this pre-decode device.
Further, this gating pulse is carried out level shift and is anti-phasely obtained the first gating signal through this first level shifter, and exports this first gate pmos utmost point to.
Further, this gating pulse is carried out level shift through this second electrical level shift unit and is obtained the second gating signal, and exports this second gate pmos utmost point to.
Further, this normal voltage generation module comprises the 3rd level shifter, the 4th level shifter, the 3rd PMOS pipe and the 4th PMOS pipe, wherein voltage and an anti-phase gating pulse are controlled in the read-write of this read-write control unit output of the 3rd level shifter input termination, the voltage of this anti-phase gating pulse of the input termination of the 4th level shifter and the output of this normal voltage generation module, the 3rd PMOS pipe source electrode connects this read-write control voltage, grid connects the 3rd level shifter, drain electrode and the interconnection of the 4th PMOS pipe, the 4th gate pmos utmost point connects the 4th level shifter, and drain electrode links to each other with this pre-decode device.
Further, this anti-phase gating pulse is by the anti-phase rear acquisition of this gating pulse.
Further, this high voltage is the voltage that produces through charge pump in this word line circuit for generating source voltage.
Further, this high voltage is 3.5V～5.5V.
For reaching above-mentioned and other purpose, the present invention also provides a kind of storer, comprise that word line voltage produces circuit, storage array and word line, this word line links to each other with this storage array, be used under this word line voltage produces the support of the read-write operation word line voltage that circuit produces, reading the data of this storage array or to this storage array data writing, this word line voltage produces circuit and also comprises word line circuit for generating source voltage, read-write control switch unit, the pre-decode device, line decoder, high voltage generation module and normal voltage generation module, its high voltage appearance generation module is connected in a gating pulse and high voltage, and be connected to the input end of this pre-decode device, this high voltage is offered this pre-decode device as the output voltage of this high voltage generation module in this gating pulse when high, drive the rising edge of signal with the address of reducing this pre-decode device output; The normal voltage generation module, be connected in this gating pulse and this read-write control switch unit, and be connected to the input end of this pre-decode device, control voltage and offer this pre-decode device as the output voltage of this normal voltage generation module will read and write read-write that the control switch unit exports when low in this gating pulse.
Compared with prior art, the present invention introduces high voltage Vpwl and carries out pre-decode Rapid Establishment XPZ (m:0) setting up the word line voltage initial stage by increasing gating pulse P_boost, process row decoding Rapid Establishment word line voltage WL (m:0) has avoided increasing the promotion circuit size and has solved the not enough problem that causes the word line voltage rising to affect slowly the storage array operation that promotes.。
Description of drawings
Fig. 1 is a kind of structural representation with storer of word line voltage generator in the prior art;
Fig. 2 is the physical circuit schematic diagram of row decoding unit in the prior art;
Fig. 3 is the sequential chart of each signal in the prior art;
Fig. 4 is the electrical block diagram of the specific embodiment of a kind of tool word line voltage of the present invention storer that produces circuit;
Fig. 5 is the sequential chart of each signal in the present invention's the preferred embodiment.
Embodiment
Below by specific instantiation and accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention also can be implemented or be used by other different instantiation, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not deviating from.
Fig. 4 is the electrical block diagram of the specific embodiment of a kind of tool word line voltage of the present invention storer that produces circuit.As shown in Figure 4, a kind of tool word line voltage of the present invention produces the storer of circuit, comprise that word line voltage produces circuit 40, storage array 41 and word line WL＜m:0 〉, word line WL＜m:0 wherein〉link to each other with storage array 41, be used under word line voltage produces the support of the read-write operation word line voltage that circuit 10 produces, reading the data of storage array 41 or to storage array 41 data writings, in the present invention, word line voltage produces circuit 40 and comprises again word line circuit for generating source voltage 401, read-write control switch unit 402, high voltage generation module 403, normal voltage generation module 404, pre-decode device 405 and line decoder 406, word line circuit for generating source voltage 401 wherein, read-write control switch unit 402, the structure of pre-decode device 405 and line decoder 406 is same as the prior art with effect, do not repeat them here, the below is with article high voltage generation module 403 and normal voltage generation module 404.
High voltage generation module 403 is connected in a gating pulse P_boost and high voltage Vpwl, and be connected to the input end of pre-decode device 405, high voltage Vpwl is offered pre-decode device 405 so that the rise time of pre-decode device 405 shortens as the output voltage ZVpz of high voltage generation module 403 in gating pulse P_boost when high, driving velocity is accelerated, thereby the address of reducing 405 outputs of pre-decode device drives signal XPZ＜m:0〉rising edge; Normal voltage generation module 404 is connected in gating pulse P_boost and read-write control switch unit, and be connected to the input end of pre-decode device 405, control voltage ZVDD take the read-write that will read and write 402 outputs of control switch unit in gating pulse P_boost when low and offer pre-decode device 405 as the output voltage ZVpz of normal voltage generation module 403.
Particularly, high voltage generation module 403 comprises the first level shifter 407, second electrical level shift unit 408, the one PMOS pipe P1 and the 2nd PMOS pipe P2, wherein the first level shifter 407 1 is inputted termination gating pulse P_boost, another input termination high voltage Vpwl, it should be noted that at this, in preferred embodiment of the present invention, high voltage Vpwl is the voltage that produces through charge pump 1 in the word line circuit for generating source voltage 401, gating pulse P_boost is that the first level shifter 407 of Vpwl carries out level shift and the anti-phase first gating signal Psel0 that obtains through supply voltage, the voltage ZVpz of the input termination gating pulse P_boost of second electrical level shift unit 408 and 403 outputs of high voltage generation module, gating pulse P_boost is that the second electrical level shifter 408 of ZVpz carries out level shift and obtains the second gating signal Psel1 through supply voltage, the one PMOS pipe P1 source electrode meets high voltage Vpwl, grid meets the first gating signal Psel0, drain electrode and the interconnection of the 2nd PMOS pipe P2 source electrode, the 2nd PMOS pipe P2 grid meets the second gating signal Psel1, and drain electrode output voltage ZVpz is to pre-decode device 405.
Normal voltage generation module 404 comprises the 3rd level shifter 409, the 4th level shifter 410, the 3rd PMOS pipe P3 and the 4th PMOS pipe P4, read-write control voltage ZVDD and the anti-phase gating pulse P_boostb of 402 outputs of the 3rd level shifter 409 input termination read-write control units, that is: the designature of gating pulse P_boost, anti-phase gating pulse P_boostb is that the 3rd level displacement shifter 409 of ZVDD carries out level shift and obtains the 3rd gating signal Psel2 through supply voltage, the voltage ZVpz of the anti-phase gating pulse P_boostb of input termination of the 4th level shifter 410 and high voltage generation module 403 (or normal voltage generation module 404) output, anti-phase gating pulse P_boostb is that the 4th level displacement shifter 410 of ZVpz carries out level shift and obtains the 4th gating signal Psel3 through supply voltage, the 3rd PMOS pipe P3 source electrode meets read-write control voltage ZVDD, grid meets the 3rd gating signal Psel2, drain electrode and the 4th PMOS pipe P4 interconnection, the 4th PMOS pipe P4 grid meets the 4th gating signal Psel3, and drain electrode output voltage ZVpz is to pre-decode device 405.
Fig. 5 is the sequential chart of each signal in the present invention's the preferred embodiment.Below will cooperate Fig. 5 to further specify the present invention.
Gating pulse P_boost is that the first level displacement shifter of Vpwl carries out obtaining the first gating signal Psel0 after the level shift P1 pipe break-make is control effectively through supply voltage, and gating pulse P_boost is that the second electrical level shifter of ZVpz carries out obtaining the second gating signal Psel1 after the level shift P2 pipe break-make is control effectively through supply voltage; Anti-phase gating pulse P_boostb is that gating pulse P_boost obtains after anti-phase, anti-phase gating pulse P_boostb is that the 3rd level displacement shifter of Vpwl carries out obtaining the 3rd gating signal Psel2 after the level shift P3 pipe break-make is control effectively through supply voltage, and anti-phase gating pulse P_boostb is that the 4th level displacement shifter of ZVpz carries out obtaining the 4th gating signal Psel3 after the level shift P4 pipe break-make is control effectively through supply voltage.Each level displacement shifter plays a part to prevent that the supply voltage Different Effects respectively manages break-make.Anti-phase through level displacement shifter displacement backgating signal Psel0, Psel1 and gating pulse P_boost, and gating signal Psel2, Psel3 and gating pulse P_boost homophase,
Vclamp is low when initial, and general supply voltage ZVDD_P, read-write control voltage ZVDD are low, are low thereby ZVpz and address drive signal XPZ (m:0), and read-write control word line voltage WL (m:0) also is low; Gating pulse P_boost begins to be height after ZVDD_P is stable, this moment, the first gating signal Psel0 was low, PMOS pipe P1 conducting, high voltage Vpwl is transferred into the drain electrode of P1, the P2 source electrode, this moment, ZVpz not yet set up, voltage is 0, the second gating signal Psel1 is low, thereby PMOS pipe P2 conducting, Vpwl is through P1, P2 is sent to the P2 drain electrode and forms ZVpz, this voltage begins to rise, the output of adjusting second electrical level shifter 408 makes the second gating signal Psel1 output low level, even then ZVpz is increased to stationary value, P2 still keeps conducting, and dynamically keep ZVpz be stabilized in be lower than Vpwl approximately 0.3-0.7V (depending on the circuit needs, intermediate value 0.5V is got in preferred embodiment of the present invention), while the 3rd gating signal Psel2, the 4th gating signal Psel3 is high, and PMOS manages P3, the P4 cut-off, ZVDD can not be sent to the P2 drain electrode by P3 affects ZVpz.
Behind gating pulse P_boost step-down, this moment, the first gating signal Psel0 was high, PMOS pipe P1 cut-off, and the second gating signal Psel1 also is high, PMOS pipe P2 cut-off, high voltage Vpwl can not be sent to the P2 drain electrode by P1 affects ZVpz; While the 3rd gating signal Psel2 step-down, PMOS pipe P3 conducting, read-write control voltage ZVDD is transferred into drain electrode, the P4 source electrode of P3, therefore the 4th gating signal Psel3 also is low the time, PMOS pipe P4 conducting, this moment, ZVpz was higher, and then ZVpz also finally is stabilized in ZVDD by subsequent conditioning circuit and P4, P3 discharge.
In sum, as seen, the present invention introduces high voltage Vpwl and carries out pre-decode Rapid Establishment XPZ (m:0) setting up the word line voltage initial stage by increasing gating pulse P_boost, process row decoding Rapid Establishment word line voltage WL (m:0) has avoided increasing the promotion circuit size and has solved the not enough problem that causes the word line voltage rising to affect slowly the storage array operation that promotes.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and above-described embodiment is modified and changed.Therefore, the scope of the present invention should be listed such as claims.
Claims (9)
1. a word line voltage produces circuit, to produce the read-write operation word line voltage on the storage unit word line, comprise word line circuit for generating source voltage, read-write control switch unit, pre-decode device and line decoder, it is characterized in that, this word line voltage produces circuit and also comprises:
The high voltage generation module, be connected in a gating pulse and high voltage, and be connected to the input end of this pre-decode device, this high voltage is offered this pre-decode device as the output voltage of this high voltage generation module in this gating pulse when high, drive the rising edge of signal with the address of reducing this pre-decode device output; And
The normal voltage generation module, be connected in this gating pulse and this read-write control switch unit, and be connected to the input end of this pre-decode device, control voltage and offer this pre-decode device as the output voltage of this normal voltage generation module will read and write read-write that the control switch unit exports when low in this gating pulse.
2. word line voltage as claimed in claim 1 produces circuit, it is characterized in that: this high voltage generation module comprises the first level shifter, the second electrical level shift unit, the one PMOS pipe and the 2nd PMOS pipe, wherein this first level shifter one is inputted this gating pulse of termination, another this high voltage of input termination, the voltage of this gating pulse of input termination of this second electrical level shift unit and the output of this high voltage generation module, the one PMOS pipe source electrode connects this high voltage, grid connects this first level shifter, drain electrode and the interconnection of the 2nd PMOS pipe source electrode, this the second gate pmos utmost point connects this second electrical level shift unit, and drain electrode links to each other with this pre-decode device.
3. word line voltage as claimed in claim 2 produces circuit, it is characterized in that: this gating pulse is carried out level shift and is anti-phasely obtained the first gating signal through this first level shifter, and exports this first gate pmos utmost point to.
4. word line voltage as claimed in claim 3 produces circuit, it is characterized in that: this gating pulse is carried out level shift and is anti-phasely obtained the second gating signal through this second electrical level shift unit, and exports this second gate pmos utmost point to.
5. word line voltage as claimed in claim 2 produces circuit, it is characterized in that: this normal voltage generation module comprises the 3rd level shifter, the 4th level shifter, the 3rd PMOS pipe and the 4th PMOS pipe, wherein voltage and an anti-phase gating pulse are controlled in the read-write of this read-write control unit output of the 3rd level shifter input termination, the voltage of this anti-phase gating pulse of the input termination of the 4th level shifter and the output of this normal voltage generation module, the 3rd PMOS pipe source electrode connects this read-write control voltage, grid connects the 3rd level shifter, drain electrode and the interconnection of the 4th PMOS pipe, the 4th gate pmos utmost point connects the 4th level shifter, and drain electrode links to each other with this pre-decode device.
6. word line voltage as claimed in claim 5 produces circuit, and it is characterized in that: this anti-phase gating pulse is by the anti-phase rear acquisition of this gating pulse.
7. word line voltage as claimed in claim 1 produces circuit, it is characterized in that: the voltage of this high voltage for producing through charge pump in this word line circuit for generating source voltage.
8. word line voltage as claimed in claim 1 produces circuit, and it is characterized in that: this high voltage is 3.5V～5.5V.
9. storer, comprise that word line voltage produces circuit, storage array and word line, this word line links to each other with this storage array, be used under this word line voltage produces the support of the read-write operation word line voltage that circuit produces, reading the data of this storage array or to this storage array data writing, it is characterized in that: this word line voltage produces circuit and also comprises word line circuit for generating source voltage, read-write control switch unit, the pre-decode device, line decoder, high voltage generation module and normal voltage generation module, its high voltage appearance generation module is connected in a gating pulse and high voltage, and be connected to the input end of this pre-decode device, this high voltage is offered this pre-decode device as the output voltage of this high voltage generation module in this gating pulse when high, drive the rising edge of signal with the address of reducing this pre-decode device output; The normal voltage generation module, be connected in this gating pulse and this read-write control switch unit, and be connected to the input end of this pre-decode device, control voltage and offer this pre-decode device as the output voltage of this normal voltage generation module will read and write read-write that the control switch unit exports when low in this gating pulse.
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| CN201210366860.8A CN102867535B (en) | 2012-09-27 | 2012-09-27 | Memorizer and word line voltage thereof produce circuit |
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| CN103177749A (en) * | 2013-02-01 | 2013-06-26 | 上海宏力半导体制造有限公司 | Read voltage generation circuit |
| CN104464803A (en) * | 2013-09-18 | 2015-03-25 | 北京兆易创新科技股份有限公司 | Reading voltage generating device and flash memory system |
| CN104681088A (en) * | 2015-02-28 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Row address decoding circuit |
| CN105427884A (en) * | 2014-09-12 | 2016-03-23 | 上海华虹宏力半导体制造有限公司 | Novel x decoder circuit |
| CN108986866A (en) * | 2018-07-20 | 2018-12-11 | 上海华虹宏力半导体制造有限公司 | A kind of reading high-voltage transmission circuit |
| CN112687303A (en) * | 2020-12-28 | 2021-04-20 | 海光信息技术股份有限公司 | Voltage control circuit, memory and electronic device |
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| CN108986866A (en) * | 2018-07-20 | 2018-12-11 | 上海华虹宏力半导体制造有限公司 | A kind of reading high-voltage transmission circuit |
| CN108986866B (en) * | 2018-07-20 | 2020-12-11 | 上海华虹宏力半导体制造有限公司 | Read high voltage transmission circuit |
| CN112687303A (en) * | 2020-12-28 | 2021-04-20 | 海光信息技术股份有限公司 | Voltage control circuit, memory and electronic device |
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