CN107370351B - Charge bleeding circuit - Google Patents
Charge bleeding circuit Download PDFInfo
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- CN107370351B CN107370351B CN201610318329.1A CN201610318329A CN107370351B CN 107370351 B CN107370351 B CN 107370351B CN 201610318329 A CN201610318329 A CN 201610318329A CN 107370351 B CN107370351 B CN 107370351B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/322—Means for rapidly discharging a capacitor of the converter for protecting electrical components or for preventing electrical shock
Abstract
The present invention provides a charge bleeding circuit, comprising: the first discharging unit is connected with a first power end, a second power end and a control signal, when the control signal controls the first discharging unit to be opened, the charge of the first power end is discharged to the second power end, and the first discharging unit is provided with a first node; the second discharging unit is connected with the first power supply end and a third power supply end and connected to the first node; and the voltage detection unit is connected to the first node and used for detecting the voltage of the first node, when the voltage of the first node is reduced to a safe value, the second discharge unit is opened, and the charge of the first power supply end is discharged to the third power supply end. In the invention, the voltage detection unit enables the charge of the first power supply end to be discharged to the third power supply end after the charge of the first power supply end is discharged to the second power supply end for a period of time, so that the discharge processes of the first power supply end to the second power supply end and the third power supply end are controlled, and the voltage detection unit is closed after a period of time, so that no static power consumption exists.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a charge bleeder circuit.
Background
Electrically erasable read-only memory (EPROM) is widely used as a storage medium due to its low voltage and low power consumption, for example, in a Radio Frequency Identification (RFID) system. Based on the working principle of the EEPROM, in the process of erasing the memory cell in the EEPROM, a high voltage needs to be provided to the EEPROM, however, before the EEPROM is programmed or erased, a data buffering operation needs to be performed on the EEPROM, and a normal working voltage is generally adopted in the process of the data buffering operation, so that the voltage of the EEPROM needs to be switched between the erasing high voltage and the working voltage, in order to avoid the high voltage from affecting the data buffering operation, in the prior art, the erasing high voltage is usually discharged after the erasing process, and then the working voltage is recharged, for example, the erasing high voltage is directly discharged to a working voltage end. However, due to the particularity of the RFID power supply, the power supply voltage-stabilizing capacitor is only 1nf or even smaller, and when the capacity of the EEPROM is larger and larger, the charge discharged to the operating voltage after erasing is also larger. Thus possibly causing the operating voltage to be too high and the transistor to break down.
Disclosure of Invention
The invention aims to provide a charge bleeding circuit, which solves the technical problem that the erasing high-voltage bleeding process is uncontrollable in the prior art.
To solve the above technical problem, the present invention provides a charge bleeding circuit, including:
the first discharging unit is connected with a first power end, a second power end and a control signal, when the control signal controls the first discharging unit to be opened, the charge of the first power end is discharged to the second power end, and the first discharging unit is provided with a first node;
the second bleeder unit is connected with the first power supply end and a third power supply end and connected to the first node;
and the voltage detection unit is connected to the first node and is used for detecting the voltage of the first node, when the voltage of the first node is reduced to a safe value, the second discharge unit is opened, and the charge of the first power supply end is discharged to the third power supply end.
Optionally, the first bleeding unit includes:
a first transistor, wherein a source electrode is connected with the first power supply end, a drain electrode is connected with the first node, and a grid electrode is connected with the voltage detection unit;
a second transistor having a drain connected to the first node and a gate connected to the third power supply terminal;
and the input end of the first phase inverter is connected with the control signal, and the output end of the first phase inverter is connected with the source electrode of the second transistor.
Optionally, the first inverter includes a third transistor and a fourth transistor, a source of the third transistor is connected to the third power source terminal, a drain of the third transistor is connected to the source of the second transistor, a gate of the third transistor is connected to the control signal, a source of the fourth transistor is connected to the second power source terminal, a drain of the fourth transistor is connected to the source of the second transistor, and a gate of the fourth transistor is connected to the control signal.
Optionally, the first bleeder unit further comprises a first resistor, and the first resistor is connected between the drain of the first transistor and the drain of the second transistor.
Optionally, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.
Optionally, the second bleeding unit includes a fifth transistor, a source of the fifth transistor is connected to the first power source terminal, a drain of the fifth transistor is connected to the third power source terminal, and a gate of the fifth transistor is connected to the first node.
Optionally, a second inverter and a third inverter are sequentially connected between the first node and the gate of the fifth transistor.
Optionally, the fifth transistor is a PMOS transistor.
Optionally, the voltage detection unit includes:
a sixth transistor having a source connected to the third power terminal, a drain connected to the first bleeder unit, and a gate connected to the second node;
a seventh transistor having a source connected to the third power source terminal, a drain connected to the second node, and a gate connected to the first node;
a second resistor connected between the drain of the sixth transistor and the second node;
an eighth transistor having a drain connected to the second node and a gate connected to the control signal;
and a ninth transistor having a source connected to the second power source terminal, a drain connected to the drain of the eighth transistor, and a gate connected to the first node.
Optionally, the sixth transistor and the seventh transistor are PMOS transistors, and the eighth transistor and the ninth transistor are NMOS transistors.
Optionally, when the control signal rises to a high potential, the eighth transistor is turned on, the voltage detection voltage is turned on, the potential of the sixth transistor decreases, the first bleeder circuit is turned on, the charge of the first power end is bled to the second power end, the potential of the first node decreases and decreases to the safety value, the second bleeder circuit is turned on, the charge of the first power end is bled to the third power end, the potential of the first node decreases to a low potential, the ninth transistor is turned off, and the voltage detection unit is turned off.
Optionally, the charge bleeding circuit further includes a fourth power supply end, a tenth transistor is connected between the fourth power supply end and the first power supply, a source of the tenth transistor is connected to the fourth power supply end, a drain of the tenth transistor is connected to the first power supply end, and a gate of the tenth transistor is connected to the third power supply end.
Optionally, the charge draining circuit further includes an eleventh transistor, a source of the eleventh transistor is connected to the first node, a drain of the eleventh transistor is connected to the fourth power source terminal, and a gate of the eleventh transistor is connected to the third power source terminal.
The charge leakage circuit comprises a first leakage unit, a second leakage unit and a voltage detection unit, wherein the control signal enables the voltage detection unit to be opened and opens the first leakage unit, and the charge of the first power supply end is discharged to the second power supply end through the first leakage unit. The potential of the first node is reduced along with the discharge of the first power end, when the potential is reduced to a safety value, the second discharging unit is opened, at the moment, the charge of the first power end passes through the second discharging unit to the third power end, and the voltage detecting unit is closed accordingly. In the invention, the voltage detection unit enables the charge of the first power supply end to be discharged to the second power supply end for a period of time and then to be discharged to the third power supply end, so that the discharge processes of the first power supply end to the second power supply end and the third power supply end are controlled, and the voltage detection unit is closed after a period of time, so that no static power consumption exists.
Drawings
FIG. 1 is a schematic diagram of a charge bleed-off circuit in the prior art;
FIG. 2 is a simulation diagram of a charge bleed-off process in the prior art;
FIG. 3 is a schematic diagram of a charge bleed-off circuit according to an embodiment of the present invention;
fig. 4 is a simulation diagram of a charge draining process in an embodiment of the invention.
Detailed Description
In order to solve the problem of erasing high-voltage leakage in the prior art, the inventor researches, and can also firstly discharge the erasing high-voltage to the ground end, and then discharge the erasing high-voltage to the working voltage end after a period of time. Referring to fig. 1, when the potential VDISC of the control terminal DISC rises to the high potential, the transistor N2 is turned on so that the voltage of the power source terminal VPP is discharged to the ground terminal VSS along the transistor P2, the transistor N1 and the transistor N2, as shown in fig. 2, during the erasing process in which the erase high voltage is supplied from the power source terminal VPP, and the charges of the power source terminal VPP are discharged after the erasing operation is completed. As the power supply terminal VPP drains a portion of the charge, the voltage of the power supply terminal VPP decreases, and the voltage of the power supply terminal VPUMP also decreases, so that the transistor P1 is turned on and the charge of the power supply terminal VPP is drained to the operating voltage VDD. Because the process that the power supply end VPP releases to the operating voltage VDD is uncontrollable, the discharge time process of the power supply end VPP to the ground end VSS is enabled, and the voltage of the operating voltage VDD is too small and lower than the required operating voltage.
In order to solve the above technical problem, the inventor has further developed a technical solution of the present invention, and the charge draining circuit provided by the present invention includes a first draining unit, a second draining unit and a voltage detecting unit, wherein a control signal causes the voltage detecting unit to turn on and turns on the first draining unit, and the charge at the first power end is drained to the second power end through the first draining unit. The potential of the first node is reduced along with the discharge of the first power end, when the potential is reduced to a safety value, the second discharging unit is opened, at the moment, the charge of the first power end passes through the second discharging unit to the third power end, and the voltage detecting unit is closed accordingly. In the invention, the voltage detection unit enables the charge of the first power supply end to be discharged to the second power supply end for a period of time and then to be discharged to the third power supply end, so that the discharge processes of the first power supply end to the second power supply end and the third power supply end are controlled, and the voltage detection unit is closed after a period of time, so that no static power consumption exists.
The charge bleeding circuit of the present invention is described in detail with reference to fig. 3 to 4, fig. 3 is a schematic diagram of the charge bleeding circuit, and fig. 4 is a simulation result diagram of the charge bleeding process.
Referring to fig. 3, the charge bleeding circuit of the present invention includes a first bleeding unit 10, a second bleeding unit 30, and a voltage detecting unit 20, the control signal DISC causes the voltage detecting unit 20 to be turned on, the first bleeding unit 10 is turned on after the voltage detecting unit 20 is turned on, and the charge of the first power source terminal VPP is discharged to the second power source terminal VSS through the first bleeding unit 10. The potential of the first node S1 drops with the leakage of the first power terminal VPP, and when it drops to a safe value, which refers to a safe voltage of the second bleeder unit 30 in the present invention, the second bleeder unit 30 is turned on. At this time, the charge of the first power source terminal VPP passes through the second discharging unit 30 to the third power source terminal VDD, and the voltage detecting unit 20 is then turned off.
Referring to fig. 3, in the present embodiment, the first discharging unit 10 is connected to the first power source terminal VPP, the second power source terminal VSS and the control signal DISC. Specifically, the first bleed unit 10 includes:
a first transistor M1, wherein a source of the first transistor M1 is connected to the first power source terminal VPP, a drain thereof is connected to the first node S1, and a gate thereof is connected to the voltage detecting unit 20, in this embodiment, the first transistor M1 is a PMOS transistor;
a second transistor M2, wherein a drain of the second transistor M2 is connected to the first node S1, a gate thereof is connected to the third power source terminal VDD, and a substrate thereof is connected to the second power source terminal VSS, in this embodiment, the second transistor M2 is an NMOS transistor;
and a first inverter 11, wherein an input end of the first inverter 11 is connected to the control signal DISC, and an output end of the first inverter 11 is connected to a source of the second transistor M2. The first inverter 11 includes a third transistor M3 and a fourth transistor M4, the source of the third transistor M3 is connected to the third power source terminal VDD, the drain is connected to the source of the second transistor M2, the gate is connected to the control signal DISC, the source of the fourth transistor M4 is connected to the second power source terminal VSS, the drain is connected to the source of the second transistor M2, and the gate is connected to the control signal DISC.
In addition, the first bleeder unit 10 further comprises a first resistor R1, the first resistor R1 being connected between the drain of the first transistor M1 and the drain of the second transistor M2.
In the present invention, when the control signal DISC controls the voltage detection unit 20 to turn on, the gate Voltage (VA) of the first transistor M1 is decreased, so that the first transistor M1 is turned on, and thus the first discharging unit 10 is turned on, and the charge of the first power source terminal VPP is discharged to the second power source terminal VSS.
With continued reference to fig. 3, in the present invention, the second bleeder unit 30 is connected to the first power supply terminal VPP and the third power supply terminal VDD, and to the first node S1 of the first bleeder unit 10. Specifically, the second bleeding unit 30 includes a fifth transistor M5, the source of the fifth transistor M5 is connected to the first power source terminal VPP, the drain is connected to the second power source terminal VSS, the gate is connected to the first node S1, and the fifth transistor M5 is a PMOS transistor. In addition, a second inverter 40 and a third inverter 50 are sequentially connected between the first node S1 and the gate of the fifth transistor M5, the second inverter 40 includes a twelfth transistor M12 and a thirteenth transistor M13, a source of the twelfth transistor M12 is connected to the first power source terminal VPP, a drain of the thirteenth transistor M13 is connected to the drain of the thirteenth transistor M13, a gate of the thirteenth transistor M13 is connected to the first node, a source of the thirteenth transistor M13 is connected to the second power source terminal VSS, a gate of the thirteenth transistor M48325 is connected to the first node S1, the third inverter 50 includes a fourteenth transistor M14 and a fifteenth transistor M15, a source of the fourteenth transistor M14 is connected to the first power source terminal, a drain of the fourteenth transistor M5 is connected to the gate of the fifth transistor M5, a gate of the thirteenth transistor M13 is connected to the drain of the thirteenth transistor M637, a source of the fifteenth transistor M15 is connected to the second power source terminal VSS, a drain of the.
With continued reference to fig. 3, in the present invention, the voltage detecting unit 20 is connected to the first node S1 for detecting the voltage of the first node S1, and specifically, the voltage detecting unit 20 includes:
a sixth transistor M6, wherein a source of the sixth transistor M6 is connected to the third power source terminal VDD, a drain thereof is connected to the first bleeder unit 10, a gate thereof is connected to the second node S2, and the sixth transistor M6 is a PMOS transistor;
a seventh transistor M7, a seventh transistor M7 having a source connected to the third power source terminal VDD, a drain connected to the second node S2, and a gate connected to the first node S1, wherein the seventh transistor M7 is a PMOS transistor;
a second resistor R2, a second resistor R2 is connected between the drain of the sixth transistor M6 and the second node S2;
an eighth transistor M8, wherein a drain of the eighth transistor M8 is connected to the second node S2, a gate thereof is connected to the control signal DISC, and the eighth transistor M8 is an NMOS transistor;
a ninth transistor M9, a ninth transistor M9 having a source connected to the second power source terminal VSS, a drain connected to the drain of the eighth transistor M8, and a gate connected to the first node S1, wherein the ninth transistor M9 is an NMOS transistor.
When the voltage of the first node S1 continuously drops while the charge of the first power terminal VPP is discharged to the second power terminal through the first discharging unit 10, the fifth transistor M5 is turned on when the voltage of the first node S1 drops to a safe value, that is, a safe voltage of the fifth transistor M5, so that the second discharging unit 30 is turned on, and the charge of the first power terminal VPP is discharged to the second power terminal VSS through the fifth transistor M5.
In addition, the charge draining circuit further includes a fourth power source terminal VPP, a tenth transistor M10 is connected between the fourth power source terminal VPP and the first power source terminal VPP, a source of the tenth transistor M10 is connected to the fourth power source terminal VPP, a drain thereof is connected to the first power source terminal VPP, and a gate thereof is connected to the third power source terminal VDD. And, the charge draining circuit further includes an eleventh transistor M11 having a source connected to the first node S1, a drain connected to the fourth power source terminal VPUMP, and a gate connected to the third power source terminal VDD, for draining the charge of the fourth power source terminal VPUMP to the second power source terminal VSS.
The operation of the voltage bleeder circuit is further described with reference to fig. 3 and 4, and the operation is as follows:
in a time period T1, when the control signal DISC is at a low voltage level, the first power supply terminal VPP is at an erasing high voltage level, and the third power supply terminal VDD is at a working voltage level, the eighth transistor M8 is turned off, the gate voltage VA of the first transistor M1 is at a high voltage level, and the first transistor M1 is turned off, so that the first discharging unit 10 is turned off, and the voltages of the first power supply terminal VPP, the third power supply terminal VDD, and the fourth power supply terminal VPP are all unchanged;
in the period of T2, when the control signal DISC rises to the high potential, the eighth transistor M8 is turned on, so that the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 are all turned on, so that the voltage detection circuit 20 is turned on, the drain potential of the sixth transistor M6 is reduced accordingly, the gate voltage VA of the first transistor M1 is reduced, the first transistor M1 is turned on, so that the first discharging unit 10 is turned on, the charge of the first power source terminal VPP is discharged to the second power source terminal VSS through the first transistor M1 and the second transistor M2, the voltage of the first power source terminal VPP is reduced, and in addition, the charge of the fourth power source terminal VPP is discharged to the second power source terminal VSS along with the eleventh transistor M11 and the second transistor M2, and the voltage of the fourth power source terminal VPP is also reduced;
in the T3 time period, as the charge of the first power source terminal VPP is discharged to the second power source terminal VSS, the potential Vdet of the first node S1 drops and falls to the safe value, i.e., the safe voltage of the fifth transistor M5, so that the fifth transistor M5 is turned on, and thus the second discharging circuit 30 is turned on, the charge of the first power source terminal VPP is discharged to the third power source terminal VDD through the fifth transistor M5, and the voltage of the third power source terminal VDD rises. At this time, the potential Vdet of the first node S1 drops to a low potential, and the ninth transistor M9 is turned off, so that the voltage detection unit 20 is turned off, and thus the voltage detection circuit 20 does not have static power consumption during a subsequent charge draining process.
It should be noted that the voltage Vdet of the first node S1 is mainly determined by the currents flowing through the first transistor M1 and the second transistor M2, wherein,
the current of the first transistor M1 is:
where Cox is the capacitance of the gate oxide of the first transistor M1, WM1/LM1 is the width-to-length ratio of the first transistor M1, and Vthp is the threshold voltage of the first transistor M1.
The current of the second transistor M2 is:
cox is the capacitance of the I-gate oxide of the second transistor M2, WM2/LM2 is the width-to-length ratio of the second transistor M2, and Vthn is the threshold voltage of the second transistor M2.
In the present invention, when the current IM2 of the second transistor M2 is smaller than the current IM1 of the first transistor M1, the voltage of the first node S1 approaches the first power source terminal VPP, electric charges mainly flow from the first power source terminal VPP to the third power source terminal VSS, whereas, the voltage of the first node S1 approaches the second power source terminal VSS, electric charges mainly flow from the first power source terminal VPP to the third power source terminal VDD, so that the discharge of the first power source terminal VPP can be controlled by controlling the currents of the first transistor M1 and the second transistor M2. Further, suppose thatThe first power source terminal VPP is Tx × VDD + VA-Tx × Vthn + Vthp, and the gate voltage VA of the sixth transistor M6 is VGSM6-IM6 × R2. VGSM6 is the voltage between the gate and the source of the sixth transistor M6, and IM6 is the current of the sixth transistor M6, so that the on-time of the second bleeder circuit 30 and the time of the first power supply terminal VPP to the third power supply terminal VDD can be controlled by controlling the width-to-length ratio of the first transistor M1 and the second transistor M2, and the voltage of the first power supply terminal VPP approaches the safe voltage of the third power supply terminal VDD. The safe transition from the discharge of the second power supply terminal VSS to the discharge of the third power supply terminal VDD is ensured, and the jump of the third power supply terminal VDD can be effectively inhibited. And, in particularThe aspect ratio of the first transistor M1 and the second transistor M2 can be set according to the needs of the actual circuit.
In summary, the charge draining circuit provided by the present invention includes a first draining unit, a second draining unit and a voltage detecting unit, wherein the control signal turns on the voltage detecting unit and turns on the first draining unit, and the charge at the first power end is drained to the second power end through the first draining unit. The potential of the first node is reduced along with the discharge of the first power end, when the potential is reduced to a safety value, the second discharging unit is opened, at the moment, the charge of the first power end passes through the second discharging unit to the third power end, and the voltage detecting unit is closed accordingly. In the invention, the voltage detection unit enables the charge of the first power supply end to be discharged to the second power supply end for a period of time and then to be discharged to the third power supply end, so that the discharge processes of the first power supply end to the second power supply end and the third power supply end are controlled, and the voltage detection unit is closed after a period of time, so that no static power consumption exists.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (13)
1. A charge bleed circuit, comprising:
the first discharging unit is connected with a first power end, a second power end and a control signal, when the control signal controls the first discharging unit to be opened, the charge of the first power end is discharged to the second power end, and the first discharging unit is provided with a first node;
the second bleeder unit is connected with the first power supply end and a third power supply end and connected to the first node;
and the voltage detection unit is connected to the first node and is used for detecting the voltage of the first node, when the voltage of the first node is reduced to a safe value, the second discharge unit is opened, and the charge of the first power supply end is discharged to the third power supply end.
2. The charge bleeding circuit of claim 1, wherein the first bleeding unit comprises:
a first transistor, wherein a source electrode is connected with the first power supply end, a drain electrode is connected with the first node, and a grid electrode is connected with the voltage detection unit;
a second transistor having a drain connected to the first node and a gate connected to the third power supply terminal;
and the input end of the first phase inverter is connected with the control signal, and the output end of the first phase inverter is connected with the source electrode of the second transistor.
3. The charge bleed circuit of claim 2, wherein the first inverter comprises a third transistor having a source connected to the third power supply terminal, a drain connected to the source of the second transistor, and a gate connected to the control signal, and a fourth transistor having a source connected to the second power supply terminal, a drain connected to the source of the second transistor, and a gate connected to the control signal.
4. The charge bleeding circuit of claim 2, wherein the first bleeding unit further comprises a first resistor connected between the drain of the first transistor and the drain of the second transistor.
5. The charge bleed-off circuit of claim 2, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.
6. The charge bleeding circuit of claim 1, wherein the second bleeding unit comprises a fifth transistor having a source connected to the first power supply terminal, a drain connected to the third power supply terminal, and a gate connected to the first node.
7. The charge bleed circuit of claim 6, wherein a second inverter and a third inverter are connected in sequence between the first node and the gate of the fifth transistor.
8. The charge bleed-off circuit of claim 6, wherein the fifth transistor is a PMOS transistor.
9. The charge bleed-off circuit of claim 1, wherein the voltage detection unit comprises:
a sixth transistor having a source connected to the third power terminal, a drain connected to the first bleeder unit, and a gate connected to the second node;
a seventh transistor having a source connected to the third power source terminal, a drain connected to the second node, and a gate connected to the first node;
a second resistor connected between the drain of the sixth transistor and the second node;
an eighth transistor having a drain connected to the second node and a gate connected to the control signal;
a ninth transistor having a source connected to the second power source terminal, a drain connected to the source of the eighth transistor, and a gate connected to the first node.
10. The charge bleed-off circuit of claim 9, wherein the sixth transistor and the seventh transistor are PMOS transistors and the eighth transistor and the ninth transistor are NMOS transistors.
11. The charge bleeding circuit according to claim 9, wherein when the control signal rises to a high potential, the eighth transistor is turned on, the voltage detecting unit is turned on, the potential of the sixth transistor falls, the first bleeding unit is turned on, the charge of the first power source terminal is bled off to the second power source terminal, the potential of the first node falls, and when the potential falls to the safe value, the second bleeding circuit is turned on, the charge of the first power source terminal is bled off to the third power source terminal, the potential of the first node falls to a low potential, the ninth transistor is turned off, and the voltage detecting unit is turned off.
12. The charge bleeding circuit as recited in claim 1, further comprising a fourth power supply terminal, a tenth transistor connected between said fourth power supply terminal and said first power supply, said tenth transistor having a source connected to said fourth power supply terminal, a drain connected to said first power supply terminal, and a gate connected to said third power supply terminal.
13. The charge bleeding circuit as recited in claim 12, further comprising an eleventh transistor having a source connected to the first node, a drain connected to the fourth power supply terminal, and a gate connected to the third power supply terminal.
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| CN201610318329.1A CN107370351B (en) | 2016-05-13 | 2016-05-13 | Charge bleeding circuit |
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| CN201610318329.1A CN107370351B (en) | 2016-05-13 | 2016-05-13 | Charge bleeding circuit |
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| CN107370351A CN107370351A (en) | 2017-11-21 |
| CN107370351B true CN107370351B (en) | 2019-12-27 |
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| CN113364257B (en) * | 2021-05-11 | 2022-06-03 | 中天恒星(上海)科技有限公司 | Bleeder circuit, power conversion circuit, electronic device and bleeder method |
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| CN107370351A (en) | 2017-11-21 |
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