CN111312313B - Circuit for quickly switching voltage of charge pump - Google Patents
Circuit for quickly switching voltage of charge pump Download PDFInfo
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- CN111312313B CN111312313B CN201811519988.7A CN201811519988A CN111312313B CN 111312313 B CN111312313 B CN 111312313B CN 201811519988 A CN201811519988 A CN 201811519988A CN 111312313 B CN111312313 B CN 111312313B
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- charge pump
- nmos tube
- discharge
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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Abstract
The invention relates to a circuit for quickly switching voltage of a charge pump, belonging to the field of nonvolatile memories, and the circuit comprises: the discharge control device comprises a charge pump module, a control switch signal module and a discharge module, wherein the charge pump module is respectively connected with the control switch signal module and the discharge module, the control switch signal module is respectively connected with the charge pump module and the discharge module and used for controlling the discharge current of the discharge module, and the discharge module is respectively connected with the charge pump module and the control switch signal module and used for discharging the charge pump module. The circuit for quickly switching the voltage of the charge pump controls two different discharge currents to work when the high voltage is reduced to the low voltage when the nonvolatile memory is switched, so that the high voltage is directly discharged to the low voltage.
Description
Technical Field
The invention relates to the field of nonvolatile memories, in particular to a charge pump voltage fast switching circuit.
Background
Currently, the nonvolatile memory is basically provided with a working voltage meeting the operation requirement by a charge pump, the charge pump is a switched capacitor voltage converter, the direct current converter which utilizes a so-called 'fast' or 'pumping' capacitor instead of an inductor or a transformer to store energy can increase or decrease the input power voltage, and can also be used for generating negative voltage, and a MOS switch array in the direct current converter can control the charging and discharging of the fast capacitor in a certain mode, so that the input voltage is multiplied or decreased by a certain factor (1/2,2 or 3) to obtain the required output voltage.
In the prior art, when various operations are performed on a nonvolatile memory, the required voltage value is different, that is, the voltage value output by the charge pump is switched between the required target high voltage and the required target low voltage, and the switching is very frequent, and generally, the switching step from the required target high voltage to the required target low voltage is: when the high voltage output by the charge pump is the required target high voltage, the power supply voltage is discharged firstly, and then the required target low voltage is charged by the power supply voltage, so that a large amount of time is wasted in the process.
The charge pump voltage fast switching circuit of the existing nonvolatile memory is shown as figure 1 in the attached drawing of the specification, and the working principle is as follows: the output voltage VOUT of the charge pump 12 is divided by resistors to obtain VFB, the VFB is compared with a reference voltage VREF, the voltage comparator 10 generates an EN signal to control whether the clock circuit 11 generates a clock trigger signal to the charge pump 12, if VOUT is higher than a required voltage value, EN is a low level, the charge pump 12 does not work, if VOUT is lower than the required voltage value, EN is a high level, the charge pump 12 starts to work, when voltage switching is carried out, when VOUT is higher than the required voltage value, high voltage needs to be switched to low voltage, at the moment, EN is a low level, the charge pump 12 does not work, the output is slowly discharged downwards through a resistor string, and the charge pump 12 works again until the output is lower than a target voltage value. Generally, in order to ensure the output efficiency and power consumption of the charge pump system, the discharge resistor has a large resistance value and a small leakage current, and the discharge capability of the charge pump system with a large capacitive output load is weak, when the output voltage value VOUT of the charge pump 12 is switched from a high level to a low level, if only the leakage current flows through the discharge resistor, a long time is needed, and generally, the high level needs to be discharged to a power supply or ground first, and then the high level needs to be driven to a required lower voltage value again, but the driving process still needs a long time. Referring to fig. 2, a waveform diagram of the prior art circuit in operation is shown, where VDD is a power voltage, V1 is a desired target low voltage, V2 is a desired target high voltage, and a solid black line in the diagram is a VOUT waveform of the prior art circuit, where the VOUT waveform is discharged from the desired target high voltage V2 to the power VDD and then hits the desired target low voltage V1 again, which requires a long time for operation, and seriously affects the operating efficiency of the nonvolatile memory.
Disclosure of Invention
In view of the above problems, the present invention provides a circuit for fast switching a charge pump voltage, which solves the problem in the prior art that the charge pump needs to discharge to the power supply voltage first when switching the voltage.
The embodiment of the invention provides a circuit for quickly switching voltage of a charge pump, which is applied to a nonvolatile memory and comprises:
the device comprises a charge pump module, a control switch signal module and a discharging module;
the charge pump module is respectively connected with the control switch signal module and the discharge module and is used for providing voltage for various operations of the nonvolatile memory;
the control switch signal module is respectively connected with the charge pump module and the discharge module and is used for controlling the discharge current of the discharge module according to a work enabling signal, a voltage reduction enabling signal and an output signal of a voltage comparator in the charge pump module, and the work enabling signal and the voltage reduction enabling signal are sent out by a control module of the nonvolatile memory;
the discharging module is respectively connected with the charge pump module and the control switch signal module and is used for discharging the charge pump module, so that the voltage provided by the charge pump module is reduced to a target low voltage from a target high voltage, the target high voltage is the voltage required by the current operation of the nonvolatile memory, and the target low voltage is the voltage required by the next operation of the nonvolatile memory.
Optionally, the charge pump module comprises: the voltage comparator, the clock circuit, the charge pump and the comparison voltage circuit;
the voltage comparator comprises a reference voltage connecting end, a comparison voltage connecting end and an output end;
the reference voltage connection end is connected with a reference voltage, the comparison voltage connection end is connected with the comparison voltage circuit, the output end of the voltage comparator is respectively connected with the control switch signal module and the clock circuit and used for providing a discharge enabling signal for the control switch signal module and providing a trigger signal for the clock circuit, and the discharge enabling signal is used for the control switch signal module to generate a signal for controlling the discharge module;
the output end of the clock circuit is connected with the input end of the charge pump and is used for providing a clock signal for the charge pump;
the output end of the charge pump is respectively connected with the comparison voltage circuit and the discharge module and used for providing voltage for various operations of the nonvolatile memory;
and the comparison voltage circuit is connected with a comparison voltage connecting end of the voltage comparator and is used for providing comparison voltage for the voltage comparator.
Optionally, the circuit for fast switching of the charge pump voltage is applied to a nonvolatile memory, and the nonvolatile memory further comprises a control module;
the control module is connected with the control switch signal module, and is used for sending a work enabling signal and a voltage reduction enabling signal to the control switch signal module, wherein the work enabling signal and the voltage reduction enabling signal are used for the control switch signal module to generate a signal for controlling the discharging module.
Optionally, the discharge module comprises: the device comprises a mirror current module, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube;
the mirror current module is respectively connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube and is used for providing a standard value of a discharge current value for the discharge module, and the standard value is the magnitude of the mirror current in the mirror current module;
the grid electrode of the first NMOS tube is connected with the control switch signal module, the drain electrode of the first NMOS tube is connected with the output end of the charge pump module, and the source electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube and is used for generating a first discharge current when the first NMOS tube is conducted;
the grid electrode of the second NMOS tube is connected with the control switch signal module, the drain electrode of the second NMOS tube is connected with the output end of the charge pump module, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube and used for generating a second discharge current when the second NMOS tube is conducted;
the grid electrode of the third NMOS tube is connected with the mirror current module, the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube, and the source electrode of the third NMOS tube is grounded and used for enabling the first discharge current to be discharged by multiplying the current by the standard value;
the grid electrode of the fourth NMOS tube is connected with the mirror current module, the drain electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube, and the source electrode of the fourth NMOS tube is grounded and used for enabling a second discharge current to be discharged by multiplying the current by the standard value.
Optionally, the control switch signal module includes: the first NAND gate, the second NAND gate, the first inverter, the second inverter, the third inverter and the fourth inverter;
two input signals of the first nand gate are the working enable signal and the voltage reduction enable signal respectively, and an input end signal of the third inverter is the discharge enable signal;
the output end of the first NAND gate is connected with the input end of the first inverter;
the output end of the first inverter is respectively connected with one input end of the second NAND gate, the input end of the second inverter and the grid electrode of the first NMOS tube;
the output end of the second inverter is connected with the mirror current module;
the output end of the third inverter is connected with the other input end of the second NAND gate;
the output end of the second NAND gate is connected with the fourth inverter;
and the output end of the fourth inverter is connected with the grid electrode of the second NMOS tube.
Optionally, the comparison voltage circuit comprises: a plurality of series resistors;
one end of a first resistor in the plurality of series resistors is connected with the output end of the charge pump, the other end of the first resistor is connected with the comparison voltage connecting end of the voltage comparator and one end of a second resistor, and the other end of the second resistor is connected with one end of any resistor except the first resistor and the second resistor in the plurality of series resistors.
Optionally, when the operation enable signal, the step-down enable signal, and the discharge enable signal are at a high level, the first NMOS transistor is turned on;
and when the working enabling signal and the voltage reduction enabling signal are at high level and the discharge enabling signal is at low level, the first NMOS tube and the second NMOS tube are simultaneously conducted.
Optionally, the first discharge current is less than the second discharge current.
Compared with the prior art, the charge pump voltage fast switching circuit provided by the invention has the advantages that when the nonvolatile memory is subjected to switching operation, when the voltage required by next operation is smaller than the voltage required by current operation, namely the target high voltage is reduced to the target low voltage, the switching signal module is controlled to discharge by controlling the discharging module according to the work enabling signal, the voltage reduction enabling signal and the discharging enabling signal and according to the sum of the first discharging current and the second discharging current, so that the target high voltage is directly discharged to the target low voltage.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a circuit diagram of a prior art charge pump;
fig. 2 is a graph of a prior art charge pump output voltage waveform;
FIG. 3 is a block diagram of a charge pump fast switching circuit according to the present invention;
FIG. 4 is a circuit diagram of a charge pump fast switch of the present invention;
FIG. 5 is a waveform diagram of the output voltage of a charge pump fast switching circuit according to the present invention;
fig. 6 is a waveform diagram of the output voltage when one state of the charge pump fast switching circuit of the present invention occurs.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Referring to fig. 3, a block schematic diagram of a charge pump voltage fast switching circuit is shown, which may specifically include:
a charge pump module 20, a control switch signal module 40, and a discharge module 30.
The charge pump module 20 is respectively connected to the control switch signal module 40 and the discharge module 30, and is configured to provide voltages for various operations of the nonvolatile memory, the control switch signal module 40 is respectively connected to the charge pump module 20 and the discharge module 30, and is configured to control a discharge current of the discharge module 30 according to a work enable signal, a step-down enable signal, and an output signal of a voltage comparator in the charge pump module 20, the discharge module 30 is respectively connected to the charge pump module 20 and the control switch signal module 40, and is configured to discharge the charge pump module 20, so that the voltage provided by the charge pump module 20 is reduced from a target high voltage to a target low voltage, where the target high voltage is a voltage required by a current operation of the nonvolatile memory, and the target low voltage is a voltage required by a next operation of the nonvolatile memory, it should be noted that, if the voltage required by the next operation of the nonvolatile memory is higher than the voltage required by the current operation, the discharging module 30 does not work, and the charge pump module 20 repeatedly pumps the voltage until the voltage required by the next operation is reached.
Alternatively, referring to fig. 4, the charge pump module 20 in the circuit of the present invention includes: a voltage comparator 201, a clock circuit 202, a charge pump 203, and a comparison voltage circuit 204.
The voltage comparator 201 comprises a reference voltage connecting end, a comparison voltage connecting end and an output end, the reference voltage connecting end is connected with a reference voltage VREF, the comparison voltage connecting end is connected, the output end of the voltage comparator 201 is respectively connected with the input end of the clock circuit 202 and the input end of the control switch signal module 40 and used for providing trigger signals for the clock circuit 202 and the control switch signal module 40, when the reference voltage VREF is larger than the comparison voltage, the voltage comparator 201 outputs a high level signal, and when the reference voltage VREF is smaller than the comparison voltage, the voltage comparator 201 outputs a low level signal.
The output of the clock circuit 202 is connected to the input of the charge pump 203 for providing a clock signal to the charge pump 203.
The charge pump 203 is connected to the comparison voltage circuit 204 and the control switch signal module 40, respectively, the charge pump 203 can output a voltage according to the clock signal of the clock circuit 202, and the output terminal of the charge pump 203 is the output terminal of the charge pump module 20.
The comparison voltage circuit 204 comprises two series resistors, wherein one end of a first resistor in the two series resistors is connected with the output end of the charge pump 203, the other end of the first resistor is connected with a comparison voltage connection end of the voltage comparator 201, the other end of the second resistor is connected with the ground, the comparison voltage circuit 204 is used for providing comparison voltage for the voltage comparator 201, and the comparison voltage circuit is also used for rapidly discharging the output voltage VOUT when the charge pump 203 stops working.
Optionally, referring to fig. 4, the circuit for fast switching of the charge pump voltage is applied to a memory, the memory further includes a control module 50, the control module 50 is connected to the control switch signal module 40, and the control module 50 is configured to send an operation enable signal and a step-down enable signal to the control switch signal module 40, and the operation enable signal and the step-down enable signal are used to control the switch signal module 40 to generate a signal for controlling the discharge module 30.
Alternatively, referring to fig. 4, the discharge module 30 in the circuit of the present invention includes: a first NMOS transistor 401, a second NMOS transistor 402, a third NMOS transistor 403, a fourth NMOS transistor 404, and a mirror current module 405.
The drain of the first NMOS transistor 401 is connected to the charge pump 203 and the drain of the second NMOS transistor 402, the gate of the first NMOS transistor 401 is connected to the control switch signal module 40, the source of the first NMOS transistor 401 is connected to the drain of the third NMOS transistor 403, and the first NMOS transistor 401 is used to generate a first discharge current under the combined action of the third NMOS transistor 403 when the first NMOS transistor 401 is turned on.
The gate of the second NMOS transistor 402 is connected to the control switch signal module 40, the drain of the second NMOS transistor 402 is connected to the charge pump 203, and the source of the second NMOS transistor 402 is connected to the drain of the fourth NMOS transistor 404, for generating a second discharge current under the combined action of the second NMOS transistor 402 and the fourth NMOS transistor 404 when the second NMOS transistor 402 is turned on.
The gate of the third NMOS transistor 403 is connected to the mirror current module 405, the drain of the third NMOS transistor 403 is connected to the source of the first NMOS transistor 401, and the source of the third NMOS transistor 403 is grounded, so that when the third NMOS transistor 403 is turned on, the first discharging current is discharged by a current multiplied by the mirror current in the mirror current module 405.
The gate of the fourth NMOS transistor 404 is connected to the mirror current module 405, the drain of the fourth NMOS transistor 404 is connected to the source of the second NMOS transistor 402, and the source of the fourth NMOS transistor 404 is grounded, so that when the fourth NMOS transistor 404 is turned on, the second discharging current is discharged by multiplying the mirror current in the mirror current module 405 by the current.
The mirror current module 405 includes: the PMOS transistor 4051 and the fifth NMOS transistor 4052, the source of the PMOS transistor 4051 is connected to the mirror current generated by the current mirror circuit, the gate of the PMOS transistor 4501 is connected to the control switch signal module 30, the drain of the PMOS transistor 4051 is connected to the drain of the fifth NMOS transistor 4052 and the gate of the fifth NMOS transistor 4052, and the PMOS transistor 4051 is used for providing a standard value of the current magnitude for the first discharge current and the second discharge current when conducting, and the standard value is the magnitude of the mirror current.
The drain of the fifth NMOS tube 4052 is connected to the drain of the PMOS tube 4051 and the gate of the fifth NMOS tube, the gate of the fifth NMOS tube 4052 is connected to the third NMOS tube 403 and the fourth NMOS tube 404, the source of the fifth NMOS tube 4052 is grounded, and the fifth NMOS tube 4052 is configured to generate a first discharge current and a second discharge current under the combined action of the third NMOS tube 403 and the fourth NMOS tube 404.
According to the mirror current principle, the third NMOS transistor 403 can discharge at a low power, i.e., within 2 times the magnitude of the reference bias current, and the fourth NMOS transistor 404 can discharge at a high power, i.e., within 8 times the magnitude of the reference bias current. It should be noted that the data is obtained through simulation experiments and is applicable to a discharge current in a general situation, and does not represent all standards of the nonvolatile memory, and the embodiment of the present invention is not particularly limited thereto.
Alternatively, referring to fig. 4, the switch signal control module 40 in the circuit of the present invention includes: a first nand gate nand1, a second nand gate nand2, a first inverter inv1, a second inverter inv2, a third inverter inv3 and a fourth inverter inv 4.
Two input signals of the first nand gate nand1 are respectively a working enable signal PUMP _ EN and a voltage reduction enable signal DISC _ EN, an input signal of the third inverter inv3 is a discharge enable signal EN, the discharge enable signal EN is output by the voltage comparator 201, an output end of the first nand gate nand1 is connected with an input end of the first inverter inv1, an output end of the first inverter inv1 is respectively connected with one input end of the second nand gate nand2, an input end of the second inverter inv2 and a gate of the first NMOS tube 401, an output end of the second inverter inv2 is connected with a gate of the PMOS tube 4051, an output end of the third inverter inv3 is connected with the other input end of the second nand gate 2, an output end of the second nand gate 2 is connected with a fourth inverter inv4, and an output end of the fourth inverter inv4 is connected with a gate of the second NMOS tube 402.
When the operation enable signal PUMP _ EN, the step-down enable signal DISC _ EN, and the discharge enable signal EN are at high levels, the first NMOS transistor 401 is turned on, and discharges with a first current, wherein the operation enable signal PUMP _ EN is a control signal of the charge PUMP 203, and is generally set to be at high level when the whole charge PUMP system is required to operate, the operation enable signal PUMP _ EN is at high level when the whole charge PUMP system operates, the step-down enable signal DISC _ EN is an enable signal sent by the controller when the output voltage VOUT decreases from a target high voltage value to a target low voltage value, the discharge enable signal EN is an output signal of the voltage comparator 201, when EN is 0, it indicates that the VOUT voltage is higher than a required voltage value, the discharge module 30 discharges with the first current plus the second current, when EN is 1, it indicates that VOUT is lower than the required voltage value, and at this time, the charge PUMP 203 starts to operate, at the same time, the discharging module 30 discharges with the first discharging current, so that the voltage ripple of the voltage output by the charge pump 203 is smaller.
In addition, the circuit has the advantage that when large current is used for discharging, the required low voltage is not discharged, if the output EN of the voltage comparator 201 is turned over by mistake due to some factors, namely when the target high voltage is not discharged to the target low voltage by large current discharging, the EN jumps to the high level, the charge pump 203 starts to work, and the existence of small discharging current can ensure that the voltage of the charge pump 203 is not overhigh.
When the operation enable signal PUMP _ EN and the voltage drop enable signal DISC _ EN are at a high level and the discharge enable signal EN is at a low level, the first NMOS transistor 401 and the second NMOS transistor 402 are simultaneously turned on, and at this time, the first current and the second current are simultaneously discharged. The control switch signal module 30 in the above embodiment may also be composed of circuits formed by other electrical components, and the embodiments of the present invention are not limited thereto, and any circuit capable of implementing the above functions falls within the scope of the present invention.
In summary, comparing fig. 4 with the circuit diagram 1 of the prior art, the working principle of the circuit of the present invention is: when the nonvolatile memory works, the output VOUT is divided by a resistor to obtain VFB, the VFB is compared with a reference voltage VREF, the voltage comparator 201 generates an EN signal to control whether the clock circuit 202 generates a clock trigger signal to the charge pump 203, if VOUT is higher than a required voltage value, EN is at a low level, the charge pump 12 does not work, if VOUT is lower than the required voltage value, EN is at a high level, the charge pump 12 starts working, when the output VOUT is higher than the required voltage value, the target high voltage needs to be switched to the target low voltage, at this time, the voltage reduction enable signal DISC _ EN and the operation enable signal PUMP _ EN are high level, EN is low level, the charge PUMP 203 does not operate, the discharge module 30 starts to operate, the PMOS transistor 4051, the first NMOS transistor 401 and the second NMOS transistor 402 are simultaneously turned on, and at this time, the discharge module 30 discharges with the current magnitude of the sum of the first discharge current and the second discharge current. When output VOUT is lower than a required voltage value, the voltage reduction enabling signal DISC _ EN and the work enabling signals PUMP _ EN and EN are all high levels, at the moment, the charge PUMP 203 starts to work, the PMOS tube 4051 and the first NMOS tube 401 are conducted, the second NMOS tube 402 is turned off, the first discharging current works, the second discharging current does not work, the first discharging current ensures that the voltage of VOUT cannot be too high, and the voltage ripple is small. Referring to fig. 5, which shows a waveform diagram of the circuit of the present invention during operation, wherein VDD is a power voltage, V1 is a desired target low voltage, V2 is a desired target high voltage, a solid black line in the diagram is a VOUT waveform of the circuit of the prior art, and a dashed line portion is a VOUT waveform of the circuit of the present invention, in combination with the above-mentioned operating principle of the circuit, when the operating voltage of the charge PUMP 203 reaches a desired target high level V2, and if the desired target voltage of the next operation is a low level V1, the operation enable signal PUMP _ EN and the step-down enable signal DISC _ EN are at high levels, the discharge enable signal EN is at low level, the discharge module 30 starts to operate, the PMOS transistor 4051, the first NMOS transistor 401 and the second NMOS transistor 402 are simultaneously turned on, the discharge module 30 discharges the target high voltage V2 at the same time with the sum of the first discharge current and the second discharge current, and when the output VOUT reaches the desired target low voltage, the voltage reduction enable signal DISC _ EN and the work enable signals PUMP _ EN and EN are all high level, at this time, the charge PUMP 203 starts to work, the PMOS transistor 4051 and the first NMOS transistor 401 are turned on, the second NMOS transistor 402 is turned off, the first discharge current works, the second discharge current does not work, and the first discharge current ensures that the voltage of VOUT reaches the required low voltage V1 and the voltage ripple is small. The above process enables the high voltage V2 to be discharged directly to the required low voltage V1, saving operating time. Referring to fig. 6, which shows a waveform diagram of the circuit of the present invention when the output signal EN of the voltage comparator 201 is flipped by mistake, assuming that the output EN of the voltage comparator 201 is flipped by mistake due to some factors, it can be seen intuitively that during the period when the enable signal DISC _ EN is at a high level (t1-t4), assuming that the output EN signal of the voltage comparator 201 is flipped at a high level at a time t2, the output EN signal jumps to a low level at a time t3, and a black solid line represents a waveform when there is no first current discharge path: during the period from t1 to t2, the output is rapidly discharged; during the period t2-t3, EN is high, charge pump 203 starts to operate normally, its output VOUT will be charged to a higher level, and after EN jumps low at time t3, the output will be discharged quickly again, but VOUT cannot be discharged to the desired target low voltage V1 before t4, which affects the accuracy of the nonvolatile memory operation. The dashed line shows the waveform that the first discharge current discharge path always exists: during the period from t2 to t3, the charge pump 203 drives VOUT upwards, and the first discharging current discharges VOUT, so that VOUT voltage is not driven too high, and when EN is driven low, the first discharging current and the second discharging current discharge VOUT to the desired target low voltage V1, so that the nonvolatile memory operates normally, thereby ensuring the correctness of operation and saving the operation time.
Through the embodiment, when a user uses the nonvolatile memory and the nonvolatile memory is switched, two different discharge currents are controlled to work in the process of reducing the required target high voltage to the required target low voltage, so that the required target high voltage is directly discharged to the required target low voltage.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The above detailed description is provided for the circuit for fast switching the voltage of the charge pump, and the specific examples are applied herein to explain the principle and the implementation of the present invention, and the above description of the embodiments is only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. A circuit for fast switching of charge pump voltage, which is applied to a nonvolatile memory, the circuit comprising:
the device comprises a charge pump module, a control switch signal module and a discharging module;
the charge pump module is respectively connected with the control switch signal module and the discharge module and is used for providing voltage for various operations of the nonvolatile memory;
the control switch signal module is respectively connected with the charge pump module and the discharge module and is used for controlling the discharge current of the discharge module according to a work enabling signal, a voltage reduction enabling signal and an output signal of a voltage comparator in the charge pump module, and the work enabling signal and the voltage reduction enabling signal are sent out by a control module of the nonvolatile memory;
the discharging module is respectively connected with the charge pump module and the control switch signal module, wherein the discharging module comprises: the charge pump module is used for discharging, so that voltage provided by the charge pump module is reduced to target low voltage from target high voltage, the target high voltage is voltage required by the nonvolatile memory when the nonvolatile memory is operated currently, and the target low voltage is voltage required by the nonvolatile memory when the nonvolatile memory is operated next time.
2. The circuit of claim 1, wherein the charge pump module comprises: the voltage comparator, the clock circuit, the charge pump and the comparison voltage circuit;
the voltage comparator comprises a reference voltage connecting end, a comparison voltage connecting end and an output end;
the reference voltage connection end is connected with a reference voltage, the comparison voltage connection end is connected with the comparison voltage circuit, the output end of the voltage comparator is respectively connected with the control switch signal module and the clock circuit and used for providing a discharge enabling signal for the control switch signal module and providing a trigger signal for the clock circuit, and the discharge enabling signal is used for the control switch signal module to generate a signal for controlling the discharge module;
the output end of the clock circuit is connected with the input end of the charge pump and is used for providing a clock signal for the charge pump;
the output end of the charge pump is respectively connected with the comparison voltage circuit and the discharge module and used for providing voltage for various operations of the nonvolatile memory;
and the comparison voltage circuit is connected with a comparison voltage connecting end of the voltage comparator and is used for providing comparison voltage for the voltage comparator.
3. The circuit of claim 1, wherein the circuit for charge pump voltage fast switching is applied to a non-volatile memory, the non-volatile memory further comprising a control module;
the control module is connected with the control switch signal module, and is used for sending a work enabling signal and a voltage reduction enabling signal to the control switch signal module, wherein the work enabling signal and the voltage reduction enabling signal are used for the control switch signal module to generate a signal for controlling the discharging module.
4. The circuit of claim 1, further comprising:
the mirror current module is respectively connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube and is used for providing a standard value of a discharge current value for the discharge module, and the standard value is the magnitude of the mirror current in the mirror current module;
the grid electrode of the first NMOS tube is connected with the control switch signal module, the drain electrode of the first NMOS tube is connected with the output end of the charge pump module, and the source electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube and is used for generating a first discharge current when the first NMOS tube is conducted;
the grid electrode of the second NMOS tube is connected with the control switch signal module, the drain electrode of the second NMOS tube is connected with the output end of the charge pump module, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube and used for generating a second discharge current when the second NMOS tube is conducted;
the grid electrode of the third NMOS tube is connected with the mirror current module, the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube, and the source electrode of the third NMOS tube is grounded and used for enabling the first discharge current to be discharged by multiplying the current by the standard value;
the grid electrode of the fourth NMOS tube is connected with the mirror current module, the drain electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube, and the source electrode of the fourth NMOS tube is grounded and used for enabling a second discharge current to be discharged by multiplying the current by the standard value.
5. The circuit of claim 1, wherein the control switch signal module comprises: the first NAND gate, the second NAND gate, the first inverter, the second inverter, the third inverter and the fourth inverter;
two input signals of the first nand gate are the working enable signal and the voltage reduction enable signal respectively, and an input end signal of the third inverter is a discharge enable signal;
the output end of the first NAND gate is connected with the input end of the first inverter;
the output end of the first inverter is respectively connected with one input end of the second NAND gate, the input end of the second inverter and the grid electrode of the first NMOS tube;
the output end of the second inverter is connected with the mirror current module;
the output end of the third inverter is connected with the other input end of the second NAND gate;
the output end of the second NAND gate is connected with the fourth inverter;
and the output end of the fourth inverter is connected with the grid electrode of the second NMOS tube.
6. The circuit of claim 2, wherein the comparison voltage circuit comprises: a plurality of series resistors;
one end of a first resistor in the plurality of series resistors is connected with the output end of the charge pump, the other end of the first resistor is connected with the comparison voltage connecting end of the voltage comparator and one end of a second resistor, and the other end of the second resistor is connected with one end of any resistor except the first resistor and the second resistor in the plurality of series resistors.
7. The circuit of claim 5, wherein the first NMOS transistor is turned on when the operation enable signal, the buck enable signal, and the discharge enable signal are high;
and when the working enabling signal and the voltage reduction enabling signal are at high level and the discharge enabling signal is at low level, the first NMOS tube and the second NMOS tube are simultaneously conducted.
8. The circuit of claim 4, wherein the first discharge current is less than the second discharge current.
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| CN201811519988.7A CN111312313B (en) | 2018-12-12 | 2018-12-12 | Circuit for quickly switching voltage of charge pump |
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| CN112600410B (en) * | 2020-12-24 | 2022-01-04 | 芯天下技术股份有限公司 | Discharge circuit of negative voltage charge pump and nonvolatile storage |
| CN113364276B (en) * | 2021-06-28 | 2022-08-12 | 芯天下技术股份有限公司 | Charge pump discharging method, circuit, system, electronic equipment and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1661894A (en) * | 2004-02-27 | 2005-08-31 | 恩益禧电子股份有限公司 | Power supply circuit |
| CN101009464A (en) * | 2006-01-27 | 2007-08-01 | 罗姆股份有限公司 | Charge pump circuit and electric appliance therewith |
| CN101258554A (en) * | 2005-07-12 | 2008-09-03 | 美光科技公司 | Negative voltage discharge scheme to improve snapback in a non-volatile memory |
| CN101286693A (en) * | 2007-04-10 | 2008-10-15 | 立锜科技股份有限公司 | Charge pump regulator and method for generating regulated voltage |
| CN102055320A (en) * | 2011-01-24 | 2011-05-11 | 昆山睿识微电子有限公司 | Charge pump circuit and implementation method thereof |
| CN106100320A (en) * | 2016-06-30 | 2016-11-09 | 唯捷创芯(天津)电子技术股份有限公司 | The charge pump unit of a kind of frequency-adjustable, chip and communication terminal |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004013979A (en) * | 2002-06-05 | 2004-01-15 | Elpida Memory Inc | Semiconductor device |
| JP4657252B2 (en) * | 2007-06-04 | 2011-03-23 | 三洋電機株式会社 | Charge pump circuit and slice level control circuit |
-
2018
- 2018-12-12 CN CN201811519988.7A patent/CN111312313B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1661894A (en) * | 2004-02-27 | 2005-08-31 | 恩益禧电子股份有限公司 | Power supply circuit |
| CN101258554A (en) * | 2005-07-12 | 2008-09-03 | 美光科技公司 | Negative voltage discharge scheme to improve snapback in a non-volatile memory |
| CN101009464A (en) * | 2006-01-27 | 2007-08-01 | 罗姆股份有限公司 | Charge pump circuit and electric appliance therewith |
| CN101286693A (en) * | 2007-04-10 | 2008-10-15 | 立锜科技股份有限公司 | Charge pump regulator and method for generating regulated voltage |
| CN102055320A (en) * | 2011-01-24 | 2011-05-11 | 昆山睿识微电子有限公司 | Charge pump circuit and implementation method thereof |
| CN106100320A (en) * | 2016-06-30 | 2016-11-09 | 唯捷创芯(天津)电子技术股份有限公司 | The charge pump unit of a kind of frequency-adjustable, chip and communication terminal |
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Patentee after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. Patentee before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. |