JP2000262044A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can reduce pulsation of the voltage of load capacity in a charge retention period and loss of the current by a voltage detection circuit. SOLUTION: This device is provided with a switch control circuit 22 which controls, in the period of retention of charge of a load capacity 16 where the specified voltage is detected by a voltage detection circuit, switches 7, 9, and 11-15 to add the voltages of power supplies 6 to it by a prescribed number of stages to bring it into a prescribed voltage or over, and to supply the charge charged in the capacity 8 of the charge circuit of a minimum prescribed number of stages to the load capacity 16, thus lightening the pulsation of the voltage of the load capacity 16 in the period of charge retention of the load capacity 16, and also lightening the loss of the current by the leakage via the potential dividing resistors 23 and 24 of the voltage detection circuit 21 too.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a booster circuit for boosting a load capacity.

[0002]

2. Description of the Related Art FIG. 12 is a circuit diagram showing a conventional semiconductor integrated circuit device having a booster circuit.
Is a charging circuit composed of four stages, and 5 is a booster circuit. In the charging circuits 1 to 4, 6 is a power supply, 7 is a switch constituted by an FET or the like, 8 is a capacitance such as a gate capacitance and a well capacitance of a transistor, 9 is a switch constituted by an FET or the like, and 10 is a ground. . Here, the switch 7 is connected to the anode of the capacitor 8, and the switch 9 is connected to the cathode of the capacitor 8. In the booster circuit 5, 6 is a power supply, 11 is a switch for connecting the power supply 6 and the charging circuit 1 in series, 12 to 14 are switches for connecting the charging circuits 1 to 4 in series, and 15 is the last stage. A switch 10 for connecting the charging circuit 4 and the load capacitance 16 in series is a ground. Here, the load capacity 16 is
It is equivalent to the gate capacitance and well capacitance of transistors such as word lines of flash memory,
The capacity is larger than the capacity 8.

Next, the operation will be described. When it is desired to write and erase the flash memory using a word line of the flash memory or the like, the word line must be set to a predetermined voltage. However, since the word line has a load capacitance 16 such as a transistor gate capacitance and a well capacitance, the voltage of the load capacitance 16 must be boosted to a predetermined voltage by the booster circuit 5 shown in FIG. FIG. 13 is a circuit diagram showing a state of charge of a conventional semiconductor integrated circuit device equipped with a booster circuit during a boosting period. As shown in FIG. 13, switches 7 and 9 are turned on and switches 11 to 15 are turned off. The capacity 8 of the charging circuits 1 to 4 is charged. Here, assuming that the voltage of the power supply 6 is VDD, a voltage of VDD is applied to each capacitor 8, and a charge corresponding to the voltage of VDD is stored in each capacitor 8. FIG.
FIG. 1 is a circuit diagram showing a discharge state during a boosting period of a semiconductor integrated circuit device having a conventional booster circuit. As shown in FIG. 2, switches 7 and 9 are turned off and switches 11 to 15 are turned on. The charge stored in the capacitors 8 of the charging circuits 1 to 4 is discharged, and the voltage of the load capacitors 16 is boosted. here,
Assuming that the voltage of the power supply 6 is VDD, the voltage output from the charging circuit 4 is increased to 5VDD, and the load capacitance 16 has 5V.
Charge is supplied at the voltage of DD.

[0004] Since the load capacity 16 is large,
Since the voltage does not reach the predetermined voltage in one charge supply of the booster circuit 5, the charge and discharge of the booster circuit 5 are repeated a plurality of times to boost the voltage of the load capacitance 16 until the voltage of the load capacitor 16 becomes the predetermined voltage. However, the electric charge supplied to the load capacitance 16 is consumed by the use of the word line circuit of the flash memory, and the voltage of the load capacitance 16 falls below a predetermined voltage.
The voltage of D is supplied to the load capacity 16 so that the load capacity 1
The voltage of 6 is set to be equal to or higher than a predetermined voltage. FIG. 5 is a characteristic diagram showing the voltage characteristics of the load capacitance during the boost period and the charge retention period. As shown in the figure, the voltage of the load capacitance 16 gradually increases, and reaches a substantially constant voltage when it reaches a predetermined voltage. Become.

[0005]

The conventional semiconductor integrated circuit device is configured as described above.
There is no technical concept of controlling the number of stages 4 to an arbitrary predetermined number, and the voltage of 5VDD output from the charging circuits 1 to 4 of all stages is always supplied to the load capacitor 16 as the output of the booster circuit 5. In the charge holding period after the voltage of the flash memory reaches the predetermined voltage, a large 5VDD voltage is not supplied despite the small amount of charge that needs to be replenished by using the word line circuit of the flash memory. Not
There is a problem that pulsation (ripple) occurs in the voltage of the load capacitance 16. FIG. 15 is a characteristic diagram showing the voltage characteristics of the conventional load capacitor during the boost period and the charge holding period. As shown in the figure, the voltage of the load capacitor 16 during the charge holding period has a pulsation. Further, since there is no technical concept of controlling the charging circuits 1 to 4 to an arbitrary predetermined number of stages, it is possible to boost the load capacitance 16 to a plurality of predetermined voltages different from each other according to the arbitrary predetermined number of stages of the charging circuits 1 to 4. There were issues such as inability to do so.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a semiconductor integrated circuit device capable of reducing the pulsation of the voltage of the load capacitance during the charge holding period and the current loss due to the voltage detection circuit. The purpose is to obtain.

Another object of the present invention is to provide a semiconductor integrated circuit device capable of boosting a load capacitance to a plurality of predetermined voltages.

Another object of the present invention is to provide a semiconductor integrated circuit device capable of boosting a load capacitance to a predetermined voltage by switching a predetermined number of times regardless of the magnitude of the voltage of a power supply.

[0009]

In a semiconductor integrated circuit device according to the present invention, during a charge holding period of a load capacitor in which a predetermined voltage is detected by a voltage detection circuit, the minimum required for holding a charge of the load capacitor is set. And a switch control circuit for controlling the first and second charging switches and the first and second discharging switches so as to supply the charges charged to the predetermined number of stages of the charging circuits to the load capacitance. Things.

[0010] In the semiconductor integrated circuit device according to the present invention, during the charge holding period of the load capacitance, a predetermined number of charge stages set to the minimum necessary for holding the charge of the load capacitance in synchronization with the pulse generated from the oscillation circuit. A switch control circuit for controlling the first and second charging switches and the first and second discharging switches so as to supply the electric charge charged in the circuit capacitance to the load capacitance.

In the semiconductor integrated circuit device according to the present invention, during the boosting period of the load capacitance, the capacity of the charging circuit of a plurality of types and a predetermined number of stages set in accordance with a predetermined voltage of an arbitrary plurality of values which the load capacitance is desired to boost. The first and second charging switches and the first and second charging switches are configured to discharge the charged electric charges and supply the discharged electric charges to the load capacitance so as to boost the load capacitance to a plurality of predetermined voltages.
And a switch control circuit for controlling the switching of the discharge switch a plurality of times.

In the semiconductor integrated circuit device according to the present invention, during the boosting period of the load capacitance, the charge stored in the capacitance of the charging circuit of a predetermined number of stages set according to the voltage of the power supply is discharged and supplied to the load capacitance. Switch control for increasing the load capacity to a predetermined voltage by switching the first and second charging switches and the first and second discharging switches a predetermined number of times regardless of the magnitude of the voltage of the power supply It has a circuit.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device provided with a booster circuit according to a first embodiment of the present invention.
Is a booster circuit. In the charging circuits 1 to 4, reference numeral 6 denotes a power source, and reference numeral 7 denotes a switch (first
Switch for charging), 8 is the gate capacitance of the transistor,
And a capacitance such as a well capacitance, 9 is a switch (second charge switch) constituted by an FET or the like, and 10 is a ground. Here, the switch 7 is connected to the anode of the capacitor 8.
And a switch 9 is connected to the cathode of the capacitor 8. In the booster circuit 5, reference numeral 6 denotes a power supply, 11 denotes a switch for connecting the power supply 6 and the charging circuit 1 in series, and 12 to
Reference numeral 14 denotes a switch (first discharging switch) for connecting the charging circuits 1 to 4 in series, and 15 denotes a switch (second connection) for connecting the last-stage charging circuit 4 and the load capacitor 16 in series.
10) is a ground. here,
The load capacitance 16 corresponds to the gate capacitance and well capacitance of a transistor such as a word line of a flash memory, and is larger than the capacitance 8.

Reference numeral 21 denotes a voltage detection circuit for detecting the voltage of the load capacitance 16.
3 and 24 are voltage dividing resistors, 25 is those voltage dividing resistors 23 and 24
And the reference voltage Vr.
ef is a comparison circuit. Reference numeral 22 denotes a switch control circuit, which discharges the electric charges charged in each of the charging circuits 1 to 4 during the step-up period of the load capacitance 16 to reduce the load capacitance 1
During the charge holding period of the load capacitance 16 in which the predetermined voltage is detected by the voltage detection circuit 21, the charge charged in the capacitance 8 of the charge circuit of the predetermined number of stages set arbitrarily is stored in the load capacitance 16. Switches 7, 9, 11 to 1 to supply
5 is controlled.

Next, the operation will be described. When it is desired to write and erase the flash memory using a word line of the flash memory or the like, the word line must be set to a predetermined voltage. However, the word line has a load capacitance 16 such as a transistor gate capacitance and a well capacitance, and the voltage of the load capacitance 16 is boosted to a predetermined voltage by the booster circuit 5 shown in FIG. FIG.
FIG. 3 is a circuit diagram showing a charge state of the semiconductor integrated circuit device including the booster circuit according to the first embodiment of the present invention during the boosting period. As shown in FIG. ON, switches 11 to
15 is turned off, and the capacity 8 of each of the charging circuits 1 to 4 is charged. Here, assuming that the voltage of the power supply 6 is VDD, each capacitor 8
Is applied with a voltage of VDD, and each capacitor 8 has its VDD
The electric charge corresponding to the voltage of is stored. FIG. 3 is a circuit diagram showing a discharge state during a boosting period of the semiconductor integrated circuit device provided with the booster circuit according to the first embodiment of the present invention. As shown in FIG. The switches 7 and 9 are turned off and the switches 11 to 15 are turned on to discharge the electric charges charged in the capacitors 8 of the charging circuits 1 to 4 and to boost the voltage of the load capacitors 16. Here, assuming that the voltage of the power supply 6 is VDD, the voltage output from the charging circuit 4 is increased to 5VDD, and the load capacitance 16 has 5VDD.
The electric charge is supplied at the voltage of.

Since the load capacity 16 is large,
Since the voltage does not reach the predetermined voltage in one supply of the charge of the booster circuit 5, the voltage of the load capacitor 16 is controlled by the switch control circuit 22 by repeating the charging and discharging of the booster circuit 5 a plurality of times. Boost until voltage. In the voltage detection circuit 21, the voltage of the load capacitance 16 is divided by the voltage dividing resistors 23 and 24, and the divided voltage is compared with the reference voltage Vref by the comparison circuit 25.
The divided voltage is applied to the reference voltage Vre by the comparing circuit 25.
When the voltage reaches f, that is, when the voltage of the load capacitance 16 reaches a predetermined voltage, the boosting of the load capacitance 16 by the booster circuit 5 is stopped. However, the electric charge supplied to the load capacitor 16 consumes current due to the use of the word line circuit of the flash memory, and leaks to the ground 10 via the voltage dividing resistors 23 and 24 of the voltage detecting circuit 21. Since the voltage of the load capacitance 16 falls below the predetermined voltage, a charge is supplied from the booster circuit 5 so that the voltage of the load capacitance 16 always becomes higher than the predetermined voltage.

In the prior art, there is no technical concept of controlling the charging circuits 1 to 4 to a predetermined number of stages.
The voltage of 5VDD output from 4 is supplied to the load capacitor 16 as the output of the booster circuit 5. For example, when it is desired to write and erase data in a flash memory using a word line or the like, the voltage of the load capacitor 16 is set to 10 V
However, if the voltage of the power supply 6 is VDD = 2.
In the case of 5V, even in the charge holding period after the voltage of the load capacitor 16 reaches 10V, a large 5VDD = despite the small amount of charge that needs to be replenished by using the word line circuit of the flash memory. A voltage of 12.5 V must be supplied, and pulsation occurs in the voltage of the load capacitance 16.

FIG. 4 is a circuit diagram showing a discharge state during a charge holding period of the semiconductor integrated circuit device provided with the booster circuit according to the first embodiment of the present invention. During the charge holding period after the voltage reaches 10 V, the switch 7, the switches 9 of the charging circuits 2 to 4, the switch 11 are turned off, the switch 9 of the charging circuit 1, and the switches 12 to 15 are controlled by the switch control circuit 22. Is turned on to supply a voltage of 4VDD = 10 V to the load capacitance 16. Therefore, the pulsation of the voltage of the load capacitance 16 can be reduced. Also, 4VDD =
Since the voltage of 10 V is supplied, the voltage during the charge holding period does not become unnecessarily high, the amount of charge due to leakage through the voltage dividing resistors 23 and 24 of the voltage detection circuit 21 does not increase, and the current loss is reduced. can do. FIG. 5 is a characteristic diagram showing the voltage characteristics of the load capacitance during the boost period and the charge retention period. As shown in the figure, the voltage of the load capacitance 16 gradually increases, and reaches a substantially constant voltage when it reaches a predetermined voltage. Become.

In the first embodiment, the load capacity 16
Is 10 V, the voltage of the power supply 6 is 2.5 V, the number of stages of the charging circuits 1 to 4 in the charge holding period is four, and a voltage of 4 VDD = 10 V is supplied in the charge holding period. And the voltage of the power supply 6 may be any voltage, and the predetermined number of stages of the charging circuits 1 to 4 during the charge holding period is equal to or higher than the predetermined voltage by adding the voltage of the power supply 6 to the predetermined number of stages, and Any condition that satisfies the condition of the minimum predetermined number of stages may be used.

As described above, according to the first embodiment, during the boosting period of the load capacitance 16, the electric charges charged in the charging circuits 1 to 4 are discharged and supplied to the load capacitance 16, and the voltage detection is performed. In the charge holding period of the load capacitor 16 in which the predetermined voltage is detected by the circuit 21, the voltage of the power supply 6 is added to the predetermined number of stages, the voltage becomes equal to or higher than the predetermined voltage, and the capacitor 8 of the minimum predetermined number of stages is charged. The switch control circuit 22 for controlling the switches 7, 9, 11 to 15 so as to supply the charged electric charge to the load capacitance 16 is provided.
6, the pulsation of the voltage of the load capacitor 16 during the charge retention period can be reduced, and the current loss due to leakage through the voltage dividing resistors 23 and 24 of the voltage detection circuit 21 can be reduced.

Embodiment 2 FIG. FIG. 6 is a circuit diagram showing a semiconductor integrated circuit device provided with a booster circuit according to a second embodiment of the present invention. In the figure, reference numeral 31 denotes an oscillation circuit that generates a pulse having a constant period, 32 denotes a switch control circuit, During the step-up period of the load capacitance 16, the switches 7, 9, 11 to 15 are controlled in synchronization with the pulse generated from the oscillation circuit 31 to discharge the charges charged in the charging circuits 1 to 4 so that the load is discharged. The switches 7, 9, 1 are supplied to the capacitor 16 for a predetermined number of times when it is expected that the voltage of the load capacitor 16 has reached the predetermined voltage.
After the switching of 1 to 15, the self-determination of the charge holding period of the load capacitor 16 is made, and the capacity 8 of the charging circuit of a predetermined number of stages arbitrarily set according to the expected voltage drop of the load capacitor 16 is determined. The switches 7, 9, 11 to 15 are controlled so that the charged electric charge is supplied to the load capacitance 16. The other configuration is the same as that of the first embodiment, and the description thereof will not be repeated.

Next, the operation will be described. Embodiment 1
Then, the voltage of the load capacitance 16 is detected by the voltage detection circuit 21, and the switch control circuit 22 causes the switches 7, 9, and 9 of the load capacitance 16 to perform the boosting period and the charge holding period in accordance with the detected voltage. In the second embodiment, an oscillation circuit 31 is provided instead of the voltage detection circuit 21, and the switch control circuit 32 controls the switch 7 in synchronization with the pulse generated from the oscillation circuit 31. , 9, 11 to 15 are controlled. During the step-up period of the load capacitance 16, based on the voltage of the power supply 6, the capacitance 8, and the load capacitance 16, how many times the electric charges charged in the charging circuits 1 to 4 are supplied to the load capacitance 16, It is possible to predict whether the voltage of 16 becomes a predetermined voltage by calculation, test, or the like. The switch control circuit 32
Controls the switches 7, 9, 11 to 15 in synchronization with the pulse generated from the oscillation circuit 31 to supply the charges charged in the charging circuits 1 to 4 to the load capacitance 16, and
6 is boosted to a predetermined voltage.

During the charge holding period of the load capacitance 16, the voltage detection circuit 21 is not provided since the voltage detection circuit 21 is not provided.
Although current leakage does not occur, current is consumed by the use of the word line circuit of the flash memory, and the voltage of the load capacitance 16 decreases. Therefore, even during the charge holding period of the load capacitance 16, the number of stages of the charging circuits 1 to 4 satisfying the condition that the voltage of the power supply 6 is added to the predetermined number of stages and becomes equal to or higher than the predetermined voltage of the load capacitance 16 and the minimum predetermined number of stages is satisfied. Then, it is predicted by calculation or a test how long the charge should be supplied to the load capacitor 16 so that the voltage of the load capacitor 16 can be maintained at a predetermined voltage or more. Is switched in synchronization with the pulse generated from the oscillation circuit 31 to supply the charge charged in the capacitance 8 of the predetermined number of charging circuits to the load capacitance 16 in accordance with the cycle corresponding to the expected period. 7, 9, 11 to 15 are controlled.

As described above, according to the second embodiment, during the step-up period of the load capacitance 16, the switches 7, 9, 11 are expected to be synchronized in number with the pulse generated from the oscillation circuit 31. To charge the charging circuits 1 to 4 to discharge the charges and supply the charges to the load capacitors 16. During the charge holding period of the load capacitors 16, the voltage of the power supply 6 is added to the load capacitors 16 by a predetermined number of stages to load the load capacitors 16. The number of stages of the charging circuits 1 to 4 which is equal to or higher than the predetermined voltage of 16 and which satisfies the condition of the minimum predetermined number of stages, in synchronization with the pulse generated from the oscillation circuit 31, the period corresponding to the expected period Accordingly, a switch control circuit 32 for controlling the switches 7, 9, 11 to 15 so as to supply the charges charged in the capacitors 8 of the predetermined number of charge circuits to the load capacitors 16 is provided. 16 charge retention periods It is possible to relieve the pulsation of the voltage of the definitive load capacitance 16, since the voltage detecting circuit 21 is not provided, the effect which can prevent the loss of current due to the leakage of the voltage detection circuit 21 is obtained.

Embodiment 3 FIG. 7 is a circuit diagram showing a semiconductor integrated circuit device provided with a booster circuit according to a third embodiment of the present invention. In the figure, reference numeral 41 denotes a pulse generated from the oscillation circuit 31 during the boost period of the load capacitance 16. In synchronization with this, the charge stored in the capacitors 8 of the charging circuits 1 to 4 of a predetermined number of stages set according to an arbitrary predetermined voltage to be boosted of the load capacitance 16 is discharged and supplied to the load capacitance 16 to load the load capacitance 16 16 so that switch 16 is boosted to the predetermined voltage.
This is a switch control circuit that controls switching of 9, 11, 15, and 15 a plurality of times. The other configuration is the same as that of the second embodiment, and the description thereof will not be repeated.

Next, the operation will be described. When writing and erasing in the flash memory by using a word line of the flash memory or the like, the word line is set to 10 V
If you want to read from that memory,
The word line may be set to a voltage of 5V. FIG. 8 is a circuit diagram showing a discharge state (4VDD) in a boosting period of a semiconductor integrated circuit device provided with a boosting circuit according to a third embodiment of the present invention.
When the word line is to be set to a voltage of 10 V, that is, when the load capacitance 16 is to be set to a voltage of 10 V, the switch 7 and the charging circuit 2 are controlled by the switch control circuit 41.
Switch 9 and switch 11 are turned off, charging circuit 1
Switch 9 and switches 12 to 15 are turned on,
If DD = 2.5V, a voltage of 4VDD = 10V is supplied to the load capacitance 16. FIG. 9 is a circuit diagram showing a discharge state (2VDD) during a boost period of a semiconductor integrated circuit device provided with a booster circuit according to a third embodiment of the present invention. 1
6 is set to 5V, the switch control circuit 41
Control, the switch 7 and the charging circuits 1, 2, 4
Switch 9 and switches 11 to 13 are turned off, switch 9 of the charging circuit 3 and switches 14 and 15 are turned on,
If VDD = 2.5V, a voltage of 2VDD = 5V is supplied to the load capacitance 16. In any case, if the switch control circuit 41 controls the switching of the switches 7, 9, 11 to 15 a plurality of times in synchronism with the pulse generated from the oscillation circuit 31, the load capacitance 16 becomes a predetermined voltage of 10V or 5V. become. FIG. 10 is a characteristic diagram showing the voltage characteristics of the load capacitance during the boosting period according to the third embodiment of the present invention. As shown in the figure, in the configuration of the third embodiment, the number of stages of charging circuits 1 to 4 varies depending on the number of stages. A predetermined voltage of the load capacitance 16 can be set.

In FIG. 9, the switch control circuit 41
It is needless to say that the switches 7 and 9 of the charging circuits 1 and 2 are controlled so that the capacitors 8 of the charging circuits 1 and 2 that are not discharged are not charged in a charged state in order to prevent unnecessary loss of electric charge. Although the third embodiment has been described only during the step-up period of the load capacitance 16, the charge holding period of the load capacitance 16 may be combined with any of the other embodiments. That is, as described in the first embodiment, when the voltage detection circuit 21 detects that the voltage of the load capacitance 16 is equal to or lower than the predetermined voltage, the capacitance 8 of the charging circuit of the minimum necessary number of stages is charged. The switches 7, 9, 11 to 15 are controlled so as to supply the charged electric charges to the load capacitance 16, and the minimum necessary according to the expected period of the load capacitance 16 as described in the second embodiment. The switches 7, 9, 11-1 are connected so that the electric charge charged in the capacitance 8 of the charging circuit of the number of stages is supplied to the load capacitance 16.
5 may be controlled. In the third embodiment, the voltage of the load capacitance 16 is set to 5 V and 10 V by the configuration of the oscillation circuit 31 and the switch control circuit 41. However, as described in the first embodiment, the voltage detection circuit 21 And the switch control circuit 41, the voltage detection circuit 21 detects 5V and 10V of the voltage of the load capacitance 16, and the switch control circuit 41
, The voltage of the load capacitor 16 may be held at 5V and 10V by shifting from the boosting period to the charge holding period.

As described above, according to the third embodiment, during the boosting period of load capacitance 16, charging circuits 1-4 of a predetermined number of stages set according to an arbitrary predetermined voltage of load capacitance 16 to be boosted. A switch control circuit for controlling the switches 7, 9, 11 to 15 to switch a plurality of times so as to discharge the electric charge charged in the capacitor 8 and supply it to the load capacitor 16 to boost the load capacitor 16 to the predetermined voltage. Since the charging circuit 41 is provided, an arbitrary predetermined voltage can be supplied to the load capacitor 16 by setting the number of predetermined stages of the charging circuits 1 to 4 arbitrarily, and the load capacitor 16 is boosted to an arbitrary voltage. The effect that can be obtained is obtained.

Embodiment 4 The fourth embodiment will be described with reference to FIGS. 7 to 9 showing the third embodiment. In FIG. 7, the switch control circuit 41 according to the fourth embodiment controls the power supply 6 during the boost period of the load capacitance 16.
The charge stored in the capacitors 8 of the charging circuits 1-4 of a predetermined number of stages set according to the voltage of
, So that the load capacity 16 is boosted to a predetermined voltage by switching the switches 7, 9, 11 to 15 a predetermined number of times regardless of the magnitude of the voltage of the power supply 6. The other configuration is the same as that of the third embodiment, and the description thereof will not be repeated.

Next, the operation will be described. The voltage of the power supply 6 may be different depending on the device on which the semiconductor integrated circuit device is mounted. For example, depending on the device, 1.8V-
The voltage of the power supply 6 differs between 5.8V. Therefore, for example, when the voltage of the power supply 6 is 2.5 V, as shown in FIG.
If it is desired to set the voltage at 0 V, that is,
When a voltage of 0 V is desired, the switch 7, the switches 9 of the charging circuits 2 to 4, and the switch 11 are turned off by the control of the switch control circuit 41, and the switch 9 of the charging circuit 1 is turned off.
And switches 12 to 15 are turned on, and VDD = 2.5
If it is V, a voltage of 4 VDD = 10 V is supplied to the load capacitance 16. For example, when the voltage of the power supply 6 is 5 V,
As shown in FIG. 9, when it is desired to set the word line to a voltage of 10 V, that is, to set the load capacitance 16 to a voltage of 10 V, the switch 7 and the charging circuits 1, 2,. 4 and the switches 11 to 13 are turned off, the switch 9 of the charging circuit 3 and the switches 14 and 15 are turned on. If VDD = 5V, 2
A voltage of VDD = 10 V is supplied to the load capacitance 16. In any case, the switch control circuit 41 switches the switches 7, 9, 11 to 1 in synchronization with the pulse generated from the oscillation circuit 31.
5 is controlled a plurality of times by the same method, the load capacity 16
Becomes a predetermined voltage of 10V. FIG. 11 is a characteristic diagram showing a voltage characteristic of the load capacitance during the boosting period according to the fourth embodiment of the present invention. As shown in FIG. If the number of stages is set to 4, the load capacitance 16 can be set to a predetermined voltage with the same number of switchings regardless of the voltage of the power supply 6. still,
Five stages of 2V5 stages in FIG. 11 are when switches 11 to 15 are turned on.

In the fourth embodiment, the load capacity 16
Although only the step-up period is shown, the charge holding period of the load capacitor 16 can be combined with other embodiments as described in the third embodiment.

As described above, according to the fourth embodiment, during the boosting period of the load capacitance 16, the capacitances 8 of the charging circuits 1-4 of a predetermined number of stages set according to the voltage of the power supply 6 are charged. The charge is discharged and supplied to the load capacitor 16, and the switch 7, 9, 11 to 15 are switched a plurality of times with the same number of switchings regardless of the magnitude of the voltage of the power supply 6 by the load capacitor 16. Is configured to include the switch control circuit 41 that boosts the voltage of the charging circuit 1 to 4 in accordance with the voltage of the power supply 6.
Load capacity 16
Can be set to a predetermined voltage. Therefore, in the configuration in which the voltage detection circuit 21 is not provided and the load capacitance 16 is set to the predetermined voltage in accordance with the predetermined number of switchings expected by the pulse generated by the oscillation circuit 31, the voltage of the power supply 6 is different. Even when this semiconductor integrated circuit device is applied to a simple device, the load capacitance 16 can be set to a predetermined voltage by a fixed number of switchings regardless of the magnitude of the voltage of the power supply 6. As long as the number of stages of the charging circuits 1 to 4 is set in accordance with the size of, the effect that can be easily applied is obtained.

[0033]

As described above, according to the present invention, during the charge holding period of the load capacitor in which the predetermined voltage is detected by the voltage detection circuit, the predetermined value set to the minimum necessary for holding the charge of the load capacitor is provided. A switch control circuit for controlling the first and second charging switches and the first and second discharging switches so as to supply the charges charged in the capacitances of the number of stages of charging circuits to the load capacitance is provided. Therefore, the pulsation of the voltage of the load capacitor during the charge holding period of the load capacitor can be reduced, and the current loss due to leakage through the voltage detection circuit can be reduced.

According to the present invention, during the charge holding period of the load capacitance, the capacity of the predetermined number of charging circuits set to the minimum necessary for holding the charge of the load capacitance is synchronized with the pulse generated from the oscillation circuit. First and second charging switches and first and second charging switches for supplying the charged electric charge to the load capacitance.
Is configured to include a switch control circuit for controlling the discharge switch of the above, so that the pulsation of the voltage of the load capacitance during the charge holding period of the load capacitance can be reduced,
Since the voltage detection circuit is not provided, an effect of preventing a current loss due to leakage of the voltage detection circuit can be obtained.

According to the present invention, during the boosting period of the load capacitance, the electric charges charged to the capacitances of a plurality of types of predetermined number of stages of charging circuits set in accordance with a predetermined plurality of arbitrary values of the load capacitance to be boosted. And supply the load capacitance to the load capacitance to increase the load capacitance to a plurality of predetermined voltages.
And a switch control circuit for controlling the switching of the first and second discharging switches a plurality of times. By setting a predetermined number of stages of the charging circuit, an arbitrary predetermined voltage can be obtained. The voltage can be supplied to the load capacitance, and the load capacitance can be boosted to an arbitrary voltage.

According to the present invention, during the boosting period of the load capacity, the charge stored in the capacity of the charging circuit of the predetermined number of stages set according to the voltage of the power supply is discharged and supplied to the load capacity to supply the load capacity. A switch control circuit for controlling the voltage of the power supply to increase the voltage to a predetermined voltage by switching the first and second charging switches and the first and second discharging switches a predetermined number of times regardless of the magnitude of the voltage. Therefore, there is no voltage detection circuit, and in the configuration in which the load capacitance is set to the predetermined voltage in accordance with the predetermined number of switching expected by the pulse generated by the oscillation circuit, the magnitude of the voltage of the power supply varies. Even when this semiconductor integrated circuit device is applied to the device, the load capacitance can be set to a predetermined voltage by a fixed number of switching times regardless of the magnitude of the voltage of the power supply. By setting even number of stages of the charge circuit in response to the magnitude of the voltage source, the effect can be readily applied to obtain.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device including a booster circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a charge state during a boosting period of the semiconductor integrated circuit device including the booster circuit according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram showing a discharge state during a boosting period of the semiconductor integrated circuit device including the boosting circuit according to the first embodiment of the present invention;

FIG. 4 is a circuit diagram showing a discharge state in a charge holding period of the semiconductor integrated circuit device including the booster circuit according to the first embodiment of the present invention;

FIG. 5 is a characteristic diagram illustrating voltage characteristics during a load capacitance boosting period and a charge holding period.

FIG. 6 is a circuit diagram showing a semiconductor integrated circuit device including a booster circuit according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a semiconductor integrated circuit device including a booster circuit according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a discharge state (4VDD) in a boosting period of a semiconductor integrated circuit device provided with a boosting circuit according to a third embodiment of the present invention.

FIG. 9 is a circuit diagram showing a discharge state (2VDD) in a boosting period of a semiconductor integrated circuit device provided with a boosting circuit according to a third embodiment of the present invention.

FIG. 10 is a characteristic diagram showing a voltage characteristic during a boost period of a load capacitance according to a third embodiment of the present invention;

FIG. 11 is a characteristic diagram showing a voltage characteristic during a boost period of a load capacitance according to a fourth embodiment of the present invention;

FIG. 12 is a circuit diagram showing a semiconductor integrated circuit device provided with a conventional booster circuit.

FIG. 13 is a circuit diagram showing a state of charge in a boosting period of a semiconductor integrated circuit device including a conventional booster circuit.

FIG. 14 is a circuit diagram showing a discharge state during a boosting period of a semiconductor integrated circuit device including a conventional boosting circuit.

FIG. 15 is a characteristic diagram showing voltage characteristics of a conventional load capacitance during a boost period and a charge holding period.

[Explanation of symbols]

1-4 charging circuit, 5 booster circuit, 6 power supply, 7 switch (first charging switch), 8 capacity, 9 switch (second charging switch), 10 ground, 12-
14 switches (first discharging switch), 15 switches (second discharging switch), 16 load capacity, 21
Voltage detection circuit, 22, 32, 41 switch control circuit, 31 oscillation circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Motoharu Ishii 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation (72) Inventor Yukio Nakamoto 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsui Electric Co., Ltd. (72) Kunio Tani 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Tomohisa Iba 2-5-2, Otemachi, Chiyoda-ku, Tokyo 3 Within Ryo Denki Engineering Co., Ltd. (72) Inventor Yutaka Wakuchichi 3-1-1-17 Chuo, Itami-shi, Hyogo Mitsubishi Electric Machinery System LSI Design Inc. (72) Inventor Tetsuya Sakaba Itami-shi, Hyogo Chuo 3-1-1-17 Mitsubishi Electric System LSI Design Co., Ltd. F-term (reference) 5B025 AD10 AE06 5F03 8 BG02 BG03 BG05 BG08 EZ20 5H730 AA00 BB02 BB57 FD01

Claims (4)

[Claims] 1. A plurality of charging circuits each having an anode of a capacitor connected to a first charging switch connected to a power supply and a cathode of the capacitor connected to a second charging switch connected to ground. And the plurality of charging circuits are respectively the first
A plurality of stages are connected in series via a discharging switch, and a charging circuit at the final stage detects a booster circuit connected to a load capacitor via a second discharging switch, and detects the voltage of the load capacitor. A voltage detection circuit, and, during the step of boosting the load capacitance, the plurality of charging circuits being switched in accordance with a plurality of switching operations of the first and second charging switches and the first and second discharging switches. The charge stored in each capacitor is discharged and supplied to the load capacitor to increase the load capacitance. During the charge holding period of the load capacitor in which a predetermined voltage is detected by the voltage detection circuit, the load capacitor is charged. The first and second charging switches and the first and second charging switches so as to supply the charge charged to the capacitance of the charging circuit of a predetermined number of stages set to the minimum necessary for holding the charge to the load capacitance. Discharge switch The semiconductor integrated circuit device and a switch control circuit for controlling the pitch. 2. A plurality of charging circuits each having an anode of a capacitor connected to a first charging switch connected to a power supply and a cathode of the capacitor connected to a second charging switch connected to the ground. And the plurality of charging circuits are respectively the first
And a booster circuit in which a final stage charging circuit is connected to a load capacitor via a second discharging switch, and an oscillation circuit for generating a pulse having a constant cycle. Circuit, and during the boosting period of the load capacitance, the first and second charging switches and the first and second charging switches are synchronized with a pulse generated from the oscillation circuit.
Discharging the electric charges charged in the respective capacitances of the plurality of charging circuits in accordance with the expected predetermined number of switching operations of the discharging switch, supplying the electric charges to the load capacitance, and boosting the load capacitance to a predetermined voltage. During the charge holding period of the load capacitance after being boosted to the predetermined voltage, a predetermined number of stages set to the minimum necessary for holding the charge of the load capacitance in synchronization with the pulse generated from the oscillation circuit. The first charge is supplied to the charge capacity of the charging circuit so as to supply the charge to the load capacity.
And a second charge switch and a switch control circuit for controlling the first and second discharge switches. 3. A plurality of charging circuits each having an anode of a capacitor connected to a first charging switch connected to a power supply and a cathode of the capacitor connected to a second charging switch connected to the ground. And the plurality of charging circuits are respectively the first
And a booster circuit in which a final stage charging circuit is connected to a load capacitor via a second discharge switch, and a booster circuit connected to the load capacitor via a second discharge switch. Discharging the electric charges charged in the above-mentioned capacitances of a plurality of types of the above-mentioned charging circuits set in accordance with a plurality of arbitrary predetermined values of the load capacitances to be boosted and supplying the charges to the load capacitances, A semiconductor integrated circuit comprising: a first and a second charging switch; and a switch control circuit for controlling the first and second discharging switches a plurality of times so as to boost the capacitance to the plurality of predetermined voltages. Circuit device. 4. During the boost period of the load capacity, the charge stored in the capacity of the charging circuit of a predetermined number of stages set according to the voltage of the power supply is discharged and supplied to the load capacity, and the load capacity is stored in the load circuit. No. 1 of the predetermined times regardless of the magnitude of the voltage of the power supply
3. The semiconductor integrated circuit device according to claim 2, further comprising a switch control circuit for controlling the voltage to be raised to a predetermined voltage by switching between the second charging switch and the first and second discharging switches.