JP3578248B2 - Semiconductor booster circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a booster circuit in a semiconductor device.
[0002]
[Prior art]
In recent semiconductor integrated circuits, for example, flash EEPROMs, power supplies of various voltages such as a positive high voltage and a negative high voltage are required for writing, erasing, and reading.
[0003]
However, on the other hand, low power consumption and a single power supply have been promoted. Under such circumstances, for example, in order to achieve a single power supply, an external power supply voltage is boosted by a circuit provided internally. Is provided.
[0004]
As a semiconductor booster circuit for internally boosting such an external power supply voltage, for example, a charge pump type booster circuit as shown in FIG. 4 is known. Note that the charge pump type booster circuit of FIG. 4 is a positive booster circuit.
[0005]
The charge pump type booster circuit shown in FIG. 4 basically receives the boosting clocks CLK ₁ and CLK ₂ and receives the boosting clocks CLK ₁ and CLK ₂ to form the power supply voltage Vdd according to the number of stages of the respective pump blocks 11 to ₁ n constituting the charge pump means. It is one to obtain a predetermined voltage Vpp boosted from the output terminal 6 from the diode D ₁ -Dn are connected in series, with respect to the cathode of each of diodes D ₁ -Dn, capacitive element C for boosting The two boosting clocks CLK ₁ and CLK ₂ generated from the clock generating means 1 are supplied via _{1 to} Cn.
[0006]
Clock _CLK 1, CLK ₂ for boosting in this case, of the capacitive element _C 1 to Cn, the capacitive element _C 1, _{C 3} corresponding to the odd-numbered in the figure, one for ... clock CLK ₁ In addition, the other CLK ₂ is supplied to the capacitive elements C ₂ , C ₄ ,. The two clocks CLK ₁ and CLK ₂ have the same frequency and opposite phases. When both the clocks CLK ₁ and CLK ₂ are at the L level, they are at the GND level, and when they are at the H level, they are at the Vdd level of the power supply voltage. It is set to be. The last-stage diode Do and capacitive element Co are rectifying elements, and constitute an output rectifying means 4 for rectifying the output voltage Vpp.
[0007]
Hereinafter, the operation of the charge pump circuit shown in FIG. 4 will be described in detail.
[0008]
First, one of the clock CLK ₁ is when L level, the other clock CLK ₂ of H-level, the diode _{D 1} since the capacitive element _{C 1} subjected to any forward bias is charged, the first stage of the pump block _{1 1} node _{N 1} becomes the potential (= Vdd-Vd) obtained by subtracting the voltage drop of the diode _{D 1} a (= Vd) from Vdd.
[0009]
Next, the CLK ₁ is H level, the CLK ₂ becomes L level, the potential of the node _{N 1} becomes the potential of (Vdd-Vd) from being boosted by Vdd min (2Vdd-Vd). At this time, since the capacitive element C ₂ subjected to any forward bias to the diode D ₂ of the next stage of the pump block 1 ₂ is charged, the potential of the node N ₂ is the front of the pump block 1 ₁ node N a value of the voltage drop due to the diode _{D 2} from the _first potential (= Vd) minus (2Vdd-Vd) -Vd = 2 (Vdd-Vd).
[0010]
Subsequently, CLK ₁ is L level, the CLK ₂ becomes H level, the potential of the node _{N 2} becomes boosted by Vdd min from 2 (Vdd-Vd) (3Vdd -2Vd). At this time, since the diodes D ₃ of the next stage of the pump block 1 ₃ capacitive element C ₃ participating forward bias is charged, the potential of the node N ₃ is the node N ₂ of the preceding stage potential a value of minus voltage drop due to the diode _{D 3} a (= Vd) (3Vdd-2Vd ) -Vd = 3 (Vdd-Vd) from.
[0011]
Hereinafter, by repeating the same operation, are boosted by number of stages of each pump block ₁ 1 1n, the potential of the node Nn of pump block 1n of the n-th stage becomes n · (Vdd-Vd). The final output voltage Vpp obtained at the output terminal 6 peak-holds the potential of the node Nn by the output rectifier 4, so that Vpp = (n + 1). (Vdd-Vd).
[0012]
[Problems to be solved by the invention]
By the way, in the charge pump type booster circuit shown in FIG. 4, when the external power supply voltage Vdd fluctuates due to noise or the like and its value Vdd decreases, the output voltage Vpp also decreases accordingly and cannot output a desired voltage. There is a problem.
[0013]
Conversely, when the external power supply voltage Vdd increases, the output voltage Vpp also increases more than necessary, which is disadvantageous in terms of power consumption.
[0014]
Further, when the output voltage Vpp is too high, there is a problem that the breakdown voltage exceeds the breakdown voltage of the PN junction diode and the characteristics are deteriorated.
[0015]
In addition, a semiconductor device may require a large number of boosted voltages. At that time, however, a charge pump type booster circuit is required for each boosted voltage, which is disadvantageous in terms of mounting area and cost. There's a problem.
[0016]
An object of the present invention is to solve such a problem and to provide a low-power-consumption, low-cost semiconductor booster circuit.
[0017]
[Means for Solving the Problems]
The present invention takes the following measures in order to solve the above problems.
[0018]
Charge pump means for generating a boosted voltage by connecting a plurality of pump blocks performing a boosting operation by charging / discharging a capacitive element by a boosting clock and connecting the pump blocks in series; a clock generating means capable of controlling the supply of said charge pump means and the step-up clock for each of the pump block constituting the, of the output of the pump block in the charge pump means, rectifying one output even without least Output rectification means connected to a capacitive element via a diode for output, and in order to obtain a desired boosted voltage from the output rectification means, the clock generation means transmits the boosted clock to the charge pump. the supply from the subsequent stage of the pump block constituting stops, and wherein adjusting the number of stages of the pump block operating To have.
[0019]
According to a second aspect of the present invention, in the semiconductor booster circuit according to the first aspect, a voltage detector detects an output voltage of the output rectifier and controls supply of the booster clock by the clock generator based on the output voltage. It is characterized by comprising means.
[0020]
According to a third aspect of the present invention, in the semiconductor booster circuit according to the first or second aspect, at least an output side of the output rectifier has a regulator circuit for reducing the output voltage of the output rectifier to stabilize the output voltage. It is characterized by connecting one.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0022]
(Embodiment 1)
FIG. 1 is a circuit diagram showing a semiconductor booster circuit according to the first embodiment, in particular, a charge pump type booster circuit here. Parts corresponding to those of the conventional example shown in FIG. 4 are denoted by the same reference numerals.
[0023]
Also in the first embodiment, the diodes D _{1 to} Dn are connected in series, and the boosting capacitive elements C _{1 to} Cn are connected to the cathodes of the respective diodes D _{1 to} Dn, so that a plurality of pump blocks 1 are connected. _The point that the charge pump means 10 composed of _{1 to} 1n is configured is the same as that of the conventional example shown in FIG.
[0024]
Features of the first embodiment, each pump block 1 ₁ 1n output respectively rectifying diode Do ₁ ～Don through a single connected to the output terminal 6 output rectifying means 4 are constituted. Moreover, from the clock generating means 2, the clock _CLK 1 ～CLKn boosting in accordance with the number of each pump block ₁ 1 1n are generated, each clock _CLK 1 ～CLKn each individually each pump block ₁ 1 1n.
[0025]
In this case, among the boosting clocks CLK _{1 to} CLKn output from the clock generating means 2, the even-numbered clocks CLK ₂ , CLK ₄ ,... And the odd-numbered clocks CLK ₁ , CLK ₃ ,. It has the same frequency and and phase opposite to each other, each clock CLK ₁ ~CLKn is both at the L level to the GND level, when the H level is set to be Vdd level of the power supply voltage.
[0026]
The operation of the semiconductor booster configured as described above will be described.
[0027]
In the normal case where all of the boosting clocks CLK1 to CLKn are output from the clock generating means 2, the output voltage Vpp obtained at the output terminal 6 is obtained similarly to the conventional charge pump type boosting circuit having the configuration shown in FIG. Finally becomes (n + 1) · (Vdd−Vd).
[0028]
However, such a transient operation until reaching the final output voltage Vpp = (n + 1) · (Vdd−Vd) is slightly different from the operation of the conventional circuit shown in FIG.
[0029]
That is, when the output voltage Vpp is low, first, supplying a charge to Vpp to the output terminal 6 from the node _{N 1} of the pump block _{1 1} via the diode Do _1.
[0030]
When the potential Vpp of the output terminal 6 is gradually increased, the diode Do ₁ since a reverse bias, the operation is stopped.
[0031]
Then, supplies charges to Vpp from the node _{N 2} is boosted from the node _{N 1} through the diode Do _2. When the potential Vpp of the output terminal 6 is gradually increased, the diode Do ₂ since a reverse bias, the operation is stopped.
[0032]
By repeating the above operation, the final output voltage Vpp of the output terminal 6 becomes (n + 1) · (Vdd−Vd).
[0033]
Here, for example, when a voltage of n · (Vdd−Vd) is required as the output voltage Vpp in a certain operation mode, a clock control signal is supplied from a control circuit such as a microcomputer (not shown) at this time. Te, of the clock CLK ₁ ~CLKn boosting being output from the clock generation unit 2, and stops only the output of the clock CLKn supplied to the pump block 1n of the n-th stage.
[0034]
Then, although the step-up operation in the pump block 1n is stopped, the clock _CLK 1 _{~CLKn -1} is added continuously it than in the pump block ₁ 1 _{1n -1} in the preceding stage, (n The potential of the node Nn- ₁ of the (-1) th stage pump block 1n- ₁ is boosted to (n-1). (Vdd-Vd).
[0035]
At this time, the by the rectifier circuit consisting of _{Don -1} and Co (n-1) because the potential of the node _{Nn -1} th stage of the pump block _{1n -1} to peak hold, the final output obtained at the output terminal 6 The voltage Vpp is n · (Vdd−Vd). In this case, the other rectifying diodes Do _{1 to} Don ₋₂ do not operate because they are reverse biased.
[0036]
As can be seen from this, by stopping the clock output sequentially from the boosting clock having the larger clock number, the potential of the final output voltage Vpp obtained at the output terminal 6 decreases.
[0037]
That is, by controlling whether to supply or stop the boosting clocks CLK _{1 to} CLKn from the clock generating means 2, it is possible to arbitrarily obtain an output that is an integral multiple of (Vdd−Vd) as the value of the output voltage Vpp. Can be.
[0038]
As described above, in the first embodiment, a plurality of output voltages can be obtained by one charge pump type booster circuit by controlling the supply of the booster clock. It is not necessary to separately provide a booster circuit for each.
[0039]
When a voltage lower than the peak voltage is output, the supply of the clock is sequentially stopped from the boosting clock having the larger clock number, so that the potential of the final output voltage Vpp can be lowered to obtain a desired voltage.
[0040]
Further, at this time it is possible to achieve low power consumption it is possible to stop the unnecessary clock completely Incidentally, in the first embodiment, the diode D ₁ -Dn as components of the pump block 1 ₁ 1n Although the diodes Do1 to Don are also used as the output rectifying means 4, the same effect can be obtained by using MOS transistors instead of these diodes. Although the positive boost has been described, a negative boost charge pump type boost circuit can be realized by changing the directions of the anodes and cathodes of the diodes D _{1 to} Dn and Do _{1 to} Don.
[0041]
Further, the charge pump type booster circuit used in the first embodiment is a very basic circuit, and the same effect can be obtained by a threshold voltage canceling type or a complementary type charge pump type booster circuit. it can.
[0042]
Although the boosting clocks are independent clocks in the first embodiment, the same effect can be obtained by combining a plurality of clocks. However, in this case, although the number of voltages for which the output voltage can be adjusted is reduced, the reduction in the number of voltages to be adjusted is advantageous in terms of area by reducing the clock and the clock wiring area.
[0043]
Although the rectifier diode Do ₁ ~Don connected to each pump block 1 ₁ 1n, it can be connected only to a part of the pump block to obtain the same effect. In this case, however, the number of voltages for which the output voltage can be adjusted is reduced, but the amount of voltage to be adjusted can be reduced, so that rectifying diodes can be reduced, which is advantageous in area.
[0044]
(Embodiment 2)
FIG. 2 is a circuit diagram showing a semiconductor booster circuit according to the second embodiment, in particular, a charge pump type booster circuit. Here, the same reference numerals are used for parts corresponding to the first embodiment shown in FIG. Attach.
[0045]
The feature of the second embodiment is that a voltage detecting means 3 for inputting an output voltage Vpp applied to an output terminal 6, detecting the value, and controlling the clock generating means 2 based on the detected signal is added. That is.
[0046]
The other configuration is the same as that of the first embodiment shown in FIG. 1, and the detailed description is omitted here.
[0047]
The operation of the semiconductor booster configured as described above will be described.
[0048]
In the circuit shown in FIG. 2 as well, in the normal case where all of the boosting clocks CLK1 to CLKn are output from the clock generating means 2 and when the external power supply voltage Vdd is stable, Similarly, the output voltage Vpp obtained at the output terminal 6 finally becomes (n + 1) · (Vdd−Vd).
[0049]
In addition, by stopping the output of the boosting clocks CLK _{1 to} CLKn in ascending order of the clock number, an output of an integer multiple of (Vdd−Vd) can be selectively obtained as the value of the output voltage Vpp. This is the same as in the first embodiment.
[0050]
Further, the second embodiment has the following features.
[0051]
Normally, it is considered that the external power supply voltage Vdd constantly fluctuates due to noise or a voltage drop caused by a load current flowing.
[0052]
Here, since the final output voltage Vpp from the output terminal 6 in the normal operation in the circuit of FIG. 2 is (n + 1) · (Vdd−Vd), for example, it is assumed that Vd = 0.5V and n = 6. , Vdd = 3V, Vpp = 17.5V, and when Vdd = 3.5V, Vpp = 21V. That is, the output voltage Vpp fluctuates according to the fluctuation of the external power supply voltage Vdd.
[0053]
Therefore, the potential of the output voltage Vpp is detected by the voltage detecting means 3, and when the output voltage Vpp is higher than the desired voltage, the clock generating means 2 stops the supply of the clock sequentially from the boosting clock having the larger clock number. Control. By doing so, the potential of the final output voltage Vpp can be gradually lowered to approach a desired voltage.
[0054]
Conversely, when the output voltage Vpp is lower than the desired voltage, the clock generating means starts the supply of clocks sequentially from the booster block having the smaller clock number among the booster clocks currently stopped. 2 control. By doing so, the final output voltage Vpp can be gradually increased to approach a desired voltage.
[0055]
As a specific example, when the desired output voltage Vpp from the output terminal 6 is 17.5 V, when the power supply voltage Vdd fluctuates to 3.5 V, the output voltage Vpp becomes 21 V and is too high as it is. since, this was detected by the voltage detection unit 3 performs control so as to control the clock generation unit 2 stops the supply of the booster clock CLK _6. Then, the boosting operation of the sixth-stage pump block ₁₆ stops, and only the five-stage pump blocks ₁₁ to ₁₅ perform the boosting operation. Therefore, the output voltage Vpp becomes 18 V, and the desired output when Vdd = 3 V is obtained. The voltage can approach 17.5V.
[0056]
As described above, according to the second embodiment, the level of one output voltage Vpp obtained by the output rectifier 4 can be arbitrarily set by controlling the supply of the boosting clocks CLK _{1 to} CLKn. Sometimes, unnecessary clock generation can be completely stopped, so that low power consumption can be realized.
[0057]
Further, as a feature of the second embodiment, even when the output voltage Vpp fluctuates due to the fluctuation of the external power supply voltage Vdd, the output voltage Vpp is detected by the voltage detecting means 3 and the boosting clock is generated by the clock generating means 2. By controlling the supply, a stable output voltage can always be obtained, which is advantageous from the viewpoint of reliability.
[0058]
In the second embodiment, using a diode _D 1 -Dn as components of the pump block ₁ 1 1n, also it was also using the diode Do1~Don as output rectifying means 4, these diodes A similar effect can be obtained by using a MOS transistor instead. Although the positive boost has been described, a negative boost charge pump type boost circuit can be realized by changing the directions of the anodes and cathodes of the diodes D _{1 to} Dn and Do _{1 to} Don.
[0059]
Further, the charge pump type booster circuit used in the first embodiment is a very basic circuit, and the same effect can be obtained by a threshold voltage canceling type or a complementary type charge pump type booster circuit. it can.
[0060]
Although this embodiment 2, the step-up clock CLK ₁ ~CLKn were each independent clock can be a plurality of collectively obtain the same effect. However, in this case, although the number of voltages for which the output voltage can be adjusted is reduced, the reduction in the number of voltages to be adjusted is advantageous in terms of area by reducing the clock and the clock wiring area.
[0061]
Although the rectifier diode Do ₁ ~Don connected to each pump block 1 ₁ 1n, it can be connected only to a part of the pump block to obtain the same effect. In this case, however, the number of voltages for which the output voltage can be adjusted is reduced, but the amount of voltage to be adjusted can be reduced, so that rectifying diodes can be reduced, which is advantageous in area.
[0062]
(Embodiment 3)
FIG. 3 is a circuit diagram showing a semiconductor booster circuit according to the third embodiment, in particular, a charge pump type booster circuit in this case. Parts corresponding to the second embodiment shown in FIG. 2 are denoted by the same reference numerals. .
[0063]
Features the third embodiment, in addition to the output terminal 6 ₀ on the output side of the output rectifying means 4 are provided, and inputs the output voltage Vpp obtained by this output rectifying means 4, the output voltage a plurality of regulator circuits 5 ₁ ~5m stabilizing steps down to a predetermined respective voltage Vpp is that are connected in parallel.
[0064]
The other configuration is the same as that of the second embodiment shown in FIG. 2, and the detailed description is omitted here.
[0065]
The operation of the semiconductor booster configured as described above will be described.
[0066]
In the circuit shown in FIG. 3, the same portions as those shown in FIG. 2 perform the same operations as those in the second embodiment. That is, in the normal case where all the clocks CLK1 to CLKn for boosting are output from the clock generation means 2 and when the external power supply voltage Vdd is stable, the output terminal The output voltage Vpp obtained in 6 finally becomes (n + 1) · (Vdd−Vd).
[0067]
In addition, by stopping the output of the boosting clocks CLK _{1 to} CLKn in ascending order of the clock number, it is possible to arbitrarily obtain an output that is an integer multiple of (Vdd−Vd) as the value of the output voltage Vpp. This is the same as in the second embodiment.
[0068]
Furthermore, to detect the output voltage Vpp by the voltage detection means 3, each clock CLK ₁ ~CLKn output voltage Vpp is controlled to the supply of boosting output from the clock generation unit 2 according to the fluctuation of the output voltage Vpp The point that it can be stabilized is the same as in the case of the second embodiment.
[0069]
Further, the third embodiment has the following features.
[0070]
In some cases, a semiconductor device requires a plurality of types of voltages other than the external power supply voltage Vdd at the same time.
[0071]
As can respond to such a request, as well as taken out directly from the output terminal 6 of the output voltage Vpp obtained at the output rectifying means 4, must be individually step down the output voltage Vpp at each of the regulator circuits 5 ₁ ~5m Supply voltage Vpp _{1 to} Vppm. Note that, naturally, Vpp ≧ Vpp _{1 to} Vppm.
[0072]
As described above, according to the third embodiment, it is possible to arbitrarily set the level of one output voltage Vpp obtained by output rectifier 4 by the operation of supplying boosting clocks CLK _{1 to} CLKn. Since unnecessary clock generation can be completely stopped, low power consumption can be realized.
[0073]
Further, even when the output voltage Vpp fluctuates due to the fluctuation of the external power supply voltage Vdd, the output voltage Vpp is detected by the voltage detecting means 3 and the supply of the boosting clock by the clock generating means 2 is controlled, so that it is always stable. Output voltage can be obtained, which is advantageous from the viewpoint of reliability.
[0074]
Further, to obtain a plurality of regulator circuit ₅ 1 ～5M connected in parallel to the output rectifying means 4, from a single output voltage Vpp obtained at the output rectifying means 4, a plurality of output voltage _Vpp 1 ～Vppm lower than this at the same time be able to. Therefore, at the same time a plurality of boosted voltage Vpp, when Vpp ₁ ~Vppm is required, as in the prior art, each need not be provided separately boosting circuit for each desired boosted voltage, the area advantageous.
[0075]
In the third embodiment, using a diode _D 1 -Dn as components of the pump block ₁ 1 1n, also it was also using the diode Do1~Don as output rectifying means 4, these diodes A similar effect can be obtained by using a MOS transistor instead. Although the positive boost has been described, a negative boost charge pump type boost circuit can be realized by changing the directions of the anodes and cathodes of the diodes D _{1 to} Dn and Do _{1 to} Don.
[0076]
Further, the charge pump type booster circuit used in the third embodiment is a very basic circuit, and a similar effect can be obtained by a threshold voltage canceling type or complementary type charge pump type booster circuit. it can.
[0077]
Although the boosting clocks are independent clocks in the third embodiment, the same effect can be obtained by combining a plurality of clocks. However, in this case, although the number of voltages for which the output voltage can be adjusted is reduced, the reduction in the number of voltages to be adjusted is advantageous in terms of area by reducing the clock and the clock wiring area.
[0078]
Although the rectifier diode Do ₁ ~Don connected to each pump block 1 ₁ 1n, it can be connected only to a part of the pump block to obtain the same effect. In this case, however, the number of voltages for which the output voltage can be adjusted is reduced, but the amount of voltage to be adjusted can be reduced, so that rectifying diodes can be reduced, which is advantageous in area.
[0079]
【The invention's effect】
As described above, the semiconductor booster circuit of the present invention has the following effects.
[0080]
(1) According to the first aspect of the present invention, since the supply of the boosting clocks can be controlled independently, the number of stages of the pump block performing the boosting operation can be adjusted. Can output a plurality of voltages arbitrarily.
[0081]
(2) In the invention according to the second aspect, the output voltage is detected by the voltage detecting means and the supply of the boosting clock based on the output voltage is adjusted, so that the output voltage is always stabilized even if the power supply voltage fluctuates. And increase the reliability.
[0082]
(3) In the configuration of claim 1 or claim 2, if there is a boosting clock whose supply is stopped, unnecessary clock generation can be completely stopped, so that power consumption can be reduced.
[0083]
(4) In the invention according to claim 3, a plurality of regulator circuits can simultaneously output a plurality of output voltages lower than the output voltage Vpp of the output rectifier, so that even when a plurality of boosted voltages are required. Since only one booster circuit is required, it is advantageous in terms of area.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a semiconductor booster circuit according to a first embodiment of the present invention; FIG. 2 is a circuit diagram of a semiconductor booster circuit according to a second embodiment of the present invention; FIG. FIG. 4 is a circuit diagram of a conventional semiconductor booster circuit.
1 1 to ₁ n Pump block 2 Clock generation means 3 Voltage detection means 4 Power rectification means 51 _{1 to} 5 m Regulator circuit 10 Charge pump means

Claims (3)

Charge pump means for generating a boosted voltage by connecting a plurality of pump blocks performing a boosting operation by charging / discharging the capacitive element by the boosting clock and generating a boosted voltage;
A clock generating means capable of controlling the supply of the boost clock for each of the pump block constituting the charge pump means,
And an output rectifying means formed by connecting the capacitive element through the rectifying diode of the output of the pump block, one output even without least in the charge pump means,
In order to obtain a desired boosted voltage from the output rectifier, the clock generator stops supplying the boosted clock from a subsequent stage of the pump block constituting the charge pump, and determines the number of stages of the pump block to be operated. A semiconductor circuit characterized by adjusting . 2. The semiconductor booster circuit according to claim 1, further comprising: a voltage detector that detects an output voltage of the output rectifier and controls supply of the boosting clock by the clock generator based on the output voltage. 3. The semiconductor booster circuit according to claim 1, wherein at least one regulator circuit for lowering and stabilizing an output voltage of the output rectifier is connected to an output side of the output rectifier.

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