CN111176366B - Wide-voltage memory current mirror circuit - Google Patents
Wide-voltage memory current mirror circuit Download PDFInfo
- Publication number
- CN111176366B CN111176366B CN201811347356.7A CN201811347356A CN111176366B CN 111176366 B CN111176366 B CN 111176366B CN 201811347356 A CN201811347356 A CN 201811347356A CN 111176366 B CN111176366 B CN 111176366B
- Authority
- CN
- China
- Prior art keywords
- module
- voltage
- output end
- pmos tube
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
Abstract
The embodiment of the invention provides a wide-voltage memory current mirror circuit, and relates to the field of current mirror circuits. The circuit includes: the voltage stabilization module, reference current module, step-down module, pre-discharge circuit module, the voltage stabilization module includes: first voltage output, second voltage output, voltage stabilization module is connected with power VDD, first voltage output connects the reference current module, second voltage output connects the voltage reduction module, pre-discharge circuit module connects second voltage output, pre-discharge circuit module is used for after voltage stabilization module work, when receiving first pulse width signal, reduce the voltage of second voltage output, in order to reduce the voltage of first output. The invention effectively shortens the establishment time of the stable current mirror circuit of the wide voltage memory when the power supply voltage is lower, and improves the reading performance of the memory.
Description
Technical Field
The present invention relates to the field of current mirror circuits, and in particular, to a wide voltage memory current mirror circuit.
Background
The memory is a memory device used for storing information in modern information technology and is widely applied to various aspects.
The current memory needs to support various power supply voltages according to market demands, the current mirror circuit of the current wide-voltage memory has a faster establishment speed when the power supply voltage is ensured to be greater than or equal to 2V, but the establishment speed between 1.6V and 2V is much slower, the current mirror circuit of the current wide-voltage memory refers to fig. 1 in the attached drawings of the specification, and the working principle of the current mirror circuit of the current wide-voltage memory is that when the wide-voltage memory performs a reading operation, the control module sends an enable signal en _ b (9), the enable signal en _ b (9) controls the conduction of the PMOS tubes P1(10), P2(11) and P4(12), the PMOS tube P3(13) starts to be conducted after the PMOS tube P1(10) is conducted, the reference voltage Vref (14) conducts the NMOS tube N2(15), the source of the NMOS tube N2(15) generates a reference current at this time, the PMOS tube P5(19) starts to be conducted after the PMOS tube P4(12) is conducted, the drain of the PMOS tube P5(19) generates a mirror current, according to the principle of current mirror circuit, the magnitude of the mirror current is based on the reference current, when the NMOS transistor N2(15) is turned on, the drain voltage vc (16) thereof, which is also the gate voltage of the NMOS transistor N1(17), causes the NMOS transistor N1(17) to start to be turned on, the source voltage vg (18) of the NMOS transistor N1(17) to be generated, the source of the NMOS transistor N1(17) to generate a discharge current, the source voltage vg (18) of the NMOS transistor N1(17) is also the gate voltages of the PMOS transistor P3(13) and the PMOS transistor P5(19), at this time, the source voltage vg (18) and the drain voltage vc (16) have voltage values just enough to cause the PMOS transistor P3(13) and the NMOS transistor N2(15) to work in the saturation region, the source voltage vg (18) starts to gradually rise with the gradual turn on of the NMOS transistor N1(17), and the source voltage vg (18) of the NMOS transistor N382 (17) of the NMOS transistor N1(17) is equal to the source voltage vc (17) of the NMOS transistor N1 plus the NMOS transistor N1 of the NMOS transistor N3817, when the source voltage vg (18) rises, so that the voltage value of the gate voltage vc (16) rises, the voltages of vg (18) and vc (16) overshoot at the beginning of the conduction of P1(10) and P2(11), and the voltages are greater than the target voltage value. As the voltage value of the gate voltage vc (16) increases, the NMOS transistor N2(15) cannot operate in the saturation region, and the reference current is affected and becomes unstable, and the mirror current becomes unstable, and the discharge current generated at the source of the NMOS transistor N1(17) is used to discharge to the ground, so as to reduce the voltage value of the source voltage vg (18), and finally, the voltage value of the source voltage vg (18) is stabilized at the target voltage value that can satisfy the PMOS transistor P3(13), and the NMOS transistor N2(15) operates in the saturation region, so that the current mirror circuit is established.
However, the circuit has a problem that, in the current wide voltage memory designed for power supply voltages of 1.6V to 2V, the discharge current for reducing the voltage value of the source voltage vg (18) is relatively small, because if the discharge current is designed to be relatively large, the voltage value of the source voltage vg (18) is relatively low, so that the PMOS transistor P1(10) cannot work in a saturation region, which affects the stability of the reference current, and the relatively small discharge current needs a relatively long time to reduce the voltage value of the excessively high source voltage vg (18) to a proper voltage, so that the reference current needs a relatively long time to be stabilized, and thus the mirror current needs a relatively long time to be stably copied, so that the current mirror circuit needs a relatively long time to be established.
Disclosure of Invention
In view of the above problems, the present invention provides a wide voltage memory current mirror circuit, which solves the problem that the current mirror circuit needs to be established for a long time in the prior art because the discharge current is small and the mirror current needs a long time to be stably copied.
In order to solve the above technical problem, an embodiment of the present invention provides a wide voltage memory current mirror circuit, where the circuit includes:
the device comprises a voltage stabilizing module, a reference current module, a voltage reducing module, a pre-discharging circuit module and a mirror current module;
the power stabilizing module includes: the power supply stabilizing module is connected with a power supply VDD;
the first voltage output end is connected with the reference current module, and the second voltage output end is connected with the voltage reduction module and the mirror current module;
the pre-discharge circuit module is connected with the second voltage output end and the mirror current module, and is used for reducing the voltage of the second voltage output end after the voltage stabilizing module works and when a first pulse width signal is received so as to reduce the voltage of the first output end.
The mirror current module is connected with the second voltage output end and the pre-discharge circuit module, and is used for generating mirror current.
Optionally, the circuit further includes a pulse width generation module, connected to the pre-discharge circuit module, and configured to generate the first pulse width signal and send the first pulse width signal to the pre-discharge circuit module.
Optionally, the pulse width generating module includes:
the device comprises a pulse width signal sending module and a first inverter;
the output end of the pulse width signal sending module is connected with the input end of the first phase inverter, and the output end of the first phase inverter outputs the first pulse width signal;
and the output end of the first inverter is connected with the pre-discharge circuit module.
Optionally, the circuit further comprises a mirror current module;
the mirror current module comprises a fourth PMOS tube and a fifth PMOS tube, a source electrode of the fourth PMOS tube is connected with a power supply VDD, a grid electrode of the fourth PMOS tube is connected with the second phase inverter, a drain electrode of the fourth PMOS tube is connected with a source electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is respectively connected with the pre-discharge circuit module and the second voltage output end, and the mirror current module is used for copying mirror current.
Optionally, the wide-voltage memory current mirror circuit is applied to a memory, and the memory further comprises a control module;
the control module is respectively connected with the pulse width generation module and the second inverter, and is used for sending a first enable signal to the pulse width generation module and sending a second enable signal to the second inverter, wherein the first enable signal is used for controlling the pulse width generation module to send a first pulse width signal, and the second enable signal is used for controlling the second inverter to send a first low level signal.
Optionally, the voltage stabilizing module further includes: the PMOS transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor and a first NMOS (N-channel metal oxide semiconductor) transistor;
the grid electrode of the first PMOS tube is respectively connected with the second PMOS tube and the second phase inverter, the source electrode of the first PMOS tube is connected with a power supply VDD, and the drain electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube;
the grid electrode of the second PMOS tube is respectively connected with the first PMOS tube and the second phase inverter, the source electrode of the second PMOS tube is connected with a power supply VDD, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube;
the grid electrode of the third PMOS tube is connected with the source electrode of the first NMOS tube, the source electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the third PMOS tube is respectively connected with the first voltage output end and the grid electrode of the first NMOS tube;
the grid electrode of the first NMOS tube is respectively connected with the drain electrode of the third PMOS tube, the first voltage output end is connected, the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube, and the source electrode of the first NMOS tube is respectively connected with the grid electrode of the third PMOS tube and the second voltage output end;
the voltage stabilizing module is used for generating voltage at the first voltage output end and the second voltage output end when receiving a first low level signal.
Optionally, the reference current module includes a second NMOS transistor, a gate of the second NMOS transistor is connected to a preset voltage, a drain of the second NMOS transistor is connected to the first voltage output terminal, and the reference current module is configured to generate a reference current.
Optionally, the pre-discharge circuit module includes: the two NMOS tubes are connected in series;
or the pre-discharge circuit module is provided with more than two NMOS tubes, and the more than two NMOS tubes are connected in series or in parallel.
Optionally, the mirror current module includes: a fourth PMOS tube and a fifth PMOS tube;
the source electrode of the fourth PMOS tube is connected with a power supply VDD, the grid electrode of the fourth PMOS tube is connected with the second phase inverter, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube;
and the source electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the grid electrode of the fifth PMOS tube is respectively connected with the second voltage output end and the pre-discharge circuit module.
Optionally, the pulse width signal sending module includes:
the first NOR gate, the second NOR gate, the third NOR gate, the first resistor, the second resistor, the first NOR gate and the first capacitor;
the output end of the second inverter is connected with the input ends of the first NOR gate and the first NOT gate;
the output end of the first NOT gate is connected with one end of a series loop formed by the first resistor and the second resistor;
the other end of the series circuit is simultaneously connected with one end of the first capacitor and the input end of the second NOT gate, and the other end of the first capacitor is grounded;
the output end of the second NOT gate is connected with the input end of the third NOT gate;
the output end of the third not gate is connected with the input end of the first nor gate;
the output end of the first NOR gate is connected with the input end of the first inverter;
the output end of the first inverter is connected with the pre-discharge circuit module, and the output end of the first inverter generates a high level signal, which is the first pulse width signal.
Compared with the existing current mirror circuit applied to the wide-voltage memory, the wide-voltage memory current mirror circuit provided by the invention has the advantages that when the wide-voltage memory performs read-write operation, the pre-discharge circuit module is controlled to be started through the first pulse width signal, and during the starting period of the pre-discharge circuit module, discharge current is generated and discharged together with the discharge current originally used for reducing the voltage of the second output end, so that the time for reducing the voltage of the second voltage output end from a value higher than a target voltage value to the target voltage value is shortened, the establishment time of the wide-voltage memory current mirror circuit is effectively shortened, and the reading performance of the memory is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a diagram of a current mirror circuit of a conventional wide voltage memory;
FIG. 2 is a block diagram of a wide voltage memory current mirror circuit according to the present invention;
fig. 3 is a structural diagram of a wide voltage memory current mirror circuit according to the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Referring to fig. 2, a module schematic diagram of a current mirror circuit of a wide voltage memory according to the present invention may specifically include: the voltage stabilization module 20, the reference current module 30, the voltage reduction module 50, the pre-discharge circuit module 60, and the mirror current module 40.
The power stabilizing module 20 includes: the voltage stabilizing module 20 is connected with a power supply VDD, the first voltage output end 201 is connected with a drain electrode of a second NMOS transistor in the reference current module 30, the second voltage output end 202 is connected with the voltage reducing module 50 and the mirror current module 40, the mirror current module is connected with a second voltage output end and the pre-discharge circuit module, the pre-discharge circuit module 60 is connected with the second voltage output end 202 and the mirror current module 40, and the pre-discharge circuit module 60 is used for reducing the voltage of the second voltage output end 202 after the voltage stabilizing module 20 works and when receiving a first pulse width signal, so as to reduce the voltage of the first output end 201. It should be noted that the first pulse width signal operates within a preset time, which can be obtained through experimental simulation, and the preset time is less than the time when the voltage at the second voltage output end decreases from the time higher than the target voltage value to the time of the target voltage value.
Optionally, referring to fig. 3, the circuit of the present invention further includes a pulse width generating module 70, where the pulse width generating module 70 is configured to generate the first pulse width signal pulse.
The pulse width generating module 70 includes a pulse width signal issuing module 701 and a first inverter 702, where the pulse width signal issuing module 701 may include a first not gate inv1, a second not gate inv2, a third not gate inv3, a first resistor R2, a second resistor R3, a first nor gate nand1, and a first capacitor C2. Of course, the embodiment of the present invention does not limit the specific structure of the pulse width generating module.
The first enable output end of the control module in the wide voltage memory is connected with the input ends of nand1 and inv1, the output end of inv1 is connected with one end of R2, the other end of R2 is connected with R3 in series, the other end of R3 is connected with one end of C2 and the input end of inv2 at the same time, the other end of C2 is grounded, the output end of inv2 is connected with the input end of inv3, the output end of inv3 is connected with the input end of nand1, the output end of nand1 is connected with the input end of the first inverter 702, the output end of the first inverter 702 is connected with the pre-discharge circuit module 60, the output end of the first inverter 702 outputs a first pulse width signal pulse, the pulse is a high level signal, and the pulse controls the opening of the pre-discharge circuit module 60 to generate discharge current. The partial circuit realizes the sending of a high level signal by using a pulse width generating module, has simple and practical circuit structure, uses less electric elements and has higher reliability.
The pulse width generating module in the above embodiments may also be composed of circuits formed by other electrical components, and the embodiments of the present invention are not limited thereto.
Optionally, referring to fig. 3, the circuit of the present invention is applied to a wide voltage memory, the memory has a control module, the control module is respectively connected to the second inverter 801 and the pulse width generating module 70, and it functions that when the memory performs a read operation, the memory control module sends a first enable signal en1 to the pulse width generating module 70 through a first enable output terminal, and sends a second enable signal en2 to the second inverter 801 through a second enable output terminal, the first enable signal en1 is used to control the pulse width generating module 70 to send a first pulse width signal pulse, and the second enable signal en2 is used to control the second inverter 801 to send a first low level signal en _ b.
Optionally, referring to fig. 3, the voltage stabilizing module 20 in the circuit of the present invention further includes: a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3 and a first NMOS transistor N1, the gate of the first PMOS transistor P1 is connected to the second PMOS transistor P2 and the second inverter 801 respectively, the source of the first PMOS transistor P1 is connected to the power supply VDD, the drain of the first PMOS transistor P1 is connected to the source of the third PMOS transistor, when the second inverter 801 sends a first low level signal en _ b, the first PMOS transistor P1 is turned on, the gate of the second PMOS transistor P2 is connected to the first PMOS transistor P1 and the second inverter 801 respectively, the source of the second PMOS transistor P2 is connected to the power supply VDD, the drain of the second PMOS transistor P2 is connected to the source of the first NMOS transistor N1, when the second inverter 801 sends a first low level signal en _ b, the second PMOS transistor P365 is turned on, the gate of the third PMOS transistor P3 is connected to the source of the first NMOS transistor N1, the third PMOS transistor P59628 is connected to the drain of the first PMOS transistor P632 and the drain of the first NMOS transistor P82573201 respectively, when the first PMOS transistor P1 is turned on, the third PMOS transistor P3 starts to be turned on, the first voltage output terminal 201 generates a voltage, the gate of the first NMOS transistor N1 is connected to the drain of the third PMOS transistor P3 and the first voltage output terminal 201, the drain of the first NMOS transistor N1 is connected to the drain of the second PMOS transistor P2, the source of the first NMOS transistor N1 is connected to the gate of the third PMOS transistor P3 and the second voltage output terminal 202, and when the second PMOS transistor P2 is turned on, the first N2 is turned on
The MOS transistor N1 begins to conduct and the second voltage output terminal 202 generates a voltage.
Optionally, referring to fig. 3, the reference current module 30 of the circuit of the present invention includes a second NMOS transistor N2, a gate of the second NMOS transistor N2 is connected to the preset voltage Vref, a drain of the second NMOS transistor N2 is connected to the first voltage output terminal 201, and when the third PMOS transistor P3 starts to be turned on and the first voltage output terminal 201 generates a voltage, the reference current module 30 generates a reference current.
Optionally, referring to fig. 3, the pre-discharge circuit module 60 of the circuit of the present invention includes at least two NMOS transistors, and different charging currents are obtained through different combinations of the series-connected or parallel-connected NMOS transistors, and if there are only two NMOS transistors in the pre-discharge circuit module 60, the two NMOS transistors are connected in series; if there are more than two NMOS transistors in the pre-discharge circuit module 60, the more than two NMOS transistors are connected in series or in parallel.
Optionally, referring to fig. 3, the mirror current module of the circuit of the present invention includes: the source electrode of the fourth PMOS tube is connected with a power supply VDD, the grid electrode of the fourth PMOS tube is connected with the second phase inverter, the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube, when the second phase inverter 801 sends a first low level signal en _ b, the fourth PMOS tube is conducted, the source electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube is respectively connected with the second voltage output end and the pre-discharge circuit module, when the fourth PMOS tube is conducted, the fifth PMOS tube is conducted, the mirror current module generates mirror current, and the size of the mirror current takes the reference current as a benchmark.
In summary, comparing fig. 3 with the prior art circuit, the working principle of the circuit of the present invention is: when the wide voltage memory performs a read operation, the control module sends out a second enable signal en2, the second enable signal en2 outputs a first low level signal en _ b through the second inverter 801, the first low level signal en _ b makes the PMOS transistors P1, P2 and P4 turned on, the P3 starts to be turned on after the PMOS transistor P1 is turned on, the first voltage output terminal generates a voltage, the reference voltage Vref turns on the NMOS transistor N2, at this time, the source of the NMOS transistor N2 generates a reference current, the P5 starts to be turned on after the PMOS transistor P4 is turned on, the drain of the PMOS transistor P5 generates a mirror current, according to the principle of a current mirror circuit, the size of the mirror current is based on the reference current, when the NMOS transistor N2 is turned on, the voltage generated by the first voltage output terminal is the drain voltage vc thereof, and is the gate voltage of the NMOS transistor N1, the gate voltage makes the NMOS transistor N1 be turned on, the source voltage vg (18) of the NMOS transistor N1 generates a terminal voltage, which is the second output voltage (18), the source of the NMOS transistor N1 generates a discharge current, which is very small and cannot catch up with the voltage rise of the source voltage vg (18), the control module sends the enable signal en2 and also sends the first enable signal en1 to the pulse width generation module 70, the first enable signal en1 controls the pulse width generation module 70 to send the first pulse width signal pulse, the first pulse width signal pulse controls the pre-discharge circuit module 60 to turn on, the pre-discharge circuit module 60 generates a discharge current, and since one end of the pre-discharge circuit module 60 is grounded, the discharge current flows into the ground terminal, and the discharge current discharges together with the discharge current generated by the source of the NMOS transistor N1, so that the time for the rapidly rising source voltage vg (18) to fall to the target voltage value is shorter than the time for the source voltage vg (18) to fall by the discharge current generated by the source of the NMOS transistor N1 before. The duration of the first pulse width signal pulse is selected to decrease vg (18) to approach the target voltage, so that the small current at the source of the NMOS transistor N1 can more quickly reach vg (18) to the target voltage. After the first pulse width signal pulse lasts for the preset working time, the first pulse width signal pulse is ended, the pre-discharge circuit module 60 ends the discharge to the ground, the discharge current generated by the source electrode of the NMOS transistor N1 continues to work until the voltage value of the source electrode voltage vg (18) is stabilized at the target voltage value, the target voltage value can meet the voltage value that both the PMOS transistor P3 and the NMOS transistor N2 work in the saturation region, the reference current is stable at this time, the mirror current is also stable, and the establishment of the current mirror circuit is completed.
The discharge current of the pre-discharge circuit module 60 in the circuit of the present invention can obtain different current magnitudes according to the number of MOS transistors and the difference of the combination manner, the specific magnitude is obtained by the design of the wide voltage memory and the experimental simulation, which is not described herein in detail, and some combinations of MOS transistors can be reserved for selection during the design.
The pulse width generation module and the pre-discharge circuit module used in the embodiment of the invention have the advantages of simple overall circuit structure, less used electric elements, higher reliability of the circuit, accurate and controllable discharge current and perfectly shortened establishment time of the current mirror circuit of the wide voltage memory.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The above detailed description is made on the current mirror circuit of the wide voltage memory provided by the present invention, and the principle and the implementation of the present invention are explained by applying a specific example, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (9)
1. A wide voltage memory current mirror circuit, the circuit comprising:
the device comprises a voltage stabilizing module, a reference current module, a voltage reducing module, a pre-discharging circuit module and a mirror current module;
the voltage stabilization module includes: the voltage stabilizing module is connected with a power supply VDD;
the first voltage output end is connected with the reference current module, and the second voltage output end is connected with the voltage reduction module and the mirror current module;
the pre-discharge circuit module is connected with the second voltage output end and the mirror current module, and is used for reducing the voltage of the second voltage output end when receiving a first pulse width signal after the voltage stabilizing module works so as to reduce the voltage of the first voltage output end;
the mirror current module is connected with the second voltage output end and the voltage reduction module, and the mirror current module is used for generating mirror current.
2. The circuit of claim 1, further comprising a pulse width generation module coupled to the pre-discharge circuit module for generating and sending the first pulse width signal to the pre-discharge circuit module.
3. The circuit of claim 2, wherein the pulse width generation module comprises:
the device comprises a pulse width signal sending module and a first inverter;
the output end of the pulse width signal sending module is connected with the input end of the first phase inverter, and the output end of the first phase inverter outputs the first pulse width signal;
and the output end of the first inverter is connected with the pre-discharge circuit module.
4. The circuit of claim 1, further comprising a mirror current module;
the mirror current module comprises a fourth PMOS tube and a fifth PMOS tube, a source electrode of the fourth PMOS tube is connected with a power supply VDD, a grid electrode of the fourth PMOS tube is connected with the second phase inverter, a drain electrode of the fourth PMOS tube is connected with a source electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is respectively connected with the pre-discharge circuit module and the second voltage output end, and the mirror current module is used for copying mirror current.
5. The circuit of claim 2, wherein the wide voltage memory current mirror circuit is applied in a memory, the memory further comprising a control module;
the control module is respectively connected with the pulse width generation module and the second inverter, and is used for sending a first enable signal to the pulse width generation module and sending a second enable signal to the second inverter, wherein the first enable signal is used for controlling the pulse width generation module to send a first pulse width signal, and the second enable signal is used for controlling the second inverter to send a first low level signal.
6. The circuit of claim 4, wherein the voltage stabilization module further comprises: the PMOS transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor and a first NMOS (N-channel metal oxide semiconductor) transistor;
the grid electrode of the first PMOS tube is respectively connected with the grid electrode of the second PMOS tube and the second phase inverter, the source electrode of the first PMOS tube is connected with a power supply VDD, and the drain electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube;
the source electrode of the second PMOS tube is connected with a power supply VDD, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube;
the grid electrode of the third PMOS tube is connected with the source electrode of the first NMOS tube, the source electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the third PMOS tube is respectively connected with the first voltage output end and the grid electrode of the first NMOS tube;
the grid electrode of the first NMOS tube is respectively connected with the drain electrode of the third PMOS tube and the first voltage output end, the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube, and the source electrode of the first NMOS tube is respectively connected with the grid electrode of the third PMOS tube and the second voltage output end;
the voltage stabilizing module is used for generating voltage at the first voltage output end and the second voltage output end when receiving a first low level signal.
7. The circuit of claim 1, wherein the reference current module comprises a second NMOS transistor, a gate of the second NMOS transistor is connected to a predetermined voltage, a drain of the second NMOS transistor is connected to the first voltage output terminal, and the reference current module is configured to generate a reference current.
8. The circuit of claim 1, wherein the pre-discharge circuit module comprises: the two NMOS tubes are connected in series;
or the pre-discharge circuit module is provided with more than two NMOS tubes, and the more than two NMOS tubes are connected in series or in parallel.
9. The circuit of claim 3, wherein the pulse width signal issuing module comprises:
the first NOR gate, the second NOR gate, the third NOR gate, the first resistor, the second resistor, the first NOR gate and the first capacitor;
the control module is connected with the input ends of the first NOR gate and the first NOT gate;
the output end of the first NOT gate is connected with one end of a series loop formed by the first resistor and the second resistor;
the other end of the series circuit is simultaneously connected with one end of the first capacitor and the input end of the second NOT gate, and the other end of the first capacitor is grounded;
the output end of the second NOT gate is connected with the input end of the third NOT gate;
the output end of the third not gate is connected with the input end of the first nor gate;
the output end of the first NOR gate is connected with the input end of the first inverter;
the output end of the first inverter is connected with the pre-discharge circuit module, and the output end of the first inverter generates a high level signal, which is the first pulse width signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811347356.7A CN111176366B (en) | 2018-11-13 | 2018-11-13 | Wide-voltage memory current mirror circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811347356.7A CN111176366B (en) | 2018-11-13 | 2018-11-13 | Wide-voltage memory current mirror circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111176366A CN111176366A (en) | 2020-05-19 |
| CN111176366B true CN111176366B (en) | 2022-07-08 |
Family
ID=70624361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811347356.7A Active CN111176366B (en) | 2018-11-13 | 2018-11-13 | Wide-voltage memory current mirror circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111176366B (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102081959B (en) * | 2009-11-26 | 2013-06-12 | 中国科学院微电子研究所 | Storage reading circuit and storage |
| CN102468752B (en) * | 2010-11-15 | 2015-10-28 | 华润矽威科技（上海）有限公司 | The switching power circuit that the pulse frequency modulated with output voltage compensation controls |
| US9906745B2 (en) * | 2013-12-12 | 2018-02-27 | Cista System Corp. | Column comparator system and method for comparing a ramping signal and an input signal |
| KR102282192B1 (en) * | 2015-07-23 | 2021-07-27 | 삼성전자 주식회사 | Semiconductor device with mismatch detection and recovery circuit |
| CN105632438B (en) * | 2016-01-08 | 2017-12-08 | 京东方科技集团股份有限公司 | Level deviation unit, level shift circuit and driving method, gate driving circuit |
| CN108399933B (en) * | 2017-02-07 | 2021-05-11 | 群联电子股份有限公司 | Reference voltage generating circuit, memory storage device and reference voltage generating method |
-
2018
- 2018-11-13 CN CN201811347356.7A patent/CN111176366B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111176366A (en) | 2020-05-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100202466B1 (en) | Bootstrap circuit | |
| US9866215B2 (en) | High speed low current voltage comparator | |
| JP2019530409A (en) | Device and method for stabilizing supply voltage | |
| CN108733128B (en) | Trimming code value generating circuit with ultra-low power consumption | |
| US4952863A (en) | Voltage regulator with power boost system | |
| CN110134171B (en) | Negative voltage follower circuit | |
| KR101675561B1 (en) | Power device | |
| US20160261261A1 (en) | Methods and Apparatus for a Burst Mode Charge Pump Load Switch | |
| JP4394124B2 (en) | Charge pump | |
| JP2010123837A (en) | Semiconductor integrated circuit | |
| CN111312313B (en) | Circuit for quickly switching voltage of charge pump | |
| CN111176366B (en) | Wide-voltage memory current mirror circuit | |
| CN113050749B (en) | Voltage generating circuit and semiconductor circuit including the same | |
| JP2005176296A (en) | High voltage switch circuit | |
| CN111176367B (en) | Circuit for generating stable mirror current | |
| CN112581997B (en) | Power module and memory | |
| CN110277899B (en) | Pulse width modulation controller and third state voltage generation method | |
| CN111370037A (en) | Charge pump circuit and nonvolatile memory | |
| JP4159570B2 (en) | OSCILLATOR CIRCUIT, SEMICONDUCTOR DEVICE HAVING THE OSCILLATOR CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE OSCILLATOR CIRCUIT | |
| JPH08138375A (en) | Semiconductor memory | |
| JP6530226B2 (en) | Voltage regulator, semiconductor device, and voltage generation method of voltage regulator | |
| JP5976077B2 (en) | Internal power supply voltage generation circuit, semiconductor memory device, and semiconductor device | |
| JP2005057973A (en) | Control circuit of charge pump | |
| US10326404B2 (en) | Low power time amplifier and operating method thereof | |
| TWI692200B (en) | Turning-on and off reset circuit for carrier tape chip and the working method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 230601 No.368 Qinghua Road, Hefei Economic and Technological Development Zone, Anhui Province Patentee after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 230601 No.368 Qinghua Road, Hefei Economic and Technological Development Zone, Anhui Province Patentee before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
|
| CP01 | Change in the name or title of a patent holder |