CN108399933B

CN108399933B - Reference voltage generating circuit, memory storage device and reference voltage generating method

Info

Publication number: CN108399933B
Application number: CN201710067762.7A
Authority: CN
Inventors: 易秉威
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2017-02-07
Filing date: 2017-02-07
Publication date: 2021-05-11
Anticipated expiration: 2037-02-07
Also published as: CN108399933A

Abstract

The invention provides a reference voltage generating circuit, a memory storage device and a reference voltage generating method. The reference voltage generating circuit comprises a unit switching circuit and a voltage output circuit. The unit switching circuit is used for receiving a control voltage and generating a plurality of reference voltages at a detection point in the reference voltage generating circuit. The voltage output circuit is connected to the unit switching circuit and is used for correcting a reference voltage according to the reference voltages so as to generate a specific voltage. Therefore, the influence of the process error on the reference voltage can be reduced.

Description

Reference voltage generating circuit, memory storage device and reference voltage generating method

Technical Field

The present invention relates to a voltage generating circuit, and more particularly, to a reference voltage generating circuit, a memory storage device and a reference voltage generating method.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.

In an electronic device, different electronic circuits may operate at different operating voltages. Therefore, an electronic device is usually configured with a circuit (also referred to as a reference voltage generator) that is dedicated to provide a reference voltage, and voltage signals with different voltage values can be generated based on the reference voltage. A current mirror (current mirror) is disposed inside a conventional reference voltage generator, and includes two transistors matched with each other. The gates of the two mutually matched transistors are connected to the same control voltage and the sources thereof are connected to the same current source. Thus, the reference voltage is generated at the output terminal of one of the transistors.

However, due to the process variations of the transistors themselves, there may be process errors between the transistors on both sides of the current mirror, so that the generated reference voltage may drift (variation) in response to the process errors. Conventionally, the reference voltage generators inside different chips are checked and adjusted one by one in a manual confirmation manner, which results in great labor consumption. Alternatively, a chopper (chopper) may be provided in the reference voltage generator in an attempt to eliminate the drift, but the effect is limited.

Disclosure of Invention

The invention provides a reference voltage generating circuit, a memory storage device and a reference voltage generating method, which can reduce the influence of process errors on reference voltages.

An exemplary embodiment of the present invention provides a reference voltage generating circuit, which includes a voltage supply circuit, a cell switching circuit and a voltage output circuit. The voltage supply circuit is used for providing a control voltage. The unit switching circuit is connected to the voltage supply circuit and used for receiving the control voltage and generating a plurality of reference voltages at a detection point in the reference voltage generating circuit. The voltage output circuit is connected to the unit switching circuit and is used for correcting a reference voltage according to the reference voltages so as to generate a specific voltage.

In an exemplary embodiment of the present invention, the plurality of reference voltages includes a first reference voltage and a second reference voltage, and the cell switching circuit includes a plurality of transistor cells. The operation of the cell switching circuit generating the plurality of reference voltages at the detection point inside the reference voltage generating circuit includes: generating the first reference voltage at the detection point; performing a cell switching operation on the plurality of transistor cells after the first reference voltage is generated; and generating the second reference voltage at the detecting point after the cell switching operation is performed.

In an exemplary embodiment of the present invention, the plurality of transistor units includes at least one first type transistor unit and at least one second type transistor unit. The at least one first-type transistor unit is used for receiving the control voltage and providing a feedback voltage to the input end of the voltage supply circuit. The at least one second-type transistor unit is used for receiving the control voltage and providing the reference voltages to the detection points.

In an exemplary embodiment of the invention, the voltage output circuit includes a voltage adjustment circuit for receiving the reference voltage and the plurality of reference voltages. If the reference voltage is higher than a third reference voltage in the plurality of reference voltages, the voltage adjusting circuit reduces the voltage value of the reference voltage from a first voltage value to a second voltage value. If the reference voltage is lower than the third reference voltage, the voltage adjusting circuit increases the voltage value of the reference voltage from the first voltage value to a third voltage value.

In an exemplary embodiment of the invention, the cell switching circuit is configured to generate the mapping current flowing through the at least one second type transistor cell according to the reference current flowing through the at least one first type transistor cell.

Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, a memory control circuit unit, and a reference voltage generating circuit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The reference voltage generating circuit is disposed in the connection interface unit or the memory control circuit unit. The reference voltage generating circuit is used for receiving the control voltage and generating a plurality of reference voltages at a detection point in the reference voltage generating circuit. The reference voltage generating circuit is further used for correcting the reference voltage according to the plurality of reference voltages to generate a specific voltage.

In an exemplary embodiment of the invention, the plurality of reference voltages includes a first reference voltage and a second reference voltage, and the reference voltage generating circuit includes a plurality of transistor units. The operation of the reference voltage generation circuit generating the plurality of reference voltages at the detection point inside the reference voltage generation circuit includes: generating the first reference voltage at the detection point; performing a cell switching operation on the plurality of transistor cells after the first reference voltage is generated; and generating the second reference voltage at the detecting point after the cell switching operation is performed.

In an exemplary embodiment of the invention, the reference voltage generating circuit further includes a voltage supply circuit connected to the plurality of transistor units for generating the control voltage. The plurality of transistor units comprise at least one first type transistor and at least one second type transistor unit. The at least one first-type transistor unit is used for receiving the control voltage and providing a feedback voltage to the input end of the voltage supply circuit. The at least one second-type transistor unit is used for receiving the control voltage and providing the reference voltages to the detection points.

In an exemplary embodiment of the invention, the reference voltage generating circuit includes a voltage adjusting circuit for receiving the reference voltage and the plurality of reference voltages. The voltage adjustment circuit is further configured to decrease the voltage value of the reference voltage from a first voltage value to a second voltage value if the reference voltage is higher than a third reference voltage of the plurality of reference voltages. The voltage adjustment circuit is further configured to increase the voltage value of the reference voltage from the first voltage value to a third voltage value if the reference voltage is lower than the third reference voltage.

In an exemplary embodiment of the present invention, the voltage adjusting circuit includes a first adjusting circuit, a second adjusting circuit and a feedback control circuit. The second adjusting circuit is connected to the first adjusting circuit. The feedback control circuit is connected to the second adjusting circuit. The first adjusting circuit is used for generating the reference voltage according to an initial voltage. The second adjusting circuit is used for receiving the reference voltage and the plurality of reference voltages and generating a comparison signal. The feedback control circuit is used for controlling the first adjusting circuit to adjust the reference voltage according to the comparison signal.

In an exemplary embodiment of the present invention, the first adjusting circuit includes a first operational amplifier. The reference voltage is generated at the output of the first operational amplifier.

In an exemplary embodiment of the invention, the first adjusting circuit further includes a first variable impedance unit and a second variable impedance unit. A first terminal of the first variable impedance unit is grounded, and a second terminal of the first variable impedance unit is connected to a first input terminal of the first operational amplifier. A first terminal of the second variable impedance unit is connected to the first input terminal of the first operational amplifier, and a second terminal of the second variable impedance unit is connected to the output terminal of the first operational amplifier.

In an exemplary embodiment of the invention, the operation of the feedback control circuit for controlling the first adjusting circuit according to the comparison signal includes: if the reference voltage is higher than the third reference voltage, increasing the impedance value of the first variable impedance unit from a first impedance value to a second impedance value; and if the reference voltage is lower than the third reference voltage, increasing the impedance value of the second variable impedance unit from a third impedance value to a fourth impedance value.

In an exemplary embodiment of the invention, the second adjusting circuit includes a second operational amplifier. The first input end of the second operational amplifier is used for receiving the reference voltage. The second input terminal of the second operational amplifier is used for receiving the plurality of reference voltages. The output end of the second operational amplifier is used for generating the comparison signal.

In an exemplary embodiment of the invention, the voltage adjusting circuit further includes an initial voltage generating circuit connected to the first adjusting circuit and configured to generate the initial voltage. The voltage value of the initial voltage corresponds to an initial voltage value of the reference voltage.

In an exemplary embodiment of the invention, the reference voltage generating circuit is further configured to generate the mapping current flowing through the at least one second type transistor unit according to the reference current flowing through the at least one first type transistor unit.

Another exemplary embodiment of the present invention provides a reference voltage generating method for a memory storage device, including: receiving the control voltage and generating a plurality of reference voltages at a detection point in the reference voltage generating circuit; correcting the reference voltage according to the plurality of reference voltages; and generating a specific voltage according to the modified reference voltage.

In an exemplary embodiment of the invention, the plurality of reference voltages includes a first reference voltage and a second reference voltage, and the reference voltage generating circuit includes a plurality of transistor units. The step of generating the plurality of reference voltages at the detecting point inside the reference voltage generating circuit comprises: generating the first reference voltage at the detection point; performing a cell switching operation on the plurality of transistor cells after the first reference voltage is generated; and generating the second reference voltage at the detecting point after the cell switching operation is performed.

In an exemplary embodiment of the present invention, the plurality of transistor units includes at least one first type transistor unit and at least one second type transistor unit. In addition, the step of generating the plurality of reference voltages at the detecting point inside the reference voltage generating circuit includes: generating the control voltage by a voltage supply circuit; receiving the control voltage by the at least one first-type transistor unit and providing a feedback voltage to an input end of the voltage supply circuit; and receiving the control voltage by the at least one second-class transistor unit and providing the plurality of reference voltages at the detection point.

In an exemplary embodiment of the present invention, the cell switching operation includes at least one of a first cell switching operation and a second cell switching operation. The first cell switching operation includes: changing a first transistor cell of the plurality of transistor cells from being one of the at least one first class of transistor cells to being one of the at least one second class of transistor cells. The second unit switching operation includes: changing a second transistor cell of the plurality of transistor cells from being one of the at least one second type of transistor cell to being one of the at least one first type of transistor cell.

In an exemplary embodiment of the present invention, the total number of the at least one first type transistor unit is equal to the total number of the at least one second type transistor unit.

In an exemplary embodiment of the present invention, the step of generating the reference voltage according to the plurality of reference voltages comprises: receiving the reference voltage and the plurality of reference voltages; if the reference voltage is higher than a third reference voltage in the plurality of reference voltages, reducing the voltage value of the reference voltage from a first voltage value to a second voltage value; and if the reference voltage is lower than the third reference voltage, increasing the voltage value of the reference voltage from the first voltage value to a third voltage value.

In an exemplary embodiment of the invention, the plurality of reference voltages are sequentially generated based on a plurality of clock edges of the clock signal.

In an exemplary embodiment of the present invention, the cell switching operation is performed based on a clock edge of a clock signal.

In an exemplary embodiment of the invention, the reference voltage generating method further includes: generating a mapping current flowing through the at least one second-type transistor unit according to the reference current flowing through the at least one first-type transistor unit.

Based on the above, after receiving the control voltage, the reference voltage generating circuit generates a plurality of reference voltages at one detecting point therein. Then, based on these reference voltages, the reference voltage generating circuit generates and corrects a reference voltage. This reference voltage can then be used to generate a specific voltage. Compared with the prior art that the output voltage of the transistor at one side of the current mirror is directly used as the reference voltage, the invention can reduce the influence of the process error of the transistors at two sides of the current mirror on the drift of the reference voltage and the like.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a reference voltage generating circuit according to an exemplary embodiment of the invention.

FIG. 2 is a schematic diagram of a reference voltage generating circuit according to another exemplary embodiment of the invention.

Fig. 3A to 3D are schematic diagrams illustrating a cell switching operation according to an exemplary embodiment of the present invention.

Fig. 4 is a schematic diagram of a voltage regulation circuit according to an exemplary embodiment of the present invention.

Fig. 5 is a schematic diagram of a voltage regulation circuit according to another exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating triggering a cell switching operation with a clock signal according to an exemplary embodiment of the invention.

FIG. 7 is a diagram illustrating a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the invention.

FIG. 8 is a diagram illustrating a host system, a memory storage device and an I/O device according to another exemplary embodiment of the invention.

FIG. 9 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.

FIG. 10 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.

FIG. 11 is a diagram illustrating a connection interface unit according to an exemplary embodiment of the present invention.

FIG. 12 is a flowchart illustrating a method for generating reference voltages according to an exemplary embodiment of the invention.

Detailed Description

The present invention will be described in more detail with reference to exemplary embodiments, but the present invention is not limited to the exemplary embodiments. Also, the exemplary embodiments are also susceptible to appropriate combinations. The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples to a second device, that connection should be interpreted as either being a direct connection, or a indirect connection via other devices and some means of connection. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.

Referring to fig. 1, a reference voltage generating circuit 10 includes a voltage supply circuit 11, a cell switching circuit 12 and a voltage output circuit 13. The cell switching circuit 12 is connected to the voltage supply circuit 11 and the voltage output circuit 13. The voltage supply circuit 11 is used for generating a control voltage V _ c. The cell switching circuit 12 is used for receiving the control voltage V _ c and generating a plurality of reference voltages V _ base at a detection point D inside the reference voltage generating circuit 10. For example, the detection point D is connected to the output terminal of the cell switching circuit 12.

In the exemplary embodiment, the cell switching circuit 12 includes a plurality of transistor cells 121(1) -121 (n). Wherein n is a positive integer greater than 1. For example, in one exemplary embodiment, n is 128. In another exemplary embodiment, the value of n may also be larger or smaller as long as it is a multiple of 2. The control terminals of the transistor units 121(1) -121 (n) are all connected to the voltage supply circuit 11 and are used for receiving the control voltage V _ c. The input terminals of the transistor units 121(1) -121 (n) are connected to a current source or a voltage source. The output terminals of some of the transistor units 121(1) - (121 (n)) are connected to the detecting point D (i.e., the output terminal of the unit switching circuit 12). In addition, a transistor cell may include one or more transistor elements.

The cell switching circuit 12 performs a cell switching operation on the transistor cells 121(1) to 121 (n). For example, in the cell switching operation, at least one of the transistor cells 121(1) - (121 (n) that was not connected to the detecting point D may be switched to be connected to the detecting point D, and at least one of the transistor cells 121(1) - (121 (n) that was connected to the detecting point D may be switched to be unconnected to the detecting point D. The reference voltage V _ base at the detection point D is changed corresponding to the cell switching operation performed. For example, assume that the present cell switching circuit 12 generates a reference voltage (also referred to as a first reference voltage) having one voltage value at the detection point D. After performing the cell switching operation, the cell switching circuit 12 generates a reference voltage (also referred to as a second reference voltage) having another voltage value at the detection point D.

In an exemplary embodiment, the reference voltages V _ base are sequentially generated based on clock edges of a clock signal. The clock edges may refer to a plurality of continuous rising edges, a plurality of continuous falling edges, a plurality of discontinuous rising edges or a plurality of discontinuous falling edges of the clock signal. For example, the cell switching operation is performed based on a clock edge of the clock signal, such that the voltage at the detection point D is changed from a first reference voltage to a second reference voltage. The cell switching operation is repeatedly performed corresponding to the plurality of clock edges, thereby generating the plurality of reference voltages V _ base.

The voltage output circuit 13 is used for sequentially receiving the plurality of reference voltages V _ base at the detecting point D and generating the reference voltage V _ ref according to the plurality of reference voltages V _ base. It should be noted that, in the operation of sequentially generating the plurality of reference voltages V _ base, the voltage value of the reference voltage V _ ref is modified. For example, the voltage value of the corrected reference voltage V _ ref is closer to an average voltage value of the plurality of reference voltages V _ base. In an exemplary embodiment, the reference voltage V _ ref finally generated according to the plurality of reference voltages V _ base is in a stable state. For example, the voltage value of the reference voltage V _ ref in the steady state may be equal to (or relatively close to) the average voltage value of the plurality of reference voltages V _ base. In an exemplary embodiment, the voltage value of the reference voltage V _ ref in the steady state can also be regarded as an average voltage value of the plurality of reference voltages V _ base. In an exemplary embodiment, the total number of the reference voltages V _ base used to generate the reference voltage V _ ref in the steady state is n/2, and n/2 is also a positive integer. For example, assuming that the total number of the transistor units 121(1) -121 (n) is 128, the reference voltage V _ ref in the steady state is generated after 64 cell switching operations are performed.

Referring to fig. 2, in the present exemplary embodiment, the cell switching circuit 12 includes transistor cells (also referred to as first type transistor cells) 221(1) -221 (m) and transistor cells (also referred to as second type transistor cells) 222(1) -222 (m). m is a positive integer greater than 1. For example, m is equal to n/2. The control terminals of the transistor units 221(1) -221 (m) and 222(1) -222 (m) are connected to the voltage supply circuit 11 and are used for receiving the control voltage V _ c. The output terminals of the transistor units 221(1) -221 (m) are all connected to the voltage supply circuit 11 and are used for providing the feedback voltage V _ f to the input terminal of the voltage supply circuit 11. The voltage supply circuit 11 receives the feedback voltage V _ f and outputs a control voltage V _ c accordingly. The output terminals of the transistor units 222(1) -222 (m) are all connected to the detecting point D and are used for providing the reference voltage V _ base at the detecting point D. In addition, an impedance unit RD is connected in series between the detecting point D and the ground level, and includes at least one element for providing an impedance value (e.g., a resistance value or a reactance value), such as a resistor element.

In an exemplary embodiment, the transistor units 221(1) -221 (m) can be regarded as a transistor group located on one side of a current mirror circuit, and the transistor units 222(1) -222 (m) can be regarded as a transistor group located on the other side of the same current mirror circuit. For example, the input terminals of the transistor units 221(1) - (221 (m) are connected to a current source, and the input terminals of the transistor units 222(1) - (222 (m) are connected to a voltage source. Through current mirror mapping, the cell switching circuit 12 can generate currents (also referred to as mapping currents) flowing through the transistor cells 222(1) -222 (m) according to the currents (also referred to as reference currents) flowing through the transistor cells 221(1) -221 (m).

In an exemplary embodiment, one of the transistor cells is dynamically changeable, and the other of the transistor cells 221(1) -221 (m) or 222(1) -222 (m) is dynamically changeable. For example, in a cell switching operation, a certain transistor cell (also referred to as a first transistor cell) is changed from being one of the first-type transistor cells to being one of the second-type transistor cells, and a certain transistor cell (also referred to as a second transistor cell) is changed from being one of the second-type transistor cells to being one of the first-type transistor cells. In an example embodiment, changing the operation of the first transistor cell from being one of the first kind of transistor cells to being one of the second kind of transistor cells is also referred to as a first cell switching operation, and changing the operation of the second transistor cell from being one of the second kind of transistor cells to being one of the first kind of transistor cells is also referred to as a second cell switching operation.

In an exemplary embodiment, the type of a transistor cell can be changed by changing the connection object of the output terminal of the transistor cell. For example, when the output terminal of a certain transistor unit is electrically connected to the voltage supply circuit 11, the transistor unit can be regarded as belonging to the transistor units 221(1) -221 (m) (i.e., the first type transistor unit). If the output terminal of the transistor unit is switched to be electrically connected to the detection point D (or the voltage output circuit 13), the transistor unit can be regarded as belonging to the transistor units 222(1) to 222(m) (i.e., the second type transistor unit). In an exemplary embodiment, changing the connection of the output terminal of a transistor unit can be regarded as changing the circuit loop to which the transistor unit belongs. For example, if the circuit loop to which a transistor unit belongs includes the circuit loop for providing the output voltage of the transistor unit to the voltage supply circuit 11, the transistor unit may be considered to belong to the transistor units 221(1) to 221 (m). If the transistor unit is switched to belong to another circuit loop, so that the voltage at the output terminal of the transistor unit is no longer provided to the voltage supply circuit 11, the transistor unit can be regarded as belonging to the transistor units 222(1) -222 (m).

Referring to fig. 2 and fig. 3A, in the present exemplary embodiment, the cell switching circuit 12 includes transistor cells 321(1) -321 (n) and a switch module 300. The input terminals of the switch module 300 are connected to the transistor units 321(1) -321 (n). The first output terminal of the switch module 300 is connected to the voltage supply circuit 11 and is used for providing the feedback voltage V _ f at the first output terminal. The second output terminal of the switch module 300 is connected to the detecting point D and is used for providing the reference voltage V _ base at the second output terminal. In the present exemplary embodiment, the cell switching operation refers to changing a state of at least one switching cell in the switching module 300.

In the exemplary embodiment, the switch module 300 includes switch units 301(1) -301 (m), 311(1) -311 (m), 302(1) -302 (m), and 312(1) -312 (m). The switching units 301(1) to 301(m) are connected in series between the transistor units 321(1) to 321(m) and the voltage supply circuit 11, respectively. The switch units 311(1) to 311(m) are connected in series between the transistor units 321(1) to 321(m) and the detection point D, respectively. The switch units 302(1) to 302(m) are connected in series between the transistor units 321(m +1) to 321(n) and the detection point D, respectively. The switch units 312(1) to 312(m) are connected in series between the transistor units 321(m +1) to 321(n) and the voltage supply circuit 11, respectively. By adjusting the state of one of the switch units in the switch module 300, it can be determined whether one of the transistor units 321(1) to 321(n) belongs to the first-type transistor unit or the second-type transistor unit.

In the example embodiment of FIG. 3A, each of the switch units 301(1) -301 (m) and 302(1) -302 (m) is in an ON state, and each of the switch units 311(1) -311 (m) and 312(1) -312 (m) is in an OFF state. At this time, the transistor cells 321(1) to 321(m) connected to the voltage supply circuit 11 belong to the first type transistor cells, and the transistor cells 321(m +1) to 321(n) connected to the detection point D belong to the second type transistor cells.

Referring to fig. 2 and fig. 3B, corresponding to a switching operation of one of the units, the states of the switch units 301(1) and 302(1) are switched from the on state to the off state, and the states of the switch units 311(1) and 312(1) are switched from the off state to the on state. Therefore, the transistor unit 321(1) is switched to belong to the second type transistor unit, and the transistor unit 321(m +1) is switched to belong to the first type transistor unit. At this time, the transistor units 321(2) to 321(m +1) connected to the voltage supply circuit 11 belong to the first type transistor unit, and the transistor units 321(1) and 321(m +2) to 321(n) connected to the detection point D belong to the second type transistor unit.

Referring to fig. 3C, corresponding to another unit switching operation, the states of the switch units 301(2) and 302(2) are switched from the on state to the off state, and the states of the switch units 311(2) and 312(2) are switched from the off state to the on state. Therefore, the transistor unit 321(2) is switched to belong to the second type transistor unit, and the transistor unit 321(m +2) is switched to belong to the first type transistor unit. At this time, the transistor units 321(3) to 321(m +2) connected to the voltage supply circuit 11 belong to the first type of transistor units, and the transistor units 321(1), 321(2) and 321(m +3) to 321(n) connected to the detection point D belong to the second type of transistor units. By analogy, in the ith cell switching operation, the states of the switch cells 301(i), 302(i), 311(i) and 312(i) are switched, so that the transistor cell (i) is switched to the second type transistor cell and the transistor cell (m + i) is switched to the first type transistor cell. Wherein i is a positive integer and 0< i < (m + 1).

Referring to fig. 3D, after the m unit switching operations, each of the switch units 301(1) -301 (m) and 302(1) -302 (m) is in the off state, and each of the switch units 311(1) -311 (m) and 312(1) -312 (m) is in the on state. At this time, the transistor cells 321(m +1) to 321(n) connected to the voltage supply circuit 11 belong to the first type transistor cells, and the transistor cells 321(1) to 321(m) connected to the detection point D belong to the second type transistor cells.

In an exemplary embodiment, by exchanging the transistor cells of the first type transistor cell and the second type transistor cell, the transistor cells constituting the second type transistor cell are changed, so that the voltage value of the reference voltage V _ base at the detection point D is changed accordingly. For example, the voltage value of the reference voltage V _ base at the detection point D may be changed m times corresponding to the cell switching operation performed m times. In addition, by exchanging the transistor units in the first type transistor unit and the second type transistor unit, the reference voltage drift caused by process errors of the transistor elements on two sides in the current mirror circuit can be improved. In other words, in an exemplary embodiment, the cell switching operation is used to overcome voltage drift due to process errors of the transistor cells.

It is noted that, in the above exemplary embodiments of fig. 3A to 3D, the number of the first transistor units and the number of the second transistor units are both one. However, in another exemplary embodiment, the number of the first transistor unit and/or the second transistor unit may be plural. For example, in one cell switching operation, a plurality of transistor cells may be switched from belonging to a first kind of transistor cells to belonging to a second kind of transistor cells and a plurality of transistor cells may be switched from belonging to the second kind of transistor cells to belonging to the first kind of transistor cells. In addition, the circuit configuration of fig. 3A to 3D is only one possible circuit configuration for performing the cell switching operation. In another exemplary embodiment, the cell switching circuit 12 may also have other types of circuit structures as long as the cell switching operation can be performed.

In an exemplary embodiment, the operation of swapping the transistor cells of the first type transistor cell and the second type transistor cell (i.e., cell switching operation) is performed according to a switching rule. This switching rule is used to specify how the cell switching operation is to be performed. For example, according to the switching rule, the transistor cells to be switched (i.e., the first transistor cell and the second transistor cell) in each cell switching operation may be randomly selected or selected according to a predetermined sequence. Further, in an example embodiment, after the cell switching operation is performed a plurality of times (e.g., m times), a plurality of transistor cells originally belonging to the first type transistor cell are completely switched to belong to the second type transistor cell, and a plurality of transistor cells originally belonging to the second type transistor cell are completely switched to belong to the first type transistor cell.

Referring back to fig. 2, the voltage output circuit 13 includes a voltage adjusting circuit 23. The voltage adjustment circuit 23 is connected to the voltage supply circuit 11 and the detecting point D. The voltage adjustment circuit 23 is used for receiving the control voltage V _ c 'from the voltage supply circuit 11, wherein the voltage value of the control voltage V _ c' may be equal to or not equal to the voltage value of the control voltage V _ c. The voltage adjusting circuit 23 is further configured to continuously receive the reference voltage V _ ref and the plurality of reference voltages V _ base and continuously adjust (i.e., correct) the reference voltage V _ ref. For example, if the voltage value of the current reference voltage V _ ref is higher than the voltage value of the current reference voltage (also referred to as a third reference voltage) V _ base, the voltage adjustment circuit 23 decreases the voltage value of the reference voltage V _ ref from the current voltage value (also referred to as a first voltage value) to another voltage value (also referred to as a second voltage value). Conversely, if the voltage value of the current reference voltage V _ ref is lower than the voltage value of the current reference voltage V _ base, the voltage adjustment circuit 23 increases the voltage value of the reference voltage V _ ref from the current voltage value to another voltage value (also referred to as a third voltage value). In an exemplary embodiment, the operation of adjusting the voltage value of the reference voltage V _ ref is also referred to as a reference voltage adjusting operation. In an exemplary embodiment, a reference voltage adjustment operation is performed in response to performing a cell switching operation. In addition, in an exemplary embodiment, the output reference voltage V _ ref is in the stable state after m times of reference voltage adjustment operations.

Referring to fig. 4, in the present exemplary embodiment, the voltage adjusting circuit 23 includes an initial voltage generating circuit 41, an adjusting circuit (also referred to as a first adjusting circuit) 42, an adjusting circuit (also referred to as a second adjusting circuit) 43, and a feedback control circuit 44. The adjustment circuit 42 is connected to the initial voltage generation circuit 41, the adjustment circuit 43, and the feedback control circuit 44. The adjusting circuit 43 is further connected to the feedback control circuit 44.

The initial voltage generating circuit 41 is configured to receive the control voltage V _ c' from the voltage supply circuit 11 and generate an initial voltage V _ ini. The initial voltage V _ ini corresponds to an initial voltage value of the reference voltage V _ ref. The adjusting circuit 42 is used for generating a reference voltage V _ ref according to the initial voltage V _ ini. The adjusting circuit 43 is used for receiving the reference voltage V _ ref and the reference voltage V _ base and generating the comparison signal CA. The feedback control circuit 44 is used for controlling the adjusting circuit 42 to adjust the reference voltage V _ ref according to the comparison signal CA. For example, the adjusting circuit 42 is controlled by the feedback control circuit 44 to increase or decrease the voltage value of the reference voltage V _ ref. The details of the voltage regulator circuit 23 in an exemplary embodiment are described in more detail below.

Referring to fig. 5, in the present exemplary embodiment, the initial voltage generating circuit 41 includes a transistor unit 511, an operational amplifier 512 and a resistance unit RD. The impedance unit RD provides the same impedance value as the impedance unit RD in fig. 2 provides. The control terminal of the transistor unit 511 is connected to the voltage supply circuit 11 and is configured to receive the control voltage V _ c'. The input terminal of the transistor unit 511 is connected to a voltage source. An output terminal of the transistor unit 511 is connected to an input terminal of the operational amplifier 512. The resistance unit RD is connected in series between the transistor unit 511 and the ground level. Further, the output terminal of the operational amplifier 512 is connected to the input terminal of the adjusting circuit 42. Specifically, the transistor unit 511 provides a voltage at the detecting point I, and the voltage value of the voltage approaches the voltage value of the reference voltage V _ base at the detecting point D. The operational amplifier 512 generates an initial voltage V _ ini according to the voltage at the detecting point I.

In the present exemplary embodiment, the adjusting circuit 42 includes an operational amplifier (also referred to as a first operational amplifier) 521, an impedance unit R1, an impedance unit R1', an impedance unit (also referred to as a first variable impedance unit) R2, and an impedance unit (also referred to as a second variable impedance unit) R3. The resistance unit R1 provides the same resistance value as the resistance unit R1'. The resistance values provided by the resistance units R2 and R3 are dynamically adjustable. Specifically, the first terminal of the impedance unit R2 is connected to ground, the second terminal of the impedance unit R2 is connected to the first input terminal of the operational amplifier 521, the first terminal of the impedance unit R3 is connected to the first input terminal of the operational amplifier 521, and the second terminal of the impedance unit R3 is connected to the output terminal of the operational amplifier 521. In addition, the reference voltage V _ ref is generated at the output terminal of the operational amplifier 521.

In the present exemplary embodiment, the adjusting circuit 43 includes an operational amplifier 531 and a sampling circuit 532. The first input terminal of the operational amplifier 531 receives a reference voltage V _ ref, and the second input terminal of the operational amplifier 531 receives a reference voltage V _ base. The sampling circuit 532 is connected to the output terminal of the operational amplifier 531 and is used for sampling the output of the operational amplifier 531 based on the clock signal CLK. Based on the sampling result, the sampling circuit 532 outputs the comparison signal CA. In addition, in the present exemplary embodiment, the sampling circuit 532 includes a D-type flip-flop.

In the present exemplary embodiment, the feedback control circuit 44 includes a register 541. The feedback control circuit 44 updates the impedance parameter recorded in the register 541 according to the comparison signal CA. The feedback control circuit 44 adjusts the impedance value of the impedance unit R2 and/or the impedance unit R3 according to the impedance parameter. According to the adjusted impedance value, the voltage value of the reference voltage V _ ref outputted by the adjusting circuit 42 will change accordingly.

Referring to fig. 6, in the above exemplary embodiment, the cell switching operation and the reference voltage adjusting operation are triggered by the clock edge of the clock signal CLK. For example, in response to 5 consecutive rising edges of the clock signal CLK, rule 1-rule 5 are sequentially used to disturb (or swap) the transistor cells in the cell switching circuit 12 and 5 reference voltages V _ base _ 1-V _ base _5 with different voltage values are sequentially generated at the detection point D. In response to the reference voltages V _ base _ 1-V _ base _5, the reference voltage V _ ref is continuously adjusted (i.e., corrected) such that the voltage value of the reference voltage V _ ref gradually approaches an average voltage value of the reference voltages V _ base _ 1-V _ base _5 (or more reference voltages).

In the exemplary embodiment of fig. 4 (or fig. 5) and fig. 6, an initial voltage value of the reference voltage V _ ref is set corresponding to the voltage value of the initial voltage V _ ini. After the ith cell switching operation is performed corresponding to rule i, the reference voltage V _ base _ i is generated. In the ith reference voltage adjusting operation, the adjusting circuit 43 compares the reference voltage V _ base _ i with the current reference voltage V _ ref. If the voltage value of the current reference voltage V _ ref is higher than the voltage value of the reference voltage V _ base _ i, the feedback control circuit 44 controls the adjustment circuit 42 to decrease the voltage value of the reference voltage V _ ref. For example, the feedback control circuit 44 may increase the impedance value of the impedance unit R2 from one impedance value (also referred to as a first impedance value) to another impedance value (also referred to as a second impedance value). The voltage value of the reference voltage V _ ref decreases corresponding to the increase of the resistance value of the resistance unit R2. Conversely, if the current reference voltage V _ ref is lower than the reference voltage V _ base _ i, the feedback control circuit 44 controls the adjustment circuit 42 to increase the voltage of the reference voltage V _ ref. For example, the feedback control circuit 44 may increase the impedance value of the impedance unit R3 from one impedance value (also referred to as a third impedance value) to another impedance value (also referred to as a fourth impedance value). The voltage value of the reference voltage V _ ref rises corresponding to the increase of the resistance value of the resistance unit R3.

It is noted that, in an exemplary embodiment, in order to stably adjust the reference voltage V _ ref, the voltage value of the reference voltage V _ ref in one reference voltage adjusting operation may rise by an amount equal to the voltage value of the reference voltage V _ ref in another reference voltage adjusting operation. Alternatively, from another perspective, the difference between the first impedance value and the second impedance value is equal to the difference between the third impedance value and the fourth impedance value. In addition, after the reference voltage V _ ref is in the stable state, the reference voltage V _ ref can be used to generate a specific voltage having a specific voltage value. For example, the specific voltage value may be 5 volts (V) or higher or lower.

It should be noted that, although fig. 2 to fig. 5 show possible circuit layouts of the reference voltage generating circuit in some example embodiments, in other example embodiments not mentioned, some electronic components in the reference voltage generating circuit may be replaced by other types of electronic components, the connection relationship of some electronic components in the reference voltage generating circuit may be changed, and/or more electronic components may be added to the reference voltage generating circuit as long as the corresponding functions of the reference voltage generating circuit are satisfied.

In an example embodiment, the reference voltage generating circuit (e.g., the reference voltage generating circuit 10 of fig. 1) is also referred to as a bandgap reference (bandgap reference) circuit. In an exemplary embodiment, the reference voltage generating circuit can be applied to various electronic devices to provide a reference voltage required for the operation of the electronic devices. Alternatively, in another exemplary embodiment, the reference voltage generating circuit is applied to a memory storage device to provide a reference voltage required for the operation of the memory storage device.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 7 is a diagram illustrating a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 8 is a diagram illustrating a host system, a memory storage device and an I/O device according to another exemplary embodiment of the invention.

Referring to fig. 7 and 8, the host system 711 generally includes a processor 7111, a Random Access Memory (RAM) 7112, a Read Only Memory (ROM) 7113 and a data transmission interface 7114. The processor 7111, the random access memory 7112, the read only memory 7113 and the data transmission interface 7114 are all coupled to a system bus (system bus) 7110.

In the exemplary embodiment, host system 711 is coupled to memory storage device 710 via data transfer interface 7114. For example, the host system 711 can store data to the memory storage device 710 or read data from the memory storage device 710 via the data transmission interface 7114. Further, the host system 711 is connected to the I/O device 712 via a system bus 7110. For example, host system 711 may transmit output signals to I/O device 712 or receive input signals from I/O device 712 via system bus 7110.

In the present exemplary embodiment, the processor 7111, the ram 7112, the rom 7113 and the data transmission interface 7114 may be disposed on the motherboard 820 of the host system 711. The number of the data transmission interfaces 7114 may be one or more. The motherboard 820 can be connected to the memory storage device 710 via a wired or wireless connection via the data transmission interface 7114. The memory storage device 710 can be, for example, a flash Drive 801, a memory card 802, a Solid State Drive (SSD) 803, or a wireless memory storage device 804. The wireless memory storage device 804 can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) based memory storage device based on various wireless Communication technologies. In addition, the motherboard 820 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 805, a network interface card 806, a wireless transmission device 807, a keyboard 808, a screen 809, and a speaker 810 through a System bus 7110. For example, in an exemplary embodiment, the motherboard 820 can access the wireless memory storage device 804 via the wireless transmission device 807.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 9 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 9, in another exemplary embodiment, the host system 931 may also be a Digital camera, a video camera, a communication device, a music player, a video player, a tablet computer, etc., and the memory storage device 930 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 932, a Compact Flash (CF) card 933, or an embedded storage device 934 used therein. The embedded storage device 934 includes embedded Multi Media Card (eMMC) 941 and/or embedded Multi Chip Package (eMCP) storage 942, which connect the memory module directly to the embedded storage device on the substrate of the host system.

Referring to fig. 10, the memory storage device 710 includes a connection interface unit 1002, a memory control circuit unit 1004, and a rewritable nonvolatile memory module 1006.

The connection interface unit 1002 is used to connect the memory storage device 710 to the host system 711. In the exemplary embodiment, connection interface unit 1002 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 1002 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed Specification-I (UHS-I) interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (Flash) interface standard, the CP interface standard, the CF interface standard, the Electronic drive interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 1002 may be packaged in one chip with the memory control circuit unit 1004, or the connection interface unit 1002 may be disposed outside a chip including the memory control circuit unit 1004.

The memory control circuit unit 1004 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing of data in the rewritable nonvolatile memory module 1006 according to the commands of the host system 711.

The rewritable nonvolatile memory module 1006 is connected to the memory control circuit unit 1004 and is used for storing data written by the host system 711. The rewritable nonvolatile memory module 1006 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 1006 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, a charge trapping layer is formed between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 1006 has a plurality of storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 1006 form a plurality of physical programming units, and the physical programming units form a plurality of physical erasing units. Specifically, the memory cells on the same word line constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program unit. Generally, in the MLC NAND flash memory, the writing speed of the lower physical programming unit is faster than that of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming cell is the smallest cell to which data is written. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region is used for storing system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit region includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other exemplary embodiments, the data bit region may include 8, 16 or more or less physical fans, and the size of each physical fan may be larger or smaller. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physical erase cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).

In an exemplary embodiment, the reference voltage generating circuit (e.g., the reference voltage generating circuit 10 of fig. 1) is disposed at the connection interface unit 1002 or the memory control circuit unit 1004 to provide a reference voltage required for the operation of the connection interface unit 1002 and/or the memory control circuit unit 1004. In addition, in another exemplary embodiment, the reference voltage generating circuit can also be disposed in the rewritable nonvolatile memory module 1006 to provide a reference voltage required for the operation of the rewritable nonvolatile memory module 1006.

Referring to fig. 11, in an exemplary embodiment, the connection interface unit 1002 includes a reference voltage generating circuit 1101 and a step-up/step-down circuit 1102. The reference voltage generating circuit 1101 is the same as or similar to the reference voltage generating circuit 10 in fig. 1. After the reference voltage generation circuit 1101 generates the reference voltage V _ ref in a stable state, the up/down circuit 1102 may increase or decrease the voltage value of the reference voltage V _ ref to output the specific voltage V _ spec having a specific voltage value. For example, the buck/boost circuit 1102 may include at least one voltage divider (voltage divider) circuit. The specific voltage V _ spec can be provided to one or more electronic components in the memory storage device 710.

Referring to fig. 12, in step S1201, the control voltage is received and a plurality of reference voltages are generated at a detection point inside the reference voltage generating circuit. In step S1202, the reference voltage is corrected according to the plurality of reference voltages. In step S1203, a specific voltage is generated according to the corrected reference voltage.

However, the steps in fig. 12 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 12 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 12 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.

In summary, after receiving the control voltage, the reference voltage generating circuit generates a plurality of reference voltages at a detecting point therein based on a switching rule. Then, the reference voltage generating circuit continuously corrects a reference voltage according to the reference voltages. The reference voltage can then be used to generate a specific voltage having a specific voltage value. Compared with the prior art that the output voltage of the transistor on one side of the current mirror is directly used as the reference voltage, the invention can reduce the influence of the process error of the transistors on the two sides of the current mirror on the drift of the reference voltage and the like.

Claims

1. A reference voltage generating circuit, comprising:

a voltage supply circuit for providing a control voltage;

a cell switching circuit connected to the voltage supply circuit and configured to receive the control voltage and generate a plurality of reference voltages at a detection point inside the reference voltage generation circuit; and

a voltage output circuit connected to the cell switching circuit and used for modifying the reference voltage according to a voltage variation of the plurality of reference voltages to generate a specific voltage, the voltage output circuit comprising:

a voltage adjustment circuit for receiving the reference voltage and the plurality of reference voltages,

if the reference voltage is higher than a third reference voltage of the plurality of reference voltages, the voltage adjusting circuit reduces the voltage value of the reference voltage from a first voltage value to a second voltage value,

if the reference voltage is lower than the third reference voltage, the voltage adjusting circuit increases the voltage value of the reference voltage from the first voltage value to a third voltage value.

2. The reference voltage generating circuit of claim 1, wherein the plurality of reference voltages comprises a first reference voltage and a second reference voltage, and the cell switching circuit comprises a plurality of transistor cells,

the operation of the cell switching circuit generating the plurality of reference voltages at the detection point inside the reference voltage generating circuit includes:

generating the first reference voltage at the detection point;

performing a cell switching operation on the plurality of transistor cells after generating the first reference voltage; and

after the cell switching operation is performed, the second reference voltage is generated at the detection point.

3. The reference voltage generating circuit of claim 2, wherein the plurality of transistor units comprises at least one first type transistor unit and at least one second type transistor unit, the at least one first type transistor unit is configured to receive the control voltage and provide a feedback voltage to the input terminal of the voltage supply circuit,

the at least one second-type transistor unit is used for receiving the control voltage and providing the reference voltages to the detection points.

4. The reference voltage generating circuit of claim 3, wherein the cell switching operation comprises at least one of a first cell switching operation and a second cell switching operation,

the first cell switching operation includes:

changing a first transistor cell of the plurality of transistor cells from being one of the at least one first class of transistor cells to being one of the at least one second class of transistor cells,

the second unit switching operation includes:

changing a second transistor cell of the plurality of transistor cells from being one of the at least one second type of transistor cell to being one of the at least one first type of transistor cell.

5. The reference voltage generating circuit of claim 3, wherein the total number of the at least one first type transistor cells is equal to the total number of the at least one second type transistor cells.

6. The reference voltage generating circuit of claim 1, wherein the voltage regulating circuit comprises:

a first adjusting circuit;

a second adjusting circuit connected to the first adjusting circuit; and

a feedback control circuit connected to the second adjusting circuit,

the first adjusting circuit is used for generating the reference voltage according to an initial voltage,

the second adjusting circuit is used for receiving the reference voltage and the plurality of reference voltages and generating a comparison signal,

the feedback control circuit is used for controlling the first adjusting circuit to adjust the reference voltage according to the comparison signal.

7. The reference voltage generating circuit of claim 6, wherein the first adjusting circuit comprises a first operational amplifier,

the reference voltage is generated at the output of the first operational amplifier.

8. The reference voltage generating circuit of claim 7, wherein the first adjusting circuit further comprises a first variable impedance unit and a second variable impedance unit,

a first terminal of the first variable impedance unit is grounded, and a second terminal of the first variable impedance unit is connected to a first input terminal of the first operational amplifier,

a first terminal of the second variable impedance unit is connected to the first input terminal of the first operational amplifier, and a second terminal of the second variable impedance unit is connected to the output terminal of the first operational amplifier.

9. The reference voltage generating circuit of claim 8, wherein the feedback control circuit controlling the operation of the first adjusting circuit according to the comparison signal comprises:

if the reference voltage is higher than the third reference voltage, increasing the impedance value of the first variable impedance unit from a first impedance value to a second impedance value; and

and if the reference voltage is lower than the third reference voltage, increasing the impedance value of the second variable impedance unit from a third impedance value to a fourth impedance value.

10. The reference voltage generating circuit of claim 6, wherein the second adjusting circuit comprises a second operational amplifier,

the first input terminal of the second operational amplifier is used for receiving the reference voltage,

a second input of the second operational amplifier is configured to receive the plurality of reference voltages,

the output end of the second operational amplifier is used for generating the comparison signal.

11. The reference voltage generating circuit of claim 6, wherein the voltage adjusting circuit further comprises an initial voltage generating circuit connected to the first adjusting circuit and configured to generate the initial voltage,

the voltage value of the initial voltage corresponds to an initial voltage value of the reference voltage.

12. The reference voltage generation circuit of claim 1, wherein the plurality of reference voltages are sequentially generated based on a plurality of clock edges of a clock signal.

13. The reference voltage generation circuit of claim 2, wherein the cell switching operation is performed based on a clock edge of a clock signal.

14. The reference voltage generating circuit of claim 3, wherein the cell switching circuit is configured to generate the mapping current flowing through the at least one second type transistor cell according to the reference current flowing through the at least one first type transistor cell.

15. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module;

the memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module; and

a reference voltage generating circuit disposed in the connection interface unit or the memory control circuit unit,

the reference voltage generating circuit is used for receiving a control voltage and generating a plurality of reference voltages at a detecting point in the reference voltage generating circuit,

the reference voltage generating circuit is further used for correcting the reference voltage according to a voltage variation of the plurality of reference voltages to generate a specific voltage,

the reference voltage generating circuit further includes a voltage supply circuit connected to the plurality of transistor cells and configured to generate the control voltage,

the plurality of transistor units comprise at least one first type transistor unit and at least one second type transistor unit,

the at least one first-type transistor unit is used for receiving the control voltage and providing a feedback voltage to the input end of the voltage supply circuit,

16. The memory storage device of claim 15, wherein the plurality of reference voltages comprises a first reference voltage and a second reference voltage, and the reference voltage generation circuit comprises a plurality of transistor cells,

the operation of the reference voltage generation circuit generating the plurality of reference voltages at the detection point inside the reference voltage generation circuit includes:

generating the first reference voltage at the detection point;

17. The memory storage device of claim 16, wherein the cell switching operation comprises at least one of a first cell switching operation and a second cell switching operation,

the first cell switching operation includes:

the second unit switching operation includes:

18. The memory storage device of claim 15, wherein a total number of the at least one first type transistor cells is equal to a total number of the at least one second type transistor cells.

19. The memory storage device of claim 15, wherein the reference voltage generation circuit comprises:

the voltage adjustment circuit is further configured to decrease the voltage value of the reference voltage from a first voltage value to a second voltage value if the reference voltage is higher than a third reference voltage of the plurality of reference voltages,

the voltage adjustment circuit is further configured to increase the voltage value of the reference voltage from the first voltage value to a third voltage value if the reference voltage is lower than the third reference voltage.

20. The memory storage device of claim 19, wherein the voltage regulation circuit comprises:

a first adjusting circuit;

a second adjusting circuit connected to the first adjusting circuit; and

a feedback control circuit connected to the second adjusting circuit,

21. The memory storage device of claim 20, wherein the first adjustment circuit comprises a first operational amplifier,

22. The memory storage device of claim 21, wherein the first adjustment circuit further comprises a first variable impedance unit and a second variable impedance unit,

23. The memory storage device of claim 22, wherein the feedback control circuit controlling the operation of the first adjustment circuit according to the comparison signal comprises:

24. The memory storage device of claim 20, wherein the second adjustment circuit comprises a second operational amplifier,

25. The memory storage device of claim 20, wherein the voltage regulation circuit further comprises an initial voltage generation circuit coupled to the first regulation circuit and configured to generate the initial voltage,

26. The memory storage device of claim 15, wherein the plurality of reference voltages are sequentially generated based on a plurality of clock edges of a clock signal.

27. The memory storage device of claim 16, wherein the cell switching operation is performed based on a clock edge of a clock signal.

28. The memory storage device of claim 15, wherein the reference voltage generation circuit is further configured to generate the mapping current flowing through the at least one second type transistor cell according to the reference current flowing through the at least one first type transistor cell.

29. A method for generating a reference voltage, which is used for a memory storage device, comprises:

receiving a control voltage and generating a plurality of reference voltages at a detection point in a reference voltage generating circuit;

correcting the reference voltage according to a voltage change of the plurality of reference voltages; and

generating a specific voltage according to the modified reference voltage,

the generating of the reference voltage according to the voltage variation of the plurality of reference voltages includes:

receiving the reference voltage and the plurality of reference voltages;

if the reference voltage is higher than a third reference voltage in the plurality of reference voltages, reducing the voltage value of the reference voltage from a first voltage value to a second voltage value; and

if the reference voltage is lower than the third reference voltage, increasing the voltage value of the reference voltage from the first voltage value to a third voltage value.

30. The method according to claim 29, wherein the plurality of reference voltages comprises a first reference voltage and a second reference voltage, and the reference voltage generation circuit comprises a plurality of transistor units,

the step of generating the plurality of reference voltages at the detecting point inside the reference voltage generating circuit comprises:

generating the first reference voltage at the detection point;

performing a cell switching operation on the plurality of transistor cells after the first reference voltage is generated; and

31. The method according to claim 30, wherein the plurality of transistor cells includes at least one first type transistor cell and at least one second type transistor cell,

generating the control voltage by a voltage supply circuit;

receiving the control voltage by the at least one first-type transistor unit and providing a feedback voltage to an input end of the voltage supply circuit; and

receiving the control voltage by the at least one second-class transistor unit and providing the plurality of reference voltages at the detection point.

32. The method according to claim 31, wherein the cell switching operation comprises at least one of a first cell switching operation and a second cell switching operation,

the first cell switching operation includes:

the second unit switching operation includes:

33. The method according to claim 31, wherein a total number of the at least one first type transistor cells is equal to a total number of the at least one second type transistor cells.

34. The method according to claim 29, wherein the reference voltages are sequentially generated based on clock edges of a clock signal.

35. The method according to claim 30, wherein the cell switching operation is performed based on a clock edge of a clock signal.

36. The reference voltage generation method according to claim 31, further comprising:

generating a mapping current flowing through the at least one second-type transistor unit according to the reference current flowing through the at least one first-type transistor unit.