CN111831024B - Temperature control circuit, memory storage device and temperature control method - Google Patents

Temperature control circuit, memory storage device and temperature control method Download PDF

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Publication number
CN111831024B
CN111831024B CN201910317297.7A CN201910317297A CN111831024B CN 111831024 B CN111831024 B CN 111831024B CN 201910317297 A CN201910317297 A CN 201910317297A CN 111831024 B CN111831024 B CN 111831024B
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circuit
evaluation information
storage device
information
memory storage
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CN111831024A (en
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叶家惠
黄昭达
李宜峰
邱柏捷
凌君瑜
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
    • G05D23/00—Control of temperature
    • G05D23/19—Control of temperature characterised by the use of electric means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management

Abstract

Exemplary embodiments of the present invention provide a temperature control circuit, a memory storage device and a temperature control method for an electronic device. The temperature control circuit comprises a temperature detector, a state detection circuit and a control circuit. The temperature detector is used for detecting the temperature of the electronic device and generating first evaluation information. The state detection circuit is used for detecting the working state of at least one circuit module in the electronic device and generating second evaluation information. The control circuit is used for adjusting at least one electrical parameter of the electronic device according to the first evaluation information and the second evaluation information so as to control the temperature of the electronic device.

Description

Temperature control circuit, memory storage device and temperature control method
Technical Field
The present invention relates to temperature control technology for electronic devices, and more particularly, to a temperature control circuit, a memory storage device and a temperature control method.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
When the temperature of a memory storage device or other type of electronic device is too high, internal circuitry or stored data may be corrupted. Therefore, the temperature of the device can be detected by the temperature detector, and the frequency divider circuit is used to reduce the system frequency, so as to try to reduce the temperature of the device. However, in practice, adjusting the system frequency simply according to the temperature often results in the system frequency being excessively reduced, which greatly affects the device performance.
Disclosure of Invention
The invention provides a temperature control circuit, a memory storage device and a temperature control method, which can improve the problems.
An exemplary embodiment of the present invention provides a temperature control circuit for an electronic device. The temperature control circuit comprises a temperature detector, a state detection circuit and a control circuit. The temperature detector is used for detecting the temperature of the electronic device and generating first evaluation information. The state detection circuit is used for detecting the working state of at least one circuit module in the electronic device and generating second evaluation information. The control circuit is connected to the temperature detector and the state detection circuit and used for adjusting at least one electrical parameter of the electronic device according to the first evaluation information and the second evaluation information so as to control the temperature of the electronic device.
In an exemplary embodiment of the invention, the at least one circuit module includes a first circuit module and a second circuit module, and the operation of the state detection circuit detecting the operating state of the at least one circuit module in the electronic device and generating the second evaluation information includes: detecting a first working state of the first circuit module; detecting a second operating state of the second circuit module; and generating the second evaluation information according to the first working state, the second working state, the first weight information of the first circuit module and the second weight information of the second circuit module.
In an exemplary embodiment of the present invention, the state detection circuit includes a first gate circuit, a second gate circuit and a logic circuit. The first gate circuit is configured to generate a first output signal according to a first status signal and a first weight signal, wherein the first status signal reflects the first operating status, and the first weight signal reflects the first weight information. The second gate circuit is used for generating a second output signal according to a second state signal and a second weight signal, wherein the second state signal reflects the second working state, and the second weight signal reflects the second weight information. The logic circuit is connected to the first gate circuit and the second gate circuit and is configured to generate the second evaluation information according to the first output signal and the second output signal.
In an exemplary embodiment of the invention, the logic circuit includes an accumulator and a normalization circuit. The accumulator is connected to the first gate circuit and the second gate circuit and is used for generating accumulation information according to the first output signal and the second output signal. The normalization circuit is connected to the accumulator and is used for generating the second evaluation information according to the accumulation information.
In an exemplary embodiment of the invention, the temperature control circuit further includes a current meter connected to the control circuit and configured to detect a current of the electronic device and generate third evaluation information. The control circuit further adjusts the at least one electrical parameter of the electronic device according to the third evaluation information.
In an exemplary embodiment of the invention, the control circuit includes a comparator and an adjusting circuit. The comparator is used for generating adjustment information according to the second evaluation information and at least one threshold information. The adjusting circuit is connected to the comparator and is used for adjusting the at least one electrical parameter of the electronic device from a first electrical parameter to a second electrical parameter according to the adjusting information so as to reduce the temperature of the electronic device.
In an exemplary embodiment of the invention, the control circuit further includes a restoring circuit connected to the adjusting circuit and configured to restore the at least one electrical parameter from the second electrical parameter to the first electrical parameter when at least one of the first evaluation information and the second evaluation information meets a predetermined condition.
In an exemplary embodiment of the present invention, the recovery circuit includes a counter and a recovery controller. The counter is used for counting the maintaining time of the temperature of the electronic device at a preset temperature. The recovery controller is connected to the counter and is used for recovering the at least one electrical parameter to the first electrical parameter according to the maintaining time.
In an exemplary embodiment of the invention, the temperature control circuit further includes a compensation circuit connected to the control circuit and configured to generate at least one compensation parameter according to the temperature of the electronic device to compensate at least one analog circuit related to the at least one electrical parameter.
In an exemplary embodiment of the invention, the at least one electrical parameter includes at least one of a system voltage of the electronic device, a system frequency of the electronic device, an input voltage of the at least one circuit module, an output voltage of the at least one circuit module, and weight information of the at least one circuit module.
An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, a memory control circuit unit and a temperature control circuit. The connection interface unit is used for connecting to a host system. The temperature control circuit is connected to the connection interface unit, the rewritable nonvolatile memory module and the memory control circuit unit. The temperature control circuit is used for detecting the temperature of the memory storage device and generating first evaluation information. The temperature control circuit is further used for detecting the working state of at least one circuit module in the memory storage device and generating second evaluation information. The temperature control circuit is further configured to adjust at least one electrical parameter of the memory storage device according to the first evaluation information and the second evaluation information to control the temperature of the memory storage device.
In an exemplary embodiment of the invention, the at least one circuit module includes a first circuit module and a second circuit module, and the operation of the temperature control circuit detecting the operating state of the at least one circuit module in the memory storage device and generating the second evaluation information includes: detecting a first working state of the first circuit module; detecting a second operating state of the second circuit module; and generating the second evaluation information according to the first working state, the second working state, the first weight information of the first circuit module and the second weight information of the second circuit module.
In an exemplary embodiment of the present invention, the operation of the temperature control circuit generating the second evaluation information according to the first operating state, the second operating state, the first weight information of the first circuit module and the second weight information of the second circuit module includes: generating a first output signal according to a first status signal and a first weight signal, wherein the first status signal reflects the first working status and the first weight signal reflects the first weight information; generating a second output signal according to a second status signal and a second weight signal, wherein the second status signal reflects the second operating status, and the second weight signal reflects the second weight information; and generating the second evaluation information according to the first output signal and the second output signal.
In an exemplary embodiment of the invention, the operation of the temperature control circuit generating the second evaluation information according to the first output signal and the second output signal includes: generating accumulation information according to the first output signal and the second output signal; and generating the second evaluation information according to the accumulated information.
In an exemplary embodiment of the invention, the temperature control circuit is further configured to detect a current of the memory storage device and generate third evaluation information. The temperature control circuit is further configured to adjust the at least one electrical parameter of the memory storage device according to the third evaluation information.
In an exemplary embodiment of the invention, the operation of the temperature control circuit adjusting the at least one electrical parameter of the memory storage device according to the first evaluation information and the second evaluation information to control the temperature of the memory storage device comprises: generating adjustment information according to the second evaluation information and at least one threshold information; and adjusting the at least one electrical parameter of the memory storage device from a first electrical parameter to a second electrical parameter according to the adjustment information to reduce the temperature of the memory storage device.
In an exemplary embodiment of the invention, the operation of the temperature control circuit adjusting the at least one electrical parameter of the memory storage device according to the first evaluation information and the second evaluation information to control the temperature of the memory storage device further comprises: and when at least one of the first evaluation information and the second evaluation information meets a preset condition, restoring the at least one electrical parameter from the second electrical parameter to the first electrical parameter.
In an exemplary embodiment of the invention, the operation of the temperature control circuit to restore the at least one electrical parameter from the second electrical parameter to the first electrical parameter when the at least one of the first evaluation information and the second evaluation information meets the preset condition includes: counting a maintenance time of the temperature of the memory storage device at a preset temperature; and restoring the at least one electrical parameter to the first electrical parameter according to the maintenance time.
In an exemplary embodiment of the invention, the temperature control circuit is further configured to generate at least one compensation parameter according to the temperature of the memory storage device to compensate at least one analog circuit related to the at least one electrical parameter.
An exemplary embodiment of the present invention further provides a temperature control method for a memory storage device. The temperature control method comprises the following steps: detecting a temperature of the memory storage device and generating first evaluation information; detecting the working state of at least one circuit module in the memory storage device and generating second evaluation information; and adjusting at least one electrical parameter of the memory storage device according to the first evaluation information and the second evaluation information to control the temperature of the memory storage device.
In an exemplary embodiment of the invention, the at least one circuit module includes a first circuit module and a second circuit module, and the step of detecting the operating state of the at least one circuit module in the memory storage device and generating the second evaluation information includes: detecting a first working state of the first circuit module; detecting a second operating state of the second circuit module; and generating the second evaluation information according to the first working state, the second working state, the first weight information of the first circuit module and the second weight information of the second circuit module.
In an exemplary embodiment of the present invention, the step of generating the second evaluation information according to the first operating status, the second operating status, the first weight information of the first circuit module and the second weight information of the second circuit module includes: generating a first output signal according to a first status signal and a first weight signal, wherein the first status signal reflects the first working status and the first weight signal reflects the first weight information; generating a second output signal according to a second status signal and a second weight signal, wherein the second status signal reflects the second operating status, and the second weight signal reflects the second weight information; and generating the second evaluation information according to the first output signal and the second output signal.
In an exemplary embodiment of the present invention, the step of generating the second evaluation information according to the first output signal and the second output signal includes: generating accumulation information according to the first output signal and the second output signal; and generating the second evaluation information according to the accumulated information.
In an exemplary embodiment of the invention, the operating state of the at least one circuit module corresponds to a busy state of the at least one circuit module.
In an exemplary embodiment of the invention, the temperature control method further includes: detecting a current of the memory storage device and generating third evaluation information; and adjusting the at least one electrical parameter of the memory storage device according to the third evaluation information.
In an exemplary embodiment of the present invention, the step of adjusting the at least one electrical parameter of the memory storage device according to the first evaluation information and the second evaluation information to control the temperature of the memory storage device comprises: generating adjustment information according to the second evaluation information and at least one threshold information; and adjusting the at least one electrical parameter of the memory storage device from a first electrical parameter to a second electrical parameter according to the adjustment information to reduce the temperature of the memory storage device.
In an exemplary embodiment of the invention, the step of adjusting the at least one electrical parameter of the memory storage device according to the first evaluation information and the second evaluation information to control the temperature of the memory storage device further comprises: and when at least one of the first evaluation information and the second evaluation information meets a preset condition, restoring the at least one electrical parameter from the second electrical parameter to the first electrical parameter.
In an exemplary embodiment of the invention, the step of restoring the at least one electrical parameter from the second electrical parameter to the first electrical parameter when the at least one of the first evaluation information and the second evaluation information meets the predetermined condition includes: counting a maintenance time of the temperature of the memory storage device at a preset temperature; and restoring the at least one electrical parameter to the first electrical parameter according to the maintenance time.
In an exemplary embodiment of the invention, the temperature control method further includes: generating at least one compensation parameter based on the temperature of the memory storage device to compensate at least one analog circuit associated with the at least one electrical parameter.
In an exemplary embodiment of the invention, the at least one electrical parameter includes at least one of a system voltage of the electronic device, a system frequency of the electronic device, an input voltage of the at least one circuit module, an output voltage of the at least one circuit module, and weight information of the at least one circuit module.
Based on the above, after the temperature of the electronic device and the operating state of at least one circuit module in the electronic device are measured, the control circuit may adjust at least one electrical parameter of the electronic device according to the corresponding evaluation information to control the temperature of the electronic device. The temperature is assisted by detecting the working state of the circuit module to adjust the electrical parameters, so that the balance between temperature control and system efficiency maintenance can be more accurately obtained.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram of a temperature control circuit according to an exemplary embodiment of the present invention.
FIG. 2 is a schematic diagram of a state detection circuit according to an exemplary embodiment of the present invention.
Fig. 3 is a schematic diagram of a control circuit according to an exemplary embodiment of the present invention.
Fig. 4 is a schematic diagram of a control circuit according to an exemplary embodiment of the present invention.
Fig. 5 is a schematic diagram of a compensation circuit according to an exemplary embodiment of the invention.
FIG. 6 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention.
FIG. 7 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
FIG. 8 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.
FIG. 9 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Fig. 10 is a flowchart illustrating a temperature control method according to an exemplary embodiment of the present invention.
[ notation ] to show
10: temperature control circuit
11: temperature detector
12: state detection circuit
13: control circuit
14. 510: voltage regulation circuit
15. 520, the method comprises the following steps: oscillator
16: current meter
17: compensation circuit
101. 201(1) - (201 (n): circuit module
210(1) -210 (n): gate circuit
220: logic circuit
221: accumulator
222: normalization circuit
310: comparator with a comparator circuit
320: adjusting circuit
321: updating a filter
322: scheduler
330: recovery circuit
331: recovery controller
332: recovery monitor
333: recovery counter
501-503: multiplexer
530: I/O driver
60. 80, 90: memory storage device
61. 81: host system
610: system bus
611: processor with a memory having a plurality of memory cells
612: random access memory
613: read-only memory
614: data transmission interface
62: input/output (I/O) device
70: main machine board
701: u disk
702: memory card
703: solid state disk
704: wireless memory storage device
705: global positioning system module
706: network interface card
707: wireless transmission device
708: keyboard with a keyboard body
709: screen
710: horn type loudspeaker
82: SD card
83: CF card
64: embedded memory device
841: embedded multimedia card
842: embedded multi-chip packaging storage device
902: connection interface unit
904: memory control circuit unit
906: rewritable nonvolatile memory module
S1001: step (detecting the temperature of the electronic device and generating the first evaluation information)
S1002: step (detecting the operating status of at least one circuit module in the electronic device and generating second evaluation information)
S1003: step (adjusting at least one electrical parameter of the electronic device according to the first evaluation information and the second evaluation information to control the temperature of the electronic device)
Detailed Description
In the following, a number of embodiments are presented to illustrate the invention, however, the invention is not limited to the illustrated embodiments. Suitable combinations between the embodiments are also allowed. The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples to a second device, that connection should be interpreted as either being a direct connection, or a indirect connection via other devices and some means of connection. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.
Fig. 1 is a schematic diagram of a temperature control circuit according to an exemplary embodiment of the present invention. Referring to fig. 1, a temperature control circuit 10 may be disposed in any type of electronic device to control (or regulate) a temperature of the electronic device. In an example embodiment, the electronic device may be a memory storage device for storing data. Alternatively, in another exemplary embodiment, the electronic device may be other types of electronic devices, and the invention is not limited thereto.
In an exemplary embodiment, the temperature control circuit 10 includes a temperature detector 11, a state detection circuit 12, a control circuit 13, a voltage adjustment circuit 14, and an oscillator 15. The temperature detector 11 is used for detecting the temperature of the electronic device and generating corresponding evaluation information (also referred to as first evaluation information) ES (1). For example, the temperature detector 11 may include a thermocouple, a thermistor, or other type of temperature sensing element. The temperature detector 11 can generate evaluation information ES (1) based on the measured temperature. In other words, the evaluation information ES (1) may reflect the measured temperature of the electronic device.
The state detection circuit 12 can be used to detect the operating state of the circuit module 101 in the electronic device and generate corresponding evaluation information (also referred to as second evaluation information) ES (2). The evaluation information ES (2) may reflect the operating state of the circuit module 101. It should be noted that the number of the circuit modules 101 may be one or more, and the invention is not limited thereto. In addition, one circuit module 101 may be a chip module, a controller module, a driving circuit module or a flash memory module, and the invention does not limit the type, circuit composition and function of the circuit module 101. In an exemplary embodiment, all electronic circuits in the electronic device that generate power consumption belong to a specific circuit module 101.
In an exemplary embodiment, the operating state of the circuit module 101 corresponds to a busy state of the circuit module 101. For example, the state detection circuit 12 may obtain the busy state of the current circuit module 101 according to the measured operating state of the circuit module 101. This busy state may reflect that the circuit module 101 is currently in a busy or idle state. The state detection circuit 12 may generate the evaluation information ES (2) according to the operating state of the circuit module 101.
In an exemplary embodiment, the evaluation information ES (1) and ES (2) are transmitted in the form of current or other signals. For example, in an exemplary embodiment, the temperature detector 11 may convert the measured temperature into an output current (also referred to as a first current) and the state detection circuit 12 may convert the measured operating state into an output current (also referred to as a second current). The current value of the first current may be positively correlated to the measured temperature of the electronic device. The current value of the second current may be positively correlated to the measured busy level of the circuit module 101.
The control circuit 13 is connected to the temperature detector 11 and the state detection circuit 12. The control circuit 13 can receive evaluation information ES (1) and ES (2) from the temperature detector 11 and the state detection circuit 12, respectively. The control circuit 13 can adjust at least one electrical parameter of the electronic device according to the evaluation information ES (1) and ES (2) to control the temperature of the electronic device. The control circuit 13 may include one or more controllers or other types of control elements.
The voltage adjusting circuit 14 is connected to the control circuit 13 and outputs a voltage (also referred to as a system voltage). The oscillator 15 is connected to the control circuit 13 and is used for outputting a clock signal (also referred to as a system clock signal or a reference clock signal). The voltage outputted from the voltage adjusting circuit 14 and the clock signal outputted from the oscillator 15 can be provided to various electronic circuits and/or electronic components in the electronic device. Based on the evaluation information ES (1) and ES (2), the control circuit 13 can send the adjustment signal ADV (1) to the voltage adjustment circuit 14 and/or send the adjustment signal ADV (2) to the oscillator 15. The voltage adjusting circuit 14 may dynamically adjust (e.g., increase or decrease) the voltage value of the output voltage according to the adjusting signal ADV (1). The oscillator 15 can dynamically adjust (e.g., increase or decrease) the frequency (also referred to as the system frequency) of the outputted clock signal according to the adjustment signal ADV (2).
In an example embodiment, the electrical parameter comprises a system voltage and/or a system frequency. The control circuit 13 may reduce the voltage value of the voltage outputted by the voltage adjusting circuit 14 (i.e. the system voltage) and/or reduce the frequency of the clock signal outputted by the oscillator 15 (i.e. the system frequency) by adjusting at least one of the signals ADV (1) and ADV (2), so as to reduce the temperature of the electronic device. In an example embodiment, a decrease in system voltage and/or system frequency may result in a decrease in system performance of the electronic device. Therefore, if the temperature does not need to be continuously decreased, the control circuit 13 may increase the voltage value of the voltage outputted by the voltage adjusting circuit 14 and/or increase the frequency of the clock signal outputted by the oscillator 15 by adjusting at least one of the signals ADV (1) and ADV (2), so as to recover the system performance of the electronic device. It should be noted that, in an exemplary embodiment, the electrical parameters may also include other types of parameters that can be used to adjust the temperature of the electronic device, such as the operating mode of a specific electronic circuit, and the like, and the invention is not limited thereto.
In an exemplary embodiment, it is assumed that the circuit block 101 includes at least two circuit blocks. The circuit modules can be electrically independent or electrically connected with each other. The state detection circuit 12 can detect an operating state (also referred to as a first operating state) of a certain circuit block (also referred to as a first circuit block) in the circuit blocks 101. The state detection circuit 12 may detect an operating state (also referred to as a second operating state) of another circuit block (also referred to as a second circuit block) in the circuit block 101. The state detection circuit 12 can generate the evaluation information ES (2) according to the first operating state, the second operating state, the weight information of the first circuit block (also referred to as first weight information) and the weight information of the second circuit block (also referred to as second weight information). It should be noted that the first weight information may be the same as or different from the second weight information. For example, the first weight information may include one weight value (also referred to as a first weight value), and the second weight information may include another weight value (also referred to as a second weight value). The first weight value may be the same or different from the second weight value.
FIG. 2 is a schematic diagram of a state detection circuit according to an exemplary embodiment of the present invention. Referring to FIG. 2, in an exemplary embodiment, the state detection circuit 12 includes gate circuits 210(1) -210 (n) and a logic circuit 220. The gate circuits 210(1) to 210(n) can be connected to the circuit modules 201(1) to 201(n) respectively to detect the operating states of the circuit modules 201(1) to 201 (n). For example, the gate circuits 210(1) to 210(n) may detect the state signals BS (1) to BS (n) from the circuit modules 201(1) to 201(n), respectively. The state signals BS (1) to BS (n) reflect the operating states (or busy states) of the circuit blocks 201(1) to 201(n), respectively. Taking the state signal BS (1) as an example, a logic high of the state signal BS (1) may indicate that the circuit block 201(1) is currently in a busy state, and a logic low of the state signal BS (1) may indicate that the circuit block 201(1) is not currently in a busy state.
The gate circuits 210(1) -210 (n) can also receive the weight signals W (1) -W (n), respectively. The weight signals W (1) to W (n) correspond to the circuit blocks 201(1) to 201(n), respectively. For example, the weight signals W (1) to W (n) may reflect weight information corresponding to the circuit blocks 201(1) to 201(n), respectively.
The gate circuits 210(1) to 210(n) can generate output signals WS (1) to WS (n) according to the status signals BS (1) to BS (n) and the weight signals W (1) to W (n). For example, the gate circuit 210(1) can generate the output signal WS (1) according to the status signal BS (1) and the weight signal W (1). The state signal BS (1) reflects the operating state of the circuit module 201 (1). The weight signal W (1) reflects weight information corresponding to the circuit block 201 (1). For example, the gate circuit 210(1) can generate the output signal WS (2) according to the status signal BS (2) and the weight signal W (2). The state signal BS (2) reflects the operating state of the circuit module 201 (2). The weight signal W (2) reflects weight information corresponding to the circuit block 201 (2).
In an exemplary embodiment, the weight information corresponding to a circuit block is related to the attribute, area and/or power consumption of the circuit block. Taking the circuit module 201(1) as an example, the weight signal W (1) may positively relate to the area and/or power consumption of the circuit module 201 (1). That is, the higher the area and/or power consumption of the circuit module 201(1), the greater the weight information (e.g., weight value) reflected by the weight signal W (1). Alternatively, for example, in the circuit modules 201(1) and 201(2), if the area of the circuit module 201(1) is larger than the area of the circuit module 201(2) and/or the power consumption of the circuit module 201(1) is larger than the power consumption of the circuit module 201(2), the weight information (e.g., the weight value) reflected by the weight signal W (1) may be larger than the weight information (e.g., the weight value) reflected by the weight signal W (2).
The logic circuit 220 is connected to the gate circuits 210(1) to 210 (n). The logic circuit 220 may generate the evaluation information ES (2) according to the output signals WS (1) -WS (n). For example, the logic circuit 220 may accumulate the output signals WS (1) -WS (n) to generate the evaluation information ES (2). In addition, the logic circuit 220 may normalize the accumulated result of the signals WS (1) -WS (n) to generate the evaluation information ES (2).
In an exemplary embodiment, the logic circuit 220 includes an accumulator 221 and a normalization circuit 222. The output of accumulator 221 is connected to the input of normalization circuit 222. The accumulator 221 receives the output signals WS (1) -WS (n) and accumulates the output signals WS (1) -WS (n) to generate accumulated information. The accumulated information may reflect the sum of the logic values respectively corresponding to the signals WS (1) -WS (n). The normalization circuit 222 receives the accumulated information and performs a normalization operation on the accumulated information to generate the evaluation information ES (2).
In an exemplary embodiment, it is assumed that the status signals BS (1) and BS (2) are both logic high (corresponding to a logic value "1"), the remaining status signals are both logic low (corresponding to a logic value "0"), and the weight signals WS (1) and WS (2) correspond to weight values "10" and "5", respectively. The gate circuit 210(1) can multiply the logic value "1" corresponding to the status signal BS (1) by the weight value "10" corresponding to the weight signal WS (1) to generate the output signal WS (1) (i.e., 1 × 10 ═ 10) corresponding to the logic value "10". The gate circuit 210(2) can multiply the logic value "1" corresponding to the status signal BS (2) by the weight value "5" corresponding to the weight signal WS (2) to generate the output signal WS (2) corresponding to the logic value "5" (i.e., 1 × 5 ═ 5). The accumulator 221 may obtain the sum of the logical values "10" and "5" as the logical value "15" (i.e., 10+5 ═ 15) (i.e., the accumulated information). Then, the normalization circuit 222 adds an adjustment value to the logic value "15" to generate the evaluation information ES (2). For example, assuming that the adjustment value is a logical value of "200", the evaluation information ES (2) may correspond to a logical value of "215" (i.e., 15+200 ═ 215). Thus, the normalizing circuit 222 can output a current of 215 milliamperes (mA) (i.e., the second current).
It should be noted that, in another exemplary embodiment, the adjustment value may be other values depending on the practical requirements. In addition, the normalization operation is only exemplary, and the present invention is not limited to the details of the normalization operation performed by the normalization circuit 222. For example, in another exemplary embodiment, the normalization circuit 222 may generate the evaluation information ES (2) through other logic operations, such as multiplying the accumulated information by an adjustment value.
In an exemplary embodiment, the temperature control circuit 10 of fig. 1 further includes a current meter 16. The current meter 16 is connected to the circuit module 101 and the control circuit 13. The current meter 16 may be configured to detect a current of an electronic device (e.g., the circuit module 101) and generate evaluation information (also referred to as third evaluation information) ES (3). In other words, the evaluation information ES (3) may reflect the current flowing through the at least one detection pin of the circuit module 101, and the evaluation information ES (3) may positively correlate the current value of the current. The evaluation information ES (3) may also be output in the form of a current (also referred to as a third current).
In an exemplary embodiment, the control circuit 13 may generate the adjustment signal ADV (1) and/or ADV (2) according to at least one of the evaluation information ES (1) -ES (3). For example, the control circuit 13 may analyze at least one of the evaluation information ES (1) to ES (3) and generate the adjustment signal ADV (1) and/or ADV (2) according to the analysis result. In an exemplary embodiment, a logic value (e.g., a current value) corresponding to at least one of the evaluation information ES (1) -ES (3) may positively correlate to an adjustment amount (or an adjustment magnitude) of the electrical parameter. For example, assuming that the control circuit 13 generates the adjustment signal ADV (1) according to the evaluation information ES (1), the larger the logic value of the evaluation information ES (1), the larger the voltage drop amount of the output voltage of the voltage adjustment circuit 14 may be. Alternatively, assuming that the control circuit 13 generates the adjustment signal ADV (2) according to the evaluation information ES (1) and ES (2), the larger the logic value of the evaluation information ES (1) and/or ES (2) is, the larger the amount of decrease in the frequency of the output clock of the oscillator 15 can be.
Fig. 3 is a schematic diagram of a control circuit according to an exemplary embodiment of the present invention. Referring to fig. 3, in an exemplary embodiment, the control circuit 13 includes a comparator 310 and an adjusting circuit 320. The output of the comparator 310 is connected to the input of the adjustment circuit 320. The comparator 310 may receive the evaluation information es (i) and the threshold information THR. The evaluation information ES (i) may be one of the evaluation information ES (1) to ES (3). The comparator 310 may generate the adjustment information ADI according to the evaluation information es (i) and the threshold information THR. For example, the comparator 310 may compare the evaluation information es (i) with the threshold information THR and generate the adjustment information ADI according to the comparison result. The adjusting circuit 320 may generate the adjusting signal ADV (1) and/or ADV (2) according to the adjusting information ADI. According to the adjustment signals ADV (1) and/or ADV (2), at least one electrical parameter of the electronic device can be adjusted from one electrical parameter (also referred to as a first electrical parameter) to another electrical parameter (also referred to as a second electrical parameter) to reduce the temperature of the electronic device. For example, assuming that the current system voltage is 0.9 volts (V), the adjusting circuit 320 may generate the adjusting signal ADV (1) to reduce the system voltage to 0.7V. In addition, the evaluation information ES (i) may be switched between the evaluation information ES (1) to ES (3) while the temperature of the electronic device is adjusted.
In an exemplary embodiment, the adjusting circuit 320 includes an update filter 321 and a scheduler 322. The output of the update filter 321 is connected to the input of the scheduler 322. The update filter 321 is used to filter noise and/or glitches in the evaluation information es (i). The scheduler 322 is used for generating the adjustment signal ADV (1) and/or ADV (2) according to the output of the update filter 321. For example, the scheduler 322 may generate at least one of the adjustment signals ADV (1) and ADV (2) according to a set scheduling rule. For example, the scheduling rule may be decided according to the evaluation information es (i). For example, the scheduler 322 may decide the scheduling rule to be used according to the temperature of the current electronic device (or the evaluation information ES (1)). Furthermore, the set scheduling rules may be different at different temperature ranges.
Fig. 4 is a schematic diagram of a control circuit according to an exemplary embodiment of the present invention. Referring to fig. 4, in an exemplary embodiment, the control circuit 13 includes a comparator 310, an adjusting circuit 320, and a restoring circuit 330. The recovery circuit 330 is connected to the comparator 310 and the adjustment circuit 320. The recovery circuit 330 may determine whether at least one of the evaluation information ES (1) to ES (3) meets a predetermined condition. If at least one of the evaluation information ES (1) -ES (3) meets a predetermined condition, the restoring circuit 330 may restore the adjusted electrical parameter from the second electrical parameter to the first electrical parameter. Thus, after adjusting a portion of the electrical parameter of the electronic device to the second electrical parameter to cool down, the recovery circuit 330 may be used to recover (e.g., improve) at least a portion of the system performance.
In an example embodiment, the recovery circuit 330 includes a controller (also referred to as a recovery controller) 331, a monitor (also referred to as a recovery monitor) 332, and a counter (also referred to as a recovery counter) 333. The restoration monitor 332 may receive the evaluation information es (i) and continuously analyze the evaluation information es (i). If the evaluation information es (i) meets a trigger condition, the resume monitor 332 may start the resume counter 333 to start counting. If the count value of the recovery counter 333 matches a predetermined value, the recovery controller 331 may instruct the adjusting circuit 320 to generate the corresponding adjusting signals ADV (1) and/or ADV (2) to recover the adjusted electrical parameter from the second electrical parameter to the first electrical parameter.
In an exemplary embodiment, after adjusting some electrical parameters to the second electrical parameters to reduce the temperature of the electronic device, the recovery monitor 332 may continuously determine whether the temperature of the electronic device reaches a predetermined temperature (or a predetermined temperature range) according to the evaluation information ES (1). If the temperature of the electronic device reaches the predetermined temperature, the resume monitor 332 may start the resume counter 333 to count the time for which the temperature of the electronic device is maintained at the predetermined temperature. The recovery controller 331 may recover the adjusted electrical parameter from the second electrical parameter to the first electrical parameter according to the hold time. For example, after the temperature of the electronic device is maintained at a predetermined temperature (or a predetermined temperature range) for a predetermined time, the recovery controller 331 may instruct the adjusting circuit 320 to update at least one of the adjusting signals ADV (1) and ADV (2) to increase the system voltage and/or the system frequency. Alternatively, if the temperature of the electronic device does not reach the predetermined time in the maintaining time of the predetermined temperature, the recovery controller 331 may instruct the adjusting circuit 320 to maintain (or not update) the adjusting signals ADV (1) and/or ADV (2). In addition, after the recovery counter 333 is started, the recovery monitor 332 may reset the recovery counter 333 if the temperature of the electronic device is out of the preset temperature.
In other words, after the temperature of the electronic device has dropped and reached a steady state, the control circuit 13 may increase the system voltage and/or the system frequency by a small amount through the recovery circuit 330. Therefore, the system performance of the electronic device can be gradually recovered in the temperature reduction process of the electronic device. In addition, if the temperature of the electronic device rises beyond the allowable range again, the control circuit 13 may decrease the system voltage and/or the system frequency again according to the evaluation information es (i) to reduce the temperature of the electronic device.
In an exemplary embodiment, the temperature control circuit 10 of fig. 1 further includes a compensation circuit 17. The compensation circuit 17 can generate at least one compensation parameter according to the temperature of the electronic device to compensate at least one analog circuit related to the electrical parameter. For example, the compensation circuit 17 may be connected to the control circuit 13, the voltage adjustment circuit 14 and the oscillator 15. The compensation circuit 17 can obtain the temperature of the electronic device from the evaluation information ES (1). The compensation circuit 17 may generate the compensation parameters CP (1) and/or CP (2) according to the temperature. The compensation parameter CP (1) may be provided to the voltage adjusting circuit 14, and the compensation parameter CP (2) may be provided to the oscillator 15. Thus, under different temperature conditions, the voltage adjusting circuit 14 and the oscillator 15 can compensate (or adjust) the output signal according to the compensation parameters CP (1) and CP (2), respectively. It should be noted that the compensation circuit 17 can also compensate for other types of analog circuits, and is not limited to the voltage modulation circuit 14 and the oscillator 15 of fig. 1.
Fig. 5 is a schematic diagram of a compensation circuit according to an exemplary embodiment of the invention. Referring to FIG. 5, the compensation circuit 17 may include multiplexers 501-503. The multiplexers 501-503 are all used to receive the compensation parameters TP (1) -TP (3) and output the compensation parameters CP (1) -CP (3), respectively. The compensation parameters TP (1) to TP (3) are different from each other in the compensation capability of the circuit. The output terminals of the multiplexers 501-503 are connected to the voltage adjusting circuit 510, the oscillator 520 and the input/output (I/O) driver 530, respectively. Under different temperature conditions, the compensation circuit 17 may selectively provide one of the compensation parameters TP (1) -TP (3) to the voltage adjustment circuit 510, the oscillator 520, and/or the I/O driver 530 via the selection signals SEL (1) -SEL (3).
In an exemplary embodiment, the compensation parameters TP (1) -TP (3) correspond to the first temperature range to the third temperature range, respectively. The temperature of the first temperature range is higher than the temperature of the second temperature range, and the temperature of the second temperature range is higher than the temperature of the third temperature range. If the compensation circuit 17 determines that the current temperature of the electronic device belongs to the first temperature range, the compensation circuit 17 may selectively provide the compensation parameter TP (1) as the compensation parameters CP (1) -CP (3) to the voltage adjustment circuit 510, the oscillator 520 and/or the I/O driver 530 via the selection signals SEL (1) -SEL (3) to compensate the output of the voltage adjustment circuit 510, the oscillator 520 and/or the I/O driver 530. If the compensation circuit 17 determines that the current temperature of the electronic device belongs to the second temperature range, the compensation circuit 17 may selectively provide the compensation parameter TP (2) as the compensation parameters CP (1) -CP (3) to the voltage adjustment circuit 510, the oscillator 520 and/or the I/O driver 530 via the selection signals SEL (1) -SEL (3) to compensate the output of the voltage adjustment circuit 510, the oscillator 520 and/or the I/O driver 530. Alternatively, if the compensation circuit 17 determines that the current temperature of the electronic device belongs to the third temperature range, the compensation circuit 17 may selectively provide the compensation parameter TP (3) as the compensation parameters CP (1) -CP (3) to the voltage adjustment circuit 510, the oscillator 520 and/or the I/O driver 530 via the selection signals SEL (1) -SEL (3) to compensate the outputs of the voltage adjustment circuit 510, the oscillator 520 and/or the I/O driver 530.
In an exemplary embodiment, the circuit module (e.g., the circuit module 101 of fig. 1 or the circuit modules 201(1) -201 (n) of fig. 2) may also include the analog circuit for performing compensation according to the electrical parameter. For example, in the exemplary embodiment of fig. 1, the voltage adjusting circuit 14 and/or the oscillator 15 may also be included in the circuit module 101.
In an exemplary embodiment, the electrical parameter may further include an input voltage of a certain circuit module (e.g., the circuit module 201(1) of fig. 2), an output voltage of a certain circuit module, and/or weight information corresponding to a certain circuit module (e.g., the weight signal W (1) corresponding to the circuit module 201(1) of fig. 2). According to different temperature states and/or different operating states, the electrical parameters of at least some of the electronic circuits in the circuit module 101 may also be dynamically adjusted according to at least one of the evaluation information ES (1) -ES (3). Taking fig. 2 as an example, the weight value (i.e., the weight information) corresponding to the weight signal W (1) in fig. 2 may be dynamically adjusted according to different temperature states and/or different operating states of at least one electronic circuit in the circuit modules 201 (1). Therefore, the balance between temperature control and system performance can be more accurately obtained.
It should be noted that, in the foregoing exemplary embodiments, the connection relationship between the circuit elements is exemplary and not intended to limit the invention. In the foregoing exemplary embodiments, the connection relationship of at least some of the circuit elements may be adjusted, at least some of the circuit elements may be replaced with other circuit elements having the same or similar functions, and/or more circuit elements may be added to provide additional functions.
In an exemplary embodiment, the temperature control circuit 10 of fig. 1 may be disposed in a memory storage device or a memory control circuit unit. Alternatively, in an exemplary embodiment, the temperature control circuit 10 of fig. 1 may be disposed in any type of electronic device, and the invention is not limited thereto.
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 6 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 7 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 6 and 7, the host system 61 generally includes a processor 611, a Random Access Memory (RAM) 612, a Read Only Memory (ROM) 613 and a data transmission interface 614. The processor 611, the random access memory 612, the read only memory 613, and the data transmission interface 614 are all connected to a system bus (system bus) 610.
In the exemplary embodiment, host system 61 is coupled to memory storage device 60 via data transfer interface 614. For example, host system 61 may store data to memory storage device 60 or read data from memory storage device 60 via data transfer interface 614. The host system 61 is connected to the I/O device 62 via a system bus 610. For example, the host system 61 may transmit output signals to the I/O device 62 or receive input signals from the I/O device 62 via the system bus 610.
In the present exemplary embodiment, the processor 611, the ram 612, the rom 613 and the data transmission interface 614 are disposed on the motherboard 70 of the host system 61. The number of data transfer interfaces 614 may be one or more. Through the data transmission interface 614, the motherboard 70 can be connected to the memory storage device 60 through a wired or wireless manner. The memory storage device 60 may be, for example, a U disk 701, a memory card 702, a Solid State Drive (SSD) 703, or a wireless memory storage device 704. The wireless memory storage device 704 may be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 70 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 705, a network interface card 706, a wireless transmission device 707, a keyboard 708, a screen 709, and a speaker 710 via a System bus 610. For example, in an exemplary embodiment, the motherboard 70 may access the wireless memory storage device 704 via the wireless transmission device 707.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 8 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 8, in another exemplary embodiment, the host system 81 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 80 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 82, a Compact Flash (CF) card 83, or an embedded storage device 64. The embedded memory devices 64 include embedded Multi Media Card (eMMC) 841 and/or embedded Multi Chip Package (eMCP) memory devices 842 of various types that directly connect the memory modules to the host system on the substrate.
FIG. 9 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 9, the memory storage device 90 includes a connection interface unit 902, a memory control circuit unit 904, and a rewritable nonvolatile memory module 906.
The connection interface unit 902 is used to connect the memory storage device 90 to the host system 61. The memory storage device 90 may communicate with the host system 61 through the connection interface unit 902. In the exemplary embodiment, connection interface unit 902 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 902 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Memory (Flash) interface standard, the CP interface standard, the CF interface standard, the Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 902 may be packaged with the memory control circuit unit 904 in one chip, or the connection interface unit 902 may be disposed off-chip including the memory control circuit unit 904.
The memory control circuit unit 904 is configured to execute a plurality of logic gates or control commands implemented in hardware or firmware, and write, read, and erase data in the rewritable nonvolatile memory module 906 according to the commands of the host system 61.
The rewritable nonvolatile memory module 906 is connected to the memory control circuit unit 904 and stores data written by the host system 61. The rewritable nonvolatile memory module 906 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 906 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 1006 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 906 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).
In an example embodiment, the rewritable nonvolatile memory module 906 of FIG. 9 is also referred to as a flash memory module. In an example embodiment, the memory control circuit unit 904 of fig. 9 is also referred to as a flash memory controller for controlling a flash memory module.
Fig. 10 is a flowchart illustrating a temperature control method according to an exemplary embodiment of the present invention. Referring to fig. 10, in step S1001, a temperature of an electronic device (e.g., a memory storage device) is detected and first evaluation information is generated. In step S1002, an operating state of at least one circuit module in the electronic device is detected and second evaluation information is generated. In step S1003, at least one electrical parameter of the electronic device is adjusted according to the first evaluation information and the second evaluation information to control the temperature of the electronic device.
In summary, after the temperature of the electronic device and the operating state of at least one circuit module in the electronic device are measured, the control circuit can adjust at least one electrical parameter of the electronic device according to the corresponding evaluation information to control the temperature of the electronic device. The temperature is assisted by detecting the working state of the circuit module to adjust the electrical parameters, so that the balance between temperature control and system efficiency maintenance can be more accurately obtained.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (30)

1. A temperature control circuit for an electronic device, comprising:
the temperature detector is used for detecting the temperature of the electronic device and generating first evaluation information;
the state detection circuit is used for detecting a first busy or idle state of a first circuit module and a second busy or idle state of a second circuit module in the electronic device and generating second evaluation information according to the first busy or idle state, the second busy or idle state, first weight information of the first circuit module and second weight information of the second circuit module; and
a control circuit connected to the temperature detector and the status detection circuit and configured to adjust at least one electrical parameter of the electronic device according to the first evaluation information and the second evaluation information to control the temperature of the electronic device, wherein the first weighting information is positively related to an area and/or power consumption of the first circuit module, and the second weighting information is positively related to an area and/or power consumption of the second circuit module.
2. The temperature control circuit of claim 1, wherein the state detection circuit comprises:
a first gate circuit for generating a first output signal according to a first status signal and a first weight signal, wherein the first status signal reflects the first busy or idle state, and the first weight signal reflects the first weight information;
a second gate circuit for generating a second output signal according to a second status signal and a second weight signal, wherein the second status signal reflects the second busy or idle status, and the second weight signal reflects the second weight information; and
a logic circuit connected to the first gate circuit and the second gate circuit and configured to generate the second evaluation information according to the first output signal and the second output signal.
3. The temperature control circuit of claim 2, wherein the logic circuit comprises:
an accumulator connected to the first gate circuit and the second gate circuit and configured to generate accumulation information according to the first output signal and the second output signal; and
a normalization circuit connected to the accumulator and configured to generate the second evaluation information according to the accumulation information.
4. The temperature control circuit of claim 1, wherein the first busy or idle state of the first circuit module corresponds to a busy state of the first circuit module, and the second busy or idle state of the second circuit module corresponds to a busy state of the second circuit module.
5. The temperature control circuit of claim 1, further comprising:
a current meter connected to the control circuit and configured to detect a current of the electronic device and generate third evaluation information,
wherein the control circuit further adjusts the at least one electrical parameter of the electronic device according to the third evaluation information.
6. The temperature control circuit of claim 1, wherein the control circuit comprises:
a comparator for generating adjustment information according to the second evaluation information and at least one threshold information; and
the adjusting circuit is connected to the comparator and is used for adjusting the at least one electrical parameter of the electronic device from a first electrical parameter to a second electrical parameter according to the adjusting information so as to reduce the temperature of the electronic device.
7. The temperature control circuit of claim 6, wherein the control circuit further comprises:
and the restoring circuit is connected to the adjusting circuit and used for restoring the at least one electrical parameter from the second electrical parameter to the first electrical parameter when at least one of the first evaluation information and the second evaluation information meets a preset condition.
8. The temperature control circuit of claim 7, wherein the recovery circuit comprises:
a counter for counting a maintaining time of the temperature of the electronic device at a preset temperature; and
and the recovery controller is connected to the counter and is used for recovering the at least one electrical parameter to the first electrical parameter according to the maintaining time.
9. The temperature control circuit of claim 1, further comprising:
the compensation circuit is connected to the control circuit and used for generating at least one compensation parameter according to the temperature of the electronic device so as to compensate at least one analog circuit related to the at least one electrical parameter.
10. The temperature control circuit of claim 1, wherein the at least one electrical parameter comprises at least one of a system voltage of the electronic device, a system frequency of the electronic device, an input voltage of the first circuit module, an input voltage of the second circuit module, an output voltage of the first circuit module, an output voltage of the second circuit module, first weight information of the first circuit module, and second weight information of the second circuit module.
11. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module;
a memory control circuit unit; and
a temperature control circuit connected to the connection interface unit, the rewritable nonvolatile memory module and the memory control circuit unit,
wherein the temperature control circuit is configured to detect a temperature of the memory storage device and generate first evaluation information,
the temperature control circuit is further configured to detect a first busy or idle state of a first circuit module and a second busy or idle state of a second circuit module in the memory storage device, generate second evaluation information according to the first busy or idle state, the second busy or idle state, first weight information of the first circuit module, and second weight information of the second circuit module, and generate the second evaluation information, and
the temperature control circuit is further configured to adjust at least one electrical parameter of the memory storage device according to the first evaluation information and the second evaluation information to control the temperature of the memory storage device, wherein the first weighting information is positively related to the area and/or power consumption of the first circuit module, and the second weighting information is positively related to the area and/or power consumption of the second circuit module.
12. The memory storage device of claim 11, wherein the operation of the temperature control circuit to generate the second evaluation information from the first busy or idle state, the second busy or idle state, the first weight information for the first circuit module, and the second weight information for the second circuit module comprises:
generating a first output signal according to a first status signal and a first weight signal, wherein the first status signal reflects the first busy or idle state, and the first weight signal reflects the first weight information;
generating a second output signal according to a second status signal and a second weight signal, wherein the second status signal reflects the second busy or idle state, and the second weight signal reflects the second weight information; and
generating the second evaluation information according to the first output signal and the second output signal.
13. The memory storage device of claim 12, wherein the operation of the temperature control circuit to generate the second evaluation information from the first output signal and the second output signal comprises:
generating accumulation information according to the first output signal and the second output signal; and
and generating the second evaluation information according to the accumulated information.
14. The memory storage device of claim 11, wherein the first busy or idle state of the first circuit block corresponds to a busy state of the first circuit block and the second busy or idle state of the second circuit block corresponds to a busy state of the second circuit block.
15. The memory storage device of claim 11, wherein the temperature control circuit is further configured to detect a current of the memory storage device and generate third evaluation information, and
the temperature control circuit is further configured to adjust the at least one electrical parameter of the memory storage device according to the third evaluation information.
16. The memory storage device of claim 11, wherein the operation of the temperature control circuit to adjust the at least one electrical parameter of the memory storage device according to the first evaluation information and the second evaluation information to control the temperature of the memory storage device comprises:
generating adjustment information according to the second evaluation information and at least one threshold information; and
adjusting the at least one electrical parameter of the memory storage device from a first electrical parameter to a second electrical parameter according to the adjustment information to reduce the temperature of the memory storage device.
17. The memory storage device of claim 16, wherein the operation of the temperature control circuit to adjust the at least one electrical parameter of the memory storage device according to the first evaluation information and the second evaluation information to control the temperature of the memory storage device further comprises:
and when at least one of the first evaluation information and the second evaluation information meets a preset condition, restoring the at least one electrical parameter from the second electrical parameter to the first electrical parameter.
18. The memory storage device of claim 17, wherein the operation of the temperature control circuit to restore the at least one electrical parameter from the second electrical parameter to the first electrical parameter when the at least one of the first evaluation information and the second evaluation information meets the preset condition comprises:
counting a maintenance time of the temperature of the memory storage device at a preset temperature; and
and restoring the at least one electrical parameter to the first electrical parameter according to the maintaining time.
19. The memory storage device of claim 11, wherein the temperature control circuit is further configured to generate at least one compensation parameter based on the temperature of the memory storage device to compensate at least one analog circuit related to the at least one electrical parameter.
20. The memory storage device of claim 11, wherein the at least one electrical parameter comprises at least one of a system voltage of the memory storage device, a system frequency of the memory storage device, an input voltage of the first circuit module, an input voltage of the second circuit module, an output voltage of the first circuit module, an output voltage of the second circuit module, first weight information of the first circuit module, and second weight information of the second circuit module.
21. A temperature control method for a memory storage device, the temperature control method comprising:
detecting a temperature of the memory storage device and generating first evaluation information;
detecting a first busy or idle state of a first circuit module and a second busy or idle state of a second circuit module in the memory storage device, and generating second evaluation information according to the first busy or idle state, the second busy or idle state, first weight information of the first circuit module and second weight information of the second circuit module; and
adjusting at least one electrical parameter of the memory storage device according to the first evaluation information and the second evaluation information to control the temperature of the memory storage device, wherein the first weighting information is positively correlated to the area and/or power consumption of the first circuit module, and the second weighting information is positively correlated to the area and/or power consumption of the second circuit module.
22. The temperature control method of claim 21, wherein generating the second evaluation information according to the first busy or idle state, the second busy or idle state, the first weight information of the first circuit module, and the second weight information of the second circuit module comprises:
generating a first output signal according to a first status signal and a first weight signal, wherein the first status signal reflects the first busy or idle state, and the first weight signal reflects the first weight information;
generating a second output signal according to a second status signal and a second weight signal, wherein the second status signal reflects the second busy or idle state, and the second weight signal reflects the second weight information; and
generating the second evaluation information according to the first output signal and the second output signal.
23. The temperature control method of claim 22, wherein generating the second evaluation information from the first output signal and the second output signal comprises:
generating accumulation information according to the first output signal and the second output signal; and
and generating the second evaluation information according to the accumulated information.
24. The temperature control method of claim 21, wherein the first busy or idle state of the first circuit module corresponds to a busy state of the first circuit module, and the second busy or idle state of the second circuit module corresponds to a busy state of the second circuit module.
25. The temperature control method of claim 21, further comprising:
detecting a current of the memory storage device and generating third evaluation information; and
adjusting the at least one electrical parameter of the memory storage device according to the third evaluation information.
26. The temperature control method of claim 21, wherein adjusting the at least one electrical parameter of the memory storage device based on the first evaluation information and the second evaluation information to control the temperature of the memory storage device comprises:
generating adjustment information according to the second evaluation information and at least one threshold information; and
adjusting the at least one electrical parameter of the memory storage device from a first electrical parameter to a second electrical parameter according to the adjustment information to reduce the temperature of the memory storage device.
27. The temperature control method of claim 26, wherein adjusting the at least one electrical parameter of the memory storage device based on the first evaluation information and the second evaluation information to control the temperature of the memory storage device further comprises:
and when at least one of the first evaluation information and the second evaluation information meets a preset condition, restoring the at least one electrical parameter from the second electrical parameter to the first electrical parameter.
28. The temperature control method according to claim 27, wherein the step of restoring the at least one electrical parameter from the second electrical parameter to the first electrical parameter when the at least one of the first evaluation information and the second evaluation information meets the preset condition comprises:
counting a maintenance time of the temperature of the memory storage device at a preset temperature; and
and restoring the at least one electrical parameter to the first electrical parameter according to the maintaining time.
29. The temperature control method of claim 21, further comprising:
generating at least one compensation parameter based on the temperature of the memory storage device to compensate at least one analog circuit associated with the at least one electrical parameter.
30. The temperature control method of claim 21, wherein the at least one electrical parameter comprises at least one of a system voltage of the memory storage device, a system frequency of the memory storage device, an input voltage of the first circuit module, an input voltage of the second circuit module, an output voltage of the first circuit module, an output voltage of the second circuit module, first weight information of the first circuit module, and second weight information of the second circuit module.
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