CN109410994B

CN109410994B - Temperature control method, memory storage device and memory control circuit unit

Info

Publication number: CN109410994B
Application number: CN201710711083.9A
Authority: CN
Inventors: 刘绍先
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2017-08-18
Filing date: 2017-08-18
Publication date: 2021-06-22
Anticipated expiration: 2037-08-18
Also published as: CN109410994A

Abstract

An exemplary embodiment of the invention provides a temperature control method, a memory storage device and a memory control circuit unit. The method comprises the following steps: sensing a temperature via a temperature sensor and obtaining a temperature value; if the temperature value reaches a first threshold value, executing cooling operation based on a first cooling grade and updating the grade parameter into a first grade parameter; and after the cooling operation is executed based on the first cooling grade, if the temperature value is not reduced to be less than the first threshold value within the first time range, executing the cooling operation based on the second cooling grade according to the first grade parameter and updating the grade parameter to the second grade parameter, wherein the cooling capacity of the cooling operation executed based on the second cooling grade is higher than that of the cooling operation executed based on the first cooling grade.

Description

Temperature control method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory management technology, and more particularly, to a temperature control method, a memory storage device, and a memory control circuit unit.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.

When data reading or writing is performed for a long time, the temperature of the memory storage device may gradually rise. To avoid high temperatures affecting the performance of the memory storage device and to avoid device damage, the memory storage device may have a temperature control mechanism built in. A common temperature control mechanism is typically provided with multiple temperature ranges. Each temperature range corresponds to a fixed cooling mechanism. When the temperature of the memory storage device rises to a certain temperature range, a cooling mechanism corresponding to the temperature range is started to try to reduce the temperature of the memory storage device. When the temperature of the memory storage device is further increased to another temperature range, the next cool down mechanism may be initiated. Therefore, the temperature of the memory storage device can be gradually reduced.

However, as the types of memory storage devices and/or control chips increase, the temperature tolerances of different types of memory storage devices and/or control chips may differ. For memory storage devices and/or control chips that are temperature tolerant, the temperature that the device can withstand is high. For memory storage devices and/or control chips that are less temperature tolerant, the devices can withstand lower temperatures. For memory storage devices with different temperature tolerances, it is not possible to provide optimal temperature control parameters for each device if a fixed cooling mechanism is provided by using a conventional temperature hierarchy.

Disclosure of Invention

An exemplary embodiment of the present invention provides a temperature control method, a memory storage device and a memory control circuit unit, which can determine whether to continuously increase a cooling level of a cooling operation according to a comparison result between a detected temperature value and a single threshold value, thereby improving a temperature control mechanism of the memory storage device.

An exemplary embodiment of the present invention provides a temperature control method for a memory control circuit unit for controlling a rewritable nonvolatile memory module, the temperature control method including: sensing a temperature via a temperature sensor and obtaining a temperature value; if the temperature value reaches a first threshold value, executing a cooling operation based on a first cooling grade, and updating a grade parameter into a first grade parameter, wherein the first grade parameter corresponds to the first cooling grade; and after the temperature reduction operation is executed based on the first temperature reduction level, if the temperature value is not reduced to be smaller than the first threshold value within a first time range, changing to execute the temperature reduction operation based on a second temperature reduction level according to the first level parameter, and updating the level parameter from the first level parameter to a second level parameter, wherein the second level parameter corresponds to the second temperature reduction level, and the temperature reduction capability of the temperature reduction operation executed based on the second temperature reduction level is higher than that of the temperature reduction operation executed based on the first temperature reduction level.

In an exemplary embodiment of the invention, the temperature control method further includes: after the cooling operation is executed based on the second cooling level, if the temperature value is reduced to be smaller than the first threshold value within a second time range and the temperature value reaches a second threshold value, the cooling operation is executed based on the first cooling level according to the second level parameter, and the level parameter is updated from the second level parameter to the first level parameter, wherein the second threshold value is smaller than the first threshold value.

In an exemplary embodiment of the invention, the temperature control method further includes: after the cooling operation is executed based on the second cooling level, if the temperature value is reduced to be smaller than the first threshold value within a second time range and the temperature value does not reach a second threshold value, the cooling operation is continuously executed based on the second cooling level, wherein the second threshold value is smaller than the first threshold value.

In an exemplary embodiment of the invention, the temperature control method further includes: after the cooling operation is performed based on the second cooling level, if the temperature value decreases to be less than the first threshold value within a second time range and the temperature value increases back to the first threshold value, changing to perform the cooling operation based on a third cooling level according to the second level parameter, and updating the level parameter from the second level parameter to a third level parameter, where the third level parameter corresponds to the third cooling level, and a cooling capacity of the cooling operation performed based on the third cooling level is higher than the cooling capacity of the cooling operation performed based on the second cooling level.

In an exemplary embodiment of the invention, the temperature control method further includes: after the cooling operation is executed based on the first cooling level, if the temperature value is reduced to be smaller than the first threshold value within the first time range and the temperature value does not reach a second threshold value, the cooling operation is continuously executed based on the first cooling level, wherein the second threshold value is smaller than the first threshold value.

In an exemplary embodiment of the invention, the temperature control method further includes: before the cooling operation is executed based on the first cooling level, if the temperature value reaches a third threshold value, the cooling operation is executed based on an initial cooling level, and the level parameter is updated to an initial level parameter, wherein the initial level parameter corresponds to the initial cooling level, and the third threshold value is between the first threshold value and the second threshold value.

In an exemplary embodiment of the present invention, the cooling operation includes: and determining whether to indicate to write the written data into the rewritable nonvolatile memory module according to whether the data volume of the written data is larger than a data threshold value.

In an exemplary embodiment of the invention, the step of determining whether to instruct to write the write data to the rewritable non-volatile memory module according to whether the data amount of the write data is greater than the data threshold includes: if the data volume of the written data is larger than the data threshold value, temporarily indicating that the written data is written into the rewritable nonvolatile memory module; dynamically updating the data threshold value; and if the data volume of the written data is not larger than the data threshold value, indicating that the written data is written into the rewritable nonvolatile memory module.

Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, a temperature sensor, and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit, the rewritable nonvolatile memory module and the temperature sensor. The memory control circuit unit is used for sensing the temperature through the temperature sensor and obtaining a temperature value. If the temperature value reaches a first threshold value, the memory control circuit unit is further configured to perform a cooling operation based on a first cooling level and update a level parameter to a first level parameter, where the first level parameter corresponds to the first cooling level. After the temperature reduction operation is performed based on the first temperature reduction level, if the temperature value is not reduced to be smaller than the first threshold value within a first time range, the memory control circuit unit is further configured to change to perform the temperature reduction operation based on a second temperature reduction level according to the first level parameter and update the level parameter from the first level parameter to a second level parameter, where the second level parameter corresponds to the second temperature reduction level, and a temperature reduction capability of the temperature reduction operation performed based on the second temperature reduction level is higher than a temperature reduction capability of the temperature reduction operation performed based on the first temperature reduction level.

In an exemplary embodiment of the invention, after the temperature reduction operation is performed based on the second temperature reduction level, if the temperature value is reduced to be less than the first threshold value within a second time range and the temperature value reaches a second threshold value, the memory control circuit unit is configured to revert to performing the temperature reduction operation based on the first temperature reduction level according to the second level parameter and update the level parameter from the second level parameter to the first level parameter, wherein the second threshold value is less than the first threshold value.

In an exemplary embodiment of the invention, after the temperature reduction operation is performed based on the second temperature reduction level, if the temperature value is reduced to be smaller than the first threshold value within a second time range and the temperature value does not reach a second threshold value, the memory control circuit unit is further configured to continue to perform the temperature reduction operation based on the second temperature reduction level, wherein the second threshold value is smaller than the first threshold value.

In an exemplary embodiment of the invention, after performing the cooling operation based on the second cooling level, if the temperature value decreases to be less than the first threshold value within a second time range and the temperature value increases back to the first threshold value, the memory control circuit unit is further configured to change to perform the cooling operation based on a third cooling level according to the second level parameter and update the level parameter from the second level parameter to a third level parameter, wherein the third level parameter corresponds to the third cooling level, and a cooling capability of the cooling operation performed based on the third cooling level is higher than the cooling capability of the cooling operation performed based on the second cooling level.

In an exemplary embodiment of the invention, after the temperature reduction operation is performed based on the first temperature reduction level, if the temperature value is reduced to be smaller than the first threshold value within the first time range and the temperature value does not reach a second threshold value, the memory control circuit unit is further configured to continue to perform the temperature reduction operation based on the first temperature reduction level, wherein the second threshold value is smaller than the first threshold value

In an exemplary embodiment of the invention, before the temperature reduction operation is performed based on the first temperature reduction level, if the temperature value reaches a third threshold value, the memory control circuit unit is further configured to perform the temperature reduction operation based on an initial temperature reduction level and update the level parameter to an initial level parameter, wherein the initial level parameter corresponds to the initial temperature reduction level, and the third threshold value is between the first threshold value and the second threshold value.

In an exemplary embodiment of the invention, in the cooling operation, the memory control circuit unit is further configured to determine whether to instruct to write the write data into the rewritable non-volatile memory module according to whether a data amount of the write data is greater than a data threshold.

In an exemplary embodiment of the invention, the operation of the memory control circuit unit determining whether to instruct writing of the write data into the rewritable non-volatile memory module according to whether the data amount of the write data is greater than the data threshold value includes: if the data volume of the written data is larger than the data threshold value, temporarily indicating that the written data is written into the rewritable nonvolatile memory module; dynamically updating the data threshold value; and if the data volume of the written data is not larger than the data threshold value, indicating that the written data is written into the rewritable nonvolatile memory module.

Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit including a host interface, a memory interface, a temperature sensor, and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is connected to the host interface, the memory interface, and the temperature sensor. The memory management circuit is used for sensing the temperature through the temperature sensor and obtaining a temperature value. If the temperature value reaches a first threshold value, the memory management circuit is further configured to perform a cooling operation based on a first cooling level and update a level parameter to a first level parameter, where the first level parameter corresponds to the first cooling level. After the temperature reduction operation is performed based on the first temperature reduction level, if the temperature value is not reduced to be smaller than the first threshold value within a first time range, the memory management circuit is further configured to change to perform the temperature reduction operation based on a second temperature reduction level according to the first level parameter and update the level parameter from the first level parameter to a second level parameter, where the second level parameter corresponds to the second temperature reduction level, and a temperature reduction capability of the temperature reduction operation performed based on the second temperature reduction level is higher than a temperature reduction capability of the temperature reduction operation performed based on the first temperature reduction level.

In an exemplary embodiment of the invention, after the temperature reduction operation is performed based on the second temperature reduction level, if the temperature value decreases to be less than the first threshold value within a second time range and the temperature value reaches a second threshold value, the memory management circuit is configured to revert to performing the temperature reduction operation based on the first temperature reduction level according to the second level parameter, and update the level parameter from the second level parameter to the first level parameter, wherein the second threshold value is less than the first threshold value.

In an exemplary embodiment of the invention, after the temperature reduction operation is performed based on the second temperature reduction level, if the temperature value is reduced to be less than the first threshold value within a second time range and the temperature value does not reach a second threshold value, the memory management circuit is further configured to continuously perform the temperature reduction operation based on the second temperature reduction level, wherein the second threshold value is less than the first threshold value.

In an exemplary embodiment of the invention, after performing the cooling operation based on the second cooling level, if the temperature value decreases to be less than the first threshold value within a second time range and the temperature value increases back to the first threshold value, the memory management circuit is further configured to change to perform the cooling operation based on a third cooling level according to the second level parameter and update the level parameter from the second level parameter to a third level parameter, wherein the third level parameter corresponds to the third cooling level, and a cooling capability of the cooling operation performed based on the third cooling level is higher than the cooling capability of the cooling operation performed based on the second cooling level.

In an exemplary embodiment of the invention, after the temperature reduction operation is performed based on the first temperature reduction level, if the temperature value is reduced to be smaller than the first threshold value within the first time range and the temperature value does not reach a second threshold value, the memory management circuit is further configured to continuously perform the temperature reduction operation based on the first temperature reduction level, wherein the second threshold value is smaller than the first threshold value

In an exemplary embodiment of the invention, before the cooling operation is performed based on the first cooling level, if the temperature value reaches a third threshold value, the memory management circuit is further configured to perform the cooling operation based on an initial cooling level and update the level parameter to an initial level parameter, where the initial level parameter corresponds to the initial cooling level, and where the third threshold value is between the first threshold value and the second threshold value.

In an exemplary embodiment of the invention, in the cooling operation, the memory management circuit is further configured to determine whether to instruct to write the write data to the rewritable non-volatile memory module according to whether a data amount of the write data is greater than a data threshold.

In an exemplary embodiment of the invention, the operation of the memory management circuit determining whether to instruct writing of the write data to the rewritable non-volatile memory module according to whether the data amount of the write data is greater than the data threshold value includes: if the data volume of the written data is larger than the data threshold value, temporarily indicating that the written data is written into the rewritable nonvolatile memory module; dynamically updating the data threshold value; and if the data volume of the written data is not larger than the data threshold value, indicating that the written data is written into the rewritable nonvolatile memory module.

Based on the above, according to the sensing result of the temperature sensor, a corresponding temperature value may be obtained. If the temperature value reaches the first threshold value, a cooling operation corresponding to the first level parameter may be performed based on the first cooling level. Then, if the temperature value is not decreased to be less than the first threshold value within the first time range, according to the first class parameter, a cooling operation corresponding to the second class parameter may be performed based on the second cooling class, so as to gradually increase the cooling capability of the memory storage device according to a comparison result between the temperature value and the single threshold value. Compared with the traditional method of dividing the temperature interval to adjust the corresponding cooling mechanism, the method has more flexibility in controlling the temperature.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention.

FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating temperature values affected by a cool down operation according to an example embodiment of the invention.

FIG. 8 is a schematic diagram illustrating temperature values affected by a cool down operation according to another exemplary embodiment of the present invention.

FIG. 9 is a schematic diagram illustrating temperature values affected by a cool down operation according to another example embodiment of the present invention.

FIG. 10 is a schematic diagram illustrating temperature values affected by a cool down operation according to another exemplary embodiment of the present invention.

Fig. 11 is a flowchart illustrating a temperature control method according to an exemplary embodiment of the present invention.

Description of the reference numerals

10. 30: memory storage device

11. 31: host system

110: system bus

111: processor with a memory having a plurality of memory cells

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: main machine board

201: u disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

502: memory management circuit

504: host interface

506: memory interface

508: error checking and correcting circuit

510: buffer memory

512: power management circuit

601: storage area

602: replacement area

610(0) to 610 (B): entity unit

612(0) -612 (C): logic unit

701 to 703, 801, 901 to 903, 1001 to 1004: cooling operation

Th1, Th2, Th 3: threshold value

T1-T7: point in time

Δ T: time horizon

S1101: step (temperature is sensed and temperature value is obtained via temperature sensor)

S1102: step (judging whether cooling operation is executed)

S1103: step (judging whether the temperature value is equal to or greater than the third threshold value)

S1104: step (executing cooling operation)

S1105: step (judging whether the temperature value is equal to or greater than the first threshold value)

S1106: step (increasing the cooling grade of the cooling operation)

S1107: step (judging whether the temperature value is equal to or less than the second threshold value)

S1108: step (lowering the temperature grade of the cooling operation)

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all connected to a system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed Specification-I (UHS-I) interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (Flash ) interface standard, the CF interface standard, the Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a solid type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical programming cells on the same word line can be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit region includes 32 physical fans, and the size of one physical fan is 512-bit group (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).

Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506 and a temperature sensor 513.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in a solid state form. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 502 may also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 may also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.

The memory interface 506 is connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the command sequences may include a write command sequence for indicating data to be written, a read command sequence for indicating data to be read, an erase command sequence for indicating data to be erased, and corresponding command sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification code, memory address, etc.

The temperature sensor 513 is connected to the memory management circuit 502 and is used to sense a temperature. For example, the sensed temperature may be a temperature of the memory control circuit unit 404 and/or the rewritable non-volatile memory module 406. The temperature sensor 513 may be a thermocouple (thermocouple) temperature sensor, a resistance (resistance) temperature detector, a thermal resistance (thermistor) temperature sensor, a semiconductor (semiconductor) temperature sensor, or other various types of temperature sensors. The number of temperature sensors 513 may be one or more. The location of the temperature sensor 513 can be inside the memory control circuit unit 404, outside the memory control circuit unit 404, inside the rewritable non-volatile memory module 406, or outside the rewritable non-volatile memory module 406, and the invention is not limited thereto.

In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.

The error checking and correcting circuit 508 is connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10.

Referring to FIG. 6, the memory management circuit 502 logically groups the physical units 610(0) -610 (B) of the rewritable nonvolatile memory module 406 into the storage area 601 and the replacement area 602. The physical units 610(0) - (610 a) in the storage area 601 are used for storing data, and the physical units 610(a +1) - (610B) in the replacement area 602 are used for replacing damaged physical units in the storage area 601. For example, if the data read from a physical unit contains too many errors to be corrected, the physical unit is considered as a damaged physical unit. It is noted that if there are no physical erase units available in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 to be in a write protect (write protect) state, and no more data can be written.

In the present exemplary embodiment, each physical unit refers to a physical erase unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical programming unit, or be composed of a plurality of continuous or discontinuous physical addresses. The memory management circuitry 502 configures the logic units 612(0) - (612 (C) to map the physical units 610(0) - (610A) in the memory area 601. In the present exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic cell may also refer to a logic program cell, a logic erase cell or be composed of a plurality of continuous or discontinuous logic addresses. In addition, each of logic cells 612(0) -612 (C) may be mapped to one or more physical cells.

The memory management circuit 502 records a mapping relationship between logical units and physical units (also referred to as a logical-to-physical address mapping relationship) in at least one logical-to-physical address mapping table. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access operations with respect to the memory storage device 10 according to the logical-to-physical address mapping table.

In the present exemplary embodiment, the memory management circuit 502 senses the temperature of the memory storage device 10 via the temperature sensor 513 and obtains a temperature value. This temperature value will vary with the temperature sensed by the temperature sensor 513. This temperature value will be higher if the temperature sensed by the temperature sensor 513 is higher. The lower the temperature sensed by the temperature sensor 513, the lower this temperature value will be. If the temperature value reflects that the current temperature of memory storage device 10 may affect memory storage device 10 or even cause memory storage device 10 to be damaged, memory management circuit 502 may initiate a cooling operation. This cool down operation may be used to reduce the temperature of memory storage device 10. In addition, if the temperature value reflects that the current temperature of the memory storage device 10 has dropped to a reasonable temperature, the memory management circuit 502 will stop the cooling operation.

In the present example embodiment, the cooling operation may be performed based on a plurality of cooling levels. Assuming that the cooling operation can be performed based on the cooling levels 0 to N, the cooling capacity of the cooling operation performed based on the cooling level 0 may be lower than that of the cooling operation performed based on the cooling level 1, and the cooling capacity of the cooling operation performed based on the cooling level 1 may be lower than that of the cooling operation performed based on the cooling level 2. By analogy, the cooling capacity of the cooling operation performed based on the cooling level N-1 may be lower than that of the cooling operation performed based on the cooling level N. In other words, the cooling capacity of the cooling operation performed based on the cooling level 0 is the lowest, and the cooling capacity of the cooling operation performed based on the cooling level N is the highest. For example, N may be 10 or other positive integer depending on the practical requirements. Further, the cooling capability refers to the capability of reducing the temperature of the memory storage device 10 over a time range.

In the present exemplary embodiment, after the cooling operation is started, the cooling operation can be switched between the cooling levels 0 to N to increase or decrease the cooling capability. It should be noted that the system performance of the memory storage device 10 may be reduced or maintained as it corresponds to the increased cooling capability of the cooling operation. The system performance of the memory storage device 10 may be increased or maintained constant in response to a decrease in cooling capacity for the cooling operation.

In the exemplary embodiment, after the cooling operation is initiated, the memory management circuit 502 updates a level parameter according to the cooling level adopted by the cooling operation. A level parameter would correspond to a cooling level. For example, level parameter 0 may correspond to cooling level 0, level parameter 1 may correspond to cooling level 1, and level parameter N may correspond to cooling level N. The grade parameter is updated between 0 and N corresponding to the temperature reduction operation being switched between the temperature reduction grades 0 to N. If the current cooling operation is performed based on the cooling level M (M is an integer between 0 and N), the current level parameter is set to M (M is an integer between 0 and N). In an example embodiment, the level parameter 0 is also referred to as an initial level parameter, and the cooling level 0 is also referred to as an initial cooling level.

In an exemplary embodiment, the correspondence between the grade parameter and the cooling grade can be recorded in a cooling table, such as table 1 below.

TABLE 1

Flag bit	Grade parameter	Grade of temperature reduction
			0	0	0
1	1	1
			0	2	2
0	3	3
			0	4	4
0	5	5
			0	6	6

Taking table 1 as an example, assuming that N is 6, the level parameters 0 to 6 correspond to cooling levels 0 to 6, respectively. The flag bit is used to indicate which level parameter is the current level parameter 0-6. For example, at a certain time point, if the flag bit corresponding to level parameter 1 is set to 1 (the remaining flag bits are all 0), it indicates that the current level parameter is level parameter 1 (as shown in table 1). At another time point, if the cooling level is increased from the original cooling level 1 to the cooling level 2, the flag bit corresponding to the cooling level 1 is set to 0, and the flag bit corresponding to the cooling level 2 is set to 1, so as to indicate that the current cooling operation is operating at the cooling level 2. Based on the flag bit, the memory management circuit 502 can determine which of the level parameters 0-6 the current level parameter is. In addition, during the cooling operation, the cooling table can be loaded into the buffer memory 510 of fig. 5 for table lookup and update.

It should be noted that, although table 1 identifies the current level parameter and the cooling level by a flag bit corresponding to one level parameter. However, in another exemplary embodiment, the current rating parameter may be recorded in a specific table or field. When the cooling level needs to be adjusted, the memory management circuit 502 may look up the specific table or field to obtain the current level parameter. In addition, the table format of table 1 is merely an example. In another exemplary embodiment, the cooling table may have other formats, record other information that may be used in the cooling operation, and/or record other information related to the cooling operation. For example, in an exemplary embodiment, the cooling table may further record system parameters used for different cooling operations corresponding to different cooling levels, and the invention is not limited thereto.

In an exemplary embodiment, assume that the current level parameter is k and the cooling level of the cooling operation needs to be increased. According to the current grade parameter K, the currently adopted cooling grade K for the cooling operation can be updated to the cooling grade K +1, and the grade parameter K can be correspondingly updated to the grade parameter K + 1. Alternatively, in an exemplary embodiment, assuming that the current level parameter is P and the cooling level of the cooling operation needs to be decreased, the cooling level P currently adopted by the cooling operation may be updated to the cooling level P-1 according to the current level parameter P, and the level parameter P is also updated to the level parameter P-1 accordingly. In other words, according to the level parameter, the memory management circuit 502 can know the temperature reduction level adopted by the current temperature reduction operation, and accordingly increase or decrease the temperature reduction level of the temperature reduction operation.

In an exemplary embodiment, the cooling operation may include various cooling measures such as reducing the clock frequency of the memory storage device 10, reducing the operating voltage of the memory storage device 10, and reducing the data transmission bandwidth of the memory storage device 10. If the clock frequency, the operation voltage and/or the data transmission bandwidth of the memory storage device 10 are reduced more greatly by a certain cooling operation, the cooling capability of the cooling operation is usually higher. Conversely, if the clock frequency, the operation voltage and/or the data transmission bandwidth of the memory storage device 10 are reduced by a certain cooling operation, the cooling capability of the cooling operation is generally lower. The cooling means used in the cooling operation can be completely the same, partially the same or completely different corresponding to different cooling grades, as long as the cooling capacity requirements of the corresponding cooling grade are met.

In an exemplary embodiment, if the cooling operation includes reducing the data transmission bandwidth of the memory storage device 10, the memory management circuit 502 determines whether to instruct writing of the write data to the rewritable nonvolatile memory module 406 according to whether the data amount of the write data from the host system 11 is greater than a data threshold. For example, when receiving a write data from the host system 11, the memory management circuit 502 determines whether the data amount of the write data is greater than the data threshold. If the data amount of the write data is not greater than the data threshold, the memory management circuit 502 indicates to write the write data to the rewritable nonvolatile memory module 406.

However, if the data amount of the write data is larger than the data threshold, the memory management circuit 502 temporarily does not instruct the write data to be written into the rewritable nonvolatile memory module 406. For example, the write data may be buffered in the buffer memory 510 of FIG. 5. At the same time, the memory management circuit 502 dynamically updates the data threshold. For example, each time a predetermined period of time elapses, a predetermined value is added to the data threshold. After suspending writing of the write data to the rewritable non-volatile memory module 406, at a specific time point, if the data amount of the write data is not greater than the updated data threshold, the memory management circuit 502 will instruct to write the write data to the rewritable non-volatile memory module 406.

In an exemplary embodiment, assume that the data threshold is preset to 300 MB. If the amount of write data received from the host system 11 is 200MB (200<300), the write data may be allowed to be transferred to the rewritable nonvolatile memory module 406 for storage. However, if the data amount of a certain write data received from the host system 11 is 500MB (500>300), the write data is temporarily stored in the buffer memory 510 and is not immediately transferred to the rewritable nonvolatile memory module 406. On the other hand, the data threshold is updated in response to the write data not being transferred to the rewritable nonvolatile memory module 406. For example, after 1 millisecond (ms) has elapsed, the data threshold is added with an accumulated value (e.g., 100MB) to become 400 MB. After 2 ms, the threshold value is added to the accumulated value (e.g., 100MB) to become 500 MB. That is, after 2 ms has elapsed, the data threshold has been updated to 500MB, and the data amount of the write data temporarily stored in the buffer memory 510 has not been greater than the data threshold (500 ═ 500). Therefore, after the time for temporarily storing the write data in the buffer memory 510 is 2 milliseconds, the write data can be allowed to be transmitted to the rewritable nonvolatile memory module 406 for storage. Therefore, the effect of reducing the data transmission bandwidth of the memory storage device 10 to dissipate heat can be achieved.

It should be noted that the above-mentioned operation of reducing the data transmission bandwidth of the memory storage device 10 by comparing the write data with the data threshold is only an example of the cooling operation, and is not intended to limit the invention. In other exemplary embodiments not mentioned, any means for delaying the receiving of the write data, delaying the storing of the write data, reducing the bandwidth of the data received from the host system 11, and reducing the bandwidth for transmitting the data between the memory control circuit unit 404 and the rewritable non-volatile memory module 406 may be included in the operation of reducing the data transmission bandwidth of the memory storage device 10. For example, in an exemplary embodiment, by delaying the transmission of the completion information corresponding to a certain write data to the host system 11, the effect of reducing the bandwidth for receiving data from the host system 11 can also be achieved.

In an example embodiment, the operation of reducing the clock frequency of the memory storage device 10 may include reducing the clock frequency of the memory control circuit unit 404 and/or reducing the clock frequency of the rewritable nonvolatile memory module 406. The reducing the clock frequency of the rewritable nonvolatile memory module 406 may further include reducing the frequency of a clock signal used for programming the memory cell and/or reducing the frequency of a clock signal used for reading data from the memory cell. In addition, reducing the operating voltage of the memory storage device 10 may include reducing the voltage of the power supply of the memory control circuit unit 404 and/or reducing the voltage of the power supply of the rewritable nonvolatile memory module 406, which will not be described herein.

Referring to fig. 7, in the present exemplary embodiment, the threshold values Th1 and Th2 can be determined. The threshold value Th1 is also referred to as a first threshold value, and the threshold value Th2 is also referred to as a second threshold value. For example, the threshold Th1 may be 96 degrees celsius and the threshold Th2 may be 92 degrees celsius. Assume that at time point T1, the temperature value reaches the threshold value Th 1. Here, the temperature value reaching the threshold value Th1 means that the temperature value is equal to or greater than the threshold value Th 1. The cooling operation 701 is performed based on a certain cooling level corresponding to the temperature value reaching the threshold value Th 1. For example, the cooling operation 701 is performed based on a cooling level 1, and the current level parameter is set to 1.

After performing the temperature decreasing operation 701 based on the temperature decreasing level 1, the temperature value does not decrease to be less than the threshold value Th1 within the time range Δ T. Therefore, at time T2, cool down operation 702 is performed based on another cool down level that is higher. For example, cooling operation 702 may be performed based on cooling level 2 and level parameter 1 may be updated to level parameter 2 according to the current level parameter 1. After performing cool down operation 702 based on cool down level 2, the temperature value has not yet decreased to be less than threshold Th1 within time range Δ T. Therefore, at time T3, cool down operation 703 is performed based on another higher cool down level. For example, cooling operation 703 may be performed based on cooling level 3 and level parameter 2 may be updated to level parameter 3 according to the current level parameter 2.

After performing the cool down operation 703 based on the cool down level 3, the temperature value quickly falls below the threshold Th1 (e.g., falls below the threshold Th1 within the time range Δ T). Therefore, after time point T3, cool down operation 703 is continuously performed based on cool down level 3, so that the temperature value continues to decrease. At a time point T4, the temperature value reaches a threshold value Th 2. Here, the temperature value reaching the threshold value Th2 means that the temperature value is equal to or less than the threshold value Th 2. In response to the temperature value reaching the threshold value Th2, cooling operation 702 based on cooling level 2 is performed and level parameter 3 is updated to level parameter 2 according to the current level parameter 3.

After the time point T4, the temperature value may gradually rise. At time T5, if the temperature value reaches the threshold value Th1 again, the cooling level of the cooling operation may be increased again. For example, cooling operation 703 may be performed based on cooling level 3 and level parameter 2 may be updated to level parameter 3 according to the current level parameter 2. Then, if the temperature value again falls to the threshold value Th2, the temperature decrease level of the temperature decrease operation may be decreased again. For example, cooling operation 702 may be performed based on cooling level 2 and level parameter 3 may be updated to level parameter 2 according to the current level parameter 3. By analogy, after time T5, the temperature value may oscillate between the thresholds Th1 and Th2 and may gradually converge around the average of the thresholds Th1 and Th 2.

Referring to fig. 8, it is assumed that at time T1, the temperature value reaches the threshold value Th 1. Corresponding to the temperature value reaching the threshold value Th1, cooling operation 801 is performed based on a certain cooling level. In the present exemplary embodiment, the cooling operation 801 is performed based on the cooling level 0, and the current level parameter is set to 0. Note that cooling level 0 is the lowest cooling level. After performing the cool down operation 801 based on the cool down level 0, it is assumed that the temperature value quickly falls below the threshold value Th1 (e.g., falls below the threshold value Th1 within the time range Δ T). Therefore, after the time point T1, the cool down operation 801 is continuously performed based on the cool down level 0, so that the temperature value continues to decrease.

At a time point T2, the temperature value reaches a threshold value Th 2. The cooling operation may be stopped corresponding to the temperature value reaching the threshold value Th 2. After the cooling operation is stopped, the temperature value may gradually rise back. If the temperature value again reaches the threshold value Th1, cool down operation 801 may again be performed based on cool down level 0, and the current level parameter is set to 0. By analogy, the temperature value may continue to oscillate between the thresholds Th1 and Th2 and may gradually converge around the average of the thresholds Th1 and Th 2.

Referring to fig. 9, in the present exemplary embodiment, threshold values Th1, Th2 and Th3 may be determined. The threshold value Th3 is between the threshold values Th1 and Th 2. For example, the threshold Th3 may be an average or other value of the thresholds Th1 and Th 2. For example, the threshold values Th1, Th2 and Th3 may be respectively 96 degrees celsius, 92 degrees celsius and 94 degrees celsius. In the present exemplary embodiment, the threshold value Th1 is also referred to as a first threshold value, the threshold value Th2 is also referred to as a second threshold value, and the threshold value Th3 is also referred to as a third threshold value.

Assume that at time point T1, the temperature value reaches the threshold value Th 3. Here, the temperature value reaching the threshold value Th3 means that the temperature value is equal to or greater than the threshold value Th 3. The cooling operation 901 is performed based on a certain cooling level corresponding to the temperature value reaching the threshold value Th 3. In the exemplary embodiment, the threshold Th3 is used to initiate a cooling operation. Therefore, the cooling operation 901 is performed based on the cooling level 0 corresponding to the temperature value reaching the threshold value Th3, and the current level parameter is set to 0. However, in another exemplary embodiment, the cooling operation may be started before the temperature value reaches the threshold value Th3 (e.g., when the temperature value exceeds the threshold value Th2), and the invention is not limited thereto.

After performing the cooling operation 901 based on cooling level 0, if the temperature value continues to rise and reaches the threshold value Th1, the cooling operation 902 is performed based on another higher cooling level. For example, according to the current level parameter 0, the cooling operation 902 may be performed based on the cooling level 1 and the level parameter 0 may be updated to the level parameter 1. After performing the cool down operation 902 based on the cool down level 1, the temperature value does not drop below the threshold value Th1 within the time range Δ T. Therefore, after time T3, cool down operation 903 is performed based on another higher cool down level. For example, cooling operation 903 may be performed based on cooling level 2 and level parameter 1 may be updated to level parameter 2 according to the current level parameter 1.

After time T3, the temperature value quickly drops below threshold Th1 (e.g., drops below threshold Th1 over time Δ T). Therefore, the cool down operation 903 is continuously performed based on the cool down level 2, so that the temperature value is continuously decreased. At a time point T4, the temperature value reaches a threshold value Th 2. The cooling level of the cooling operation may be lowered corresponding to the temperature value reaching the threshold value Th 2. For example, depending on the current level parameter 2, the cooling operation 902 based on cooling level 1 may be re-performed and level parameter 2 may be updated to level parameter 1. After the time point T4, the temperature value may gradually rise.

At time T5, if the temperature value reaches the threshold value Th1 again, the cooling level of the cooling operation may be increased again. For example, cooling operation 903 may again be performed based on cooling level 2 and level parameter 1 may be updated to level parameter 2 according to the current level parameter 1. Then, at a time point T6, if the temperature value drops to the threshold value Th2 again, the cooling level of the cooling operation may be decreased again. For example, according to the current level parameter 2, the cooling operation 902 may be performed again based on the cooling level 1 and the level parameter 2 may be updated to the level parameter 1. By analogy, after time T6, the temperature value may oscillate between the thresholds Th1 and Th2 and may gradually converge around the average of the thresholds Th1 and Th2 (e.g., threshold Th 3).

Referring to fig. 10, it is assumed that at time T1, the temperature value reaches the threshold value Th 3. In response to the temperature value reaching the threshold value Th3, a cool down operation may be initiated. For example, the cooling operation 1001 may be performed based on a cooling level of 0, and the current level parameter is set to 0. However, in another exemplary embodiment, the cooling operation may be started before the temperature value reaches the threshold Th3, and the invention is not limited thereto.

After performing cooling operation 1001 based on cooling level 0, if the temperature value continues to rise and reaches threshold Th1, cooling operation 1002 is performed based on another higher cooling level. For example, according to the current level parameter 0, the cooling operation 1002 may be performed based on the cooling level 1 and the level parameter 0 may be updated to the level parameter 1. After performing the cooling operation 1002 based on the cooling level 1, the temperature value does not fall below the threshold value Th1 within the time range Δ T. Therefore, after time point T3, cool down operation 1003 would be performed based on another higher cool down level. For example, depending on the current level parameter 1, the cool down operation 1003 may be performed based on cool down level 2 and level parameter 1 may be updated to level parameter 2.

After time T3, the temperature value does not drop below threshold Th1 within time range Δ T despite the drop in temperature value. Therefore, after time T4, cool down operation 1004 is performed based on another higher cool down level. For example, cooling operation 1004 may be performed based on cooling level 3 and level parameter 2 may be updated to level parameter 3 according to the current level parameter 2.

After time T4, the temperature value quickly drops below threshold Th1 (e.g., drops below threshold Th1 over time Δ T). Accordingly, the cool down operation 1004 is continuously performed based on the cool down level 3, so that the temperature value is continuously decreased. At a time point T5, the temperature value reaches a threshold value Th 2. The cooling level of the cooling operation may be lowered corresponding to the temperature value reaching the threshold value Th 2. For example, a cool down operation 1003 based on cool down level 2 may be re-executed and level parameter 3 may be updated to level parameter 2 according to the current level parameter 3. After the time point T5, the temperature value may gradually rise.

At a time point T6, the temperature value reaches a threshold value Th 3. The cooling level of the cooling operation may be increased corresponding to the temperature value reaching the threshold value Th 3. For example, after time point T6, cooling operation 1004 may be performed based on cooling level 3 and level parameter 2 may be updated to level parameter 3 according to the current level parameter 2. Then, at a time point T7, if the temperature value drops to the threshold value Th2 again, the cooling level of the cooling operation may be decreased again. For example, depending on the current level parameter 3, the cool down operation 1003 may again be performed based on cool down level 2 and level parameter 3 may be updated to level parameter 2. By analogy, after time T7, the temperature value may oscillate between the thresholds Th2 and Th3 and may gradually converge around the average of the thresholds Th2 and Th 3.

It should be noted that in the exemplary embodiments of fig. 7-10, it is assumed that the temperature of the memory storage device 10 is only increased or decreased by the cooling operation, so that the temperature value gradually converges between the threshold values Th1 and Th2 (or threshold values Th2 and Th3) according to the cooling operation performed. In some exemplary embodiments not mentioned, if the external environment temperature drops, the memory storage device 10 stops performing data access operations or the memory storage device 10 enters an idle (idle) state, etc., the temperature of the memory storage device 10 may also drop naturally. In the case where the detected temperature value gradually decreases, the temperature decrease level employed for the temperature decrease operation may also gradually decrease or even the temperature decrease operation may stop. Alternatively, in an exemplary embodiment, if the temperature value is lower than another threshold (also referred to as a fourth threshold), the cooling operation may also be stopped directly. Wherein, the fourth threshold is smaller than the second threshold.

In the foregoing example embodiments of fig. 7 to 9, the threshold value Th1 is used as the trigger point for increasing the temperature-decreasing level of the temperature-decreasing operation, and the threshold value Th2 is used as the trigger point for decreasing the temperature-decreasing level of the temperature-decreasing operation. If the temperature value does not decrease below the threshold value Th1 within a time range (e.g., the time range Δ T), the cooling level of the cooling operation is increased by one step. Similarly, if the temperature value does not rise above the threshold value Th2 within a time range (e.g., time range Δ T), the cooling level of the cooling operation is decreased by one step. For example, in the exemplary embodiment of fig. 10, after the time point T7, if the temperature value does not rise above the threshold value Th2 (e.g., the temperature value continues to drop), the cooling level of the cooling operation is decreased by one step (e.g., from cooling level 2 to cooling level 1, or from cooling level 1 to cooling level 0) after a predetermined time period (e.g., the time period Δ T). If the cooling level is 0 and the temperature value continues to decrease (or the temperature value does not increase to the threshold value Th2), the cooling operation may be stopped.

In the foregoing example embodiment of fig. 9, the threshold value Th3 is used as the trigger point for starting the cooling operation, and after the cooling operation is started, the threshold values Th1 and Th2 are used as the trigger points for increasing and decreasing the cooling level of the cooling operation, respectively. However, in the foregoing example embodiment of fig. 10, the threshold value Th3 may be used as a trigger point for increasing the cooling level in addition to the trigger point for starting the cooling operation. Alternatively, in an exemplary embodiment not mentioned, the threshold Th3 may also be used as a trigger point for decreasing the cooling level of the cooling operation. For example, in the example embodiment in which the threshold value Th3 is used as the trigger point for decreasing the cooling level, the cooling level of the cooling operation may be decreased when the temperature value is lower than the threshold value Th 3.

In an exemplary embodiment, even if the temperature value decreases below the first threshold within the predetermined time range, the temperature reduction level of the temperature reduction operation is increased as long as the temperature value reaches the first threshold again. For example, in another example embodiment of fig. 7, after time point T3, cooling operation 703 is performed based on cooling level 3. However, after the time point T3, if the temperature value falls below the threshold value Th1 within a predetermined time range (e.g., the time range Δ T) and rises back above the threshold value Th1 before reaching the threshold value Th2, the cooling level of the cooling operation can be increased. For example, from cooling level 3 to cooling level 4. Alternatively, in another example embodiment of fig. 7, after time point T4, cooling operation 702 is performed based on cooling level 2. However, after the time point T4, if the temperature value rises back to exceed the threshold value Th2 within a predetermined time range (e.g., the time range Δ T) and falls back below the threshold value Th2 before reaching the threshold value Th1, the cooling level of the cooling operation can be decreased. For example, from cooling level 2 to cooling level 1.

It should be noted that, in the foregoing exemplary embodiment, each adjustment of the cooling level is performed by one level. However, in an exemplary embodiment, the cooling level may be increased by multiple steps at a time (e.g., increasing the cooling level from the cooling level 0 to the cooling level 3), and/or the cooling level may be decreased by multiple steps at a time (e.g., decreasing the cooling level from the cooling level 4 to the cooling level 2), which is not limited by the present invention.

In an example embodiment, the rate of rise of the temperature value may be detected. If the temperature value is increased at a rate higher than a predetermined rate (e.g., the temperature value is increased by a time unit higher than a predetermined amount), the temperature-decreasing level may be increased by a plurality of steps (e.g., 2 steps or 3 steps) at a time when it is determined that the temperature-decreasing level of the temperature-decreasing operation needs to be increased. In an exemplary embodiment, the level of temperature decrease may be increased by several levels according to the rate of temperature increase. If the temperature value rises at a higher rate, the single increase of the temperature reduction level is higher. In other words, a single increase in the cool down level may positively correlate to the rate of increase in the temperature value.

In an example embodiment, the rate of decrease of the temperature value may also be detected. If the falling rate of the temperature value is higher than a predetermined rate (for example, the falling amplitude of the temperature value in a time unit is higher than a predetermined amplitude), when it is determined that the cooling level of the cooling operation needs to be lowered, the cooling level may be lowered by multiple steps (for example, 2 steps or 3 steps) at a time. In an exemplary embodiment, the temperature reduction level is decreased by several levels, or the temperature reduction level is determined according to the rate of decrease of the temperature value. If the falling rate of the temperature value is higher, the single falling amplitude of the temperature reduction level is also higher. In other words, the magnitude of the single decrease in the temperature decrease level may positively correlate to the rate of decrease in the temperature value.

It should be noted that the foregoing exemplary embodiments provide various cooling level adjustment mechanisms and implementation details for cooling operation, but the invention is not limited thereto. In some exemplary embodiments not mentioned, it is within the scope of the present invention that a certain cooling operation is not a fixed level determined according to a temperature value currently within a predetermined temperature range, and/or that the cooling level of a certain cooling operation is increased or decreased according to a comparison result of the temperature value and a single threshold value.

Referring to fig. 11, in step S1101, a temperature is sensed by a temperature sensor and a temperature value is obtained. In step S1102, it is determined whether a cooling operation has been performed (or initiated). If the cooling operation is performed (or started), the process proceeds to step S1105. If the cooling operation is not performed (or started), in step S1103, it is determined whether the temperature value is equal to or greater than the third threshold value. If the temperature value is not equal to or greater than the third threshold value, the process returns to step S1101. If the temperature value is equal to or greater than the third threshold value, in step S1104, a cooling operation is performed (or initiated).

In step S1105, it is determined whether the temperature value is equal to or greater than a first threshold value. If the temperature value is equal to or greater than the first threshold value, in step S1106, the cooling level of the cooling operation is increased to increase the cooling capability of the cooling operation. After step S1106, the process returns to step S1101. If the temperature value is not equal to or greater than the first threshold value, in step S1107, it is determined whether the temperature value is equal to or less than the second threshold value. If the temperature value is equal to or less than the second threshold value, in step S1108, the cooling level of the cooling operation is decreased to decrease the cooling capacity of the cooling operation. After step S1108, the process returns to step S1101. If no in step S1107, the process returns to step S1101.

However, the steps in fig. 11 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 11 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 11 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto. For example, steps S1101 to S1108 can be executed by the memory management circuit 502 or the memory control circuit unit 404 in fig. 5.

In summary, when it is determined that the temperature reduction operation is required to reduce the temperature of the memory storage device, the temperature reduction level of the temperature reduction operation is not a fixed level determined according to the current temperature value within a predetermined temperature range, but is determined to be increased or decreased according to the comparison result between the measured temperature value and at least one threshold value. Therefore, the cooling level of the performed cooling operation can be dynamically determined in the temperature interval defined by the first threshold and the second threshold, thereby achieving a balance between the cooling capability and the system performance of the memory storage device.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A temperature control method is used for a memory control circuit unit, wherein the memory control circuit unit is used for controlling a rewritable nonvolatile memory module, and the temperature control method comprises the following steps:

sensing a temperature via a temperature sensor and obtaining a temperature value;

if the temperature value reaches a first threshold value, executing a cooling operation based on a first cooling grade, and updating a grade parameter into a first grade parameter, wherein the first grade parameter corresponds to the first cooling grade;

after the temperature reduction operation is executed based on the first temperature reduction level, if the temperature value is not reduced to be smaller than the first threshold value within a first time range, changing to execute the temperature reduction operation based on a second temperature reduction level according to the first level parameter, and updating the level parameter from the first level parameter to a second level parameter, wherein the second level parameter corresponds to the second temperature reduction level,

wherein the cooling capacity of the cooling operation performed based on the second cooling level is higher than the cooling capacity of the cooling operation performed based on the first cooling level; and

after the cooling operation is executed based on the second cooling level, if the temperature value is reduced to be smaller than the first threshold value in a second time range and the temperature value reaches a second threshold value, the cooling operation is executed based on the first cooling level according to the second level parameter, and the level parameter is updated from the second level parameter to the first level parameter,

after performing the cooling operation based on the first cooling level, if the temperature value decreases to be less than the second threshold value within a third time range and does not increase to be higher than the second threshold value within a fourth time range, changing to perform the cooling operation based on a fourth cooling level according to the first level parameter and updating the level parameter from the first level parameter to a fourth level parameter,

wherein the cooling capacity of the cooling operation performed based on the first cooling level is higher than the cooling capacity of the cooling operation performed based on the fourth cooling level,

wherein the second threshold is less than the first threshold.

2. The temperature control method of claim 1, further comprising:

after the cooling operation is executed based on the second cooling level, if the temperature value is reduced to be smaller than the first threshold value within the second time range and the temperature value does not reach the second threshold value, the cooling operation is continuously executed based on the second cooling level.

3. The temperature control method of claim 1, further comprising:

after the cooling operation is performed based on the second cooling level, if the temperature value decreases to be less than the first threshold value within the second time range and the temperature value increases back to the first threshold value, changing to perform the cooling operation based on a third cooling level according to the second level parameter, and updating the level parameter from the second level parameter to a third level parameter, where the third level parameter corresponds to the third cooling level,

wherein a cooling capacity of the cooling operation performed based on the third cooling level is higher than the cooling capacity of the cooling operation performed based on the second cooling level.

4. The temperature control method of claim 1, further comprising:

after the cooling operation is executed based on the first cooling grade, if the temperature value is reduced to be smaller than the first threshold value within the first time range and the temperature value does not reach the second threshold value, the cooling operation is continuously executed based on the first cooling grade.

5. The temperature control method of claim 1, further comprising:

before the cooling operation is executed based on the first cooling grade, if the temperature value reaches a third threshold value, executing the cooling operation based on an initial cooling grade, and updating the grade parameter to an initial grade parameter, wherein the initial grade parameter corresponds to the initial cooling grade,

wherein the third threshold is between the first threshold and the second threshold.

6. The temperature control method according to claim 1, wherein the cooling operation includes:

and determining whether to indicate to write the written data into the rewritable nonvolatile memory module according to whether the data volume of the written data is larger than a data threshold value.

7. The temperature control method according to claim 6, wherein the step of determining whether to instruct writing of the write data to the rewritable non-volatile memory module according to whether the data amount of the write data is greater than the data threshold value comprises:

if the data volume of the written data is larger than the data threshold value, temporarily indicating that the written data is written into the rewritable nonvolatile memory module;

dynamically updating the data threshold value; and

and if the data volume of the written data is not larger than the data threshold value, indicating that the written data is written into the rewritable nonvolatile memory module.

8. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module;

a temperature sensor; and

a memory control circuit unit connected to the connection interface unit, the rewritable nonvolatile memory module, and the temperature sensor,

wherein the memory control circuit unit is used for sensing temperature through the temperature sensor and obtaining a temperature value,

wherein if the temperature value reaches a first threshold value, the memory control circuit unit is further configured to perform a cooling operation based on a first cooling level and update a level parameter to a first level parameter, wherein the first level parameter corresponds to the first cooling level,

wherein after performing the cooling operation based on the first cooling level, if the temperature value is not decreased to be less than the first threshold value within a first time range, the memory control circuit unit is further configured to change to perform the cooling operation based on a second cooling level according to the first level parameter and update the level parameter from the first level parameter to a second level parameter, wherein the second level parameter corresponds to the second cooling level,

wherein the cooling capacity of the cooling operation performed based on the second cooling level is higher than the cooling capacity of the cooling operation performed based on the first cooling level,

wherein after the temperature reduction operation is performed based on the second temperature reduction level, if the temperature value is reduced to be less than the first threshold value within a second time range and the temperature value reaches a second threshold value, the memory control circuit unit is configured to revert to performing the temperature reduction operation based on the first temperature reduction level according to the second level parameter and update the level parameter from the second level parameter to the first level parameter,

wherein the second threshold is less than the first threshold.

9. The memory storage device of claim 8, wherein after performing the cooling operation based on the second cooling level, if the temperature value decreases to be less than the first threshold value within the second time range and the temperature value does not reach the second threshold value, the memory control circuit unit is further configured to continue performing the cooling operation based on the second cooling level.

10. The memory storage device of claim 8, wherein after performing the cooling operation based on the second cooling level, if the temperature value decreases to less than the first threshold value within the second time range and the temperature value increases back to the first threshold value, the memory control circuit unit is further configured to change to perform the cooling operation based on a third cooling level and update the level parameter from the second level parameter to a third level parameter according to the second level parameter, wherein the third level parameter corresponds to the third cooling level,

11. The memory storage device of claim 8, wherein after performing the cooling operation based on the first cooling level, the memory control circuitry is further configured to continue performing the cooling operation based on the first cooling level if the temperature value decreases to less than the first threshold value within the first time range and the temperature value does not reach the second threshold value.

12. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to perform the cooling operation based on an initial cooling level and update the level parameter to an initial level parameter if the temperature value reaches a third threshold value before performing the cooling operation based on the first cooling level, wherein the initial level parameter corresponds to the initial cooling level,

13. The memory storage device of claim 8, wherein in the cooling operation, the memory control circuit unit is further configured to determine whether to instruct writing of the write data to the rewritable non-volatile memory module according to whether a data amount of the write data is greater than a data threshold.

14. The memory storage device of claim 13, wherein the operation of the memory control circuit unit determining whether to instruct writing of the write data to the rewritable non-volatile memory module according to whether the data amount of the write data is greater than the data threshold value comprises:

dynamically updating the data threshold value; and

15. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for connecting to a host system;

a memory interface for connecting to the rewritable nonvolatile memory module;

a temperature sensor; and

a memory management circuit connected to the host interface, the memory interface, and the temperature sensor,

wherein the memory management circuitry is to sense a temperature via the temperature sensor and obtain a temperature value,

wherein if the temperature value reaches a first threshold value, the memory management circuit is further configured to perform a cooling operation based on a first cooling level and update a level parameter to a first level parameter, wherein the first level parameter corresponds to the first cooling level,

wherein after performing the cooling operation based on the first cooling level, if the temperature value is not decreased to be less than the first threshold value within a first time range, the memory management circuit is further configured to change to perform the cooling operation based on a second cooling level according to the first level parameter and update the level parameter from the first level parameter to a second level parameter, wherein the second level parameter corresponds to the second cooling level,

wherein after performing the cooling operation based on the second cooling level, if the temperature value decreases to be less than the first threshold value within a second time range and the temperature value reaches a second threshold value, the memory management circuit is configured to revert to performing the cooling operation based on the first cooling level according to the second level parameter and update the level parameter from the second level parameter to the first level parameter,

wherein the second threshold is less than the first threshold.

16. The memory control circuit unit of claim 15, wherein after the cooling operation is performed based on the second cooling level, if the temperature value decreases to be less than the first threshold value within the second time range and the temperature value does not reach the second threshold value, the memory management circuit is further configured to continue to perform the cooling operation based on the second cooling level.

17. The memory control circuit unit of claim 15, wherein after performing the cooling operation based on the second cooling level, if the temperature value decreases to be less than the first threshold value within the second time range and the temperature value increases back to the first threshold value, the memory management circuit is further configured to change to perform the cooling operation based on a third cooling level and update the level parameter from the second level parameter to a third level parameter according to the second level parameter, wherein the third level parameter corresponds to the third cooling level,

18. The memory control circuit unit of claim 15, wherein after the cooling operation is performed based on the first cooling level, if the temperature value decreases to be less than the first threshold value within the first time range and the temperature value does not reach the second threshold value, the memory management circuit is further configured to continue to perform the cooling operation based on the first cooling level.

19. The memory control circuit unit of claim 15, wherein before performing the cooling operation based on the first cooling level, if the temperature value reaches a third threshold value, the memory management circuit is further configured to perform the cooling operation based on an initial cooling level and update the level parameter to an initial level parameter, wherein the initial level parameter corresponds to the initial cooling level,

20. The memory control circuit unit of claim 15, wherein in the cooling operation, the memory management circuit is further configured to determine whether to instruct writing of the write data to the rewritable non-volatile memory module according to whether a data amount of the write data is greater than a data threshold.

21. The memory control circuit unit of claim 20, wherein the operation of the memory management circuit determining whether to instruct writing of the write data to the rewritable non-volatile memory module according to whether the data amount of the write data is greater than the data threshold value comprises:

dynamically updating the data threshold value; and