CN113724773B - Memory management method, memory storage device and memory control circuit unit - Google Patents

Memory management method, memory storage device and memory control circuit unit Download PDF

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Publication number
CN113724773B
CN113724773B CN202111076097.0A CN202111076097A CN113724773B CN 113724773 B CN113724773 B CN 113724773B CN 202111076097 A CN202111076097 A CN 202111076097A CN 113724773 B CN113724773 B CN 113724773B
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temperature state
unit
data
temperature
memory
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CN113724773A (en
Inventor
简佳帆
林纬
许祐诚
杨宇翔
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C2029/1802—Address decoder
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The method comprises the following steps: detecting a first temperature state of the rewritable nonvolatile memory module; performing a first write operation on the first physical unit in a first temperature state to store first data into the first physical unit; detecting a second temperature state of the rewritable non-volatile memory module after performing the first write operation; and responding to the first temperature state and the second temperature state to meet the first condition, and executing data refreshing operation on the first entity unit under the second temperature state so as to restore the first data to the second entity unit, wherein the second entity unit is different from the first entity unit. Therefore, the reliability of the rewritable nonvolatile memory module in data access under the environment with severe temperature change can be improved.

Description

Memory management method, memory storage device and memory control circuit unit
Technical Field
The present invention relates to a memory management technology, and more particularly, to a memory management method, a memory storage device, and a memory control circuit unit.
Background
Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable electronic devices.
The memory cells in the rewritable nonvolatile memory module store data in the form of voltages. For example, by applying a write voltage to the memory cell to store data and/or by applying a read voltage to the memory cell to read data. However, if the temperature difference between reading and writing to a certain memory cell is too large, the error occurrence rate of data read from the memory cell later is likely to be greatly increased.
Disclosure of Invention
The invention provides a memory management method, a memory storage device and a memory control circuit unit, which can improve the reliability when data access is performed on a rewritable nonvolatile memory module under the environment of severe temperature change.
Exemplary embodiments of the present invention provide a memory management method for a memory storage device. The memory storage device includes a rewritable non-volatile memory module. The rewritable nonvolatile memory module includes a plurality of physical units. The memory management method comprises the following steps: detecting a first temperature state of the rewritable non-volatile memory module; performing a first write operation on a first entity unit of the plurality of entity units in the first temperature state to store first data into the first entity unit; detecting a second temperature state of the rewritable non-volatile memory module after performing the first write operation; and responsive to the first temperature state and the second temperature state meeting a first condition, performing a data refresh operation on the first entity unit in the second temperature state to restore the first data to a second entity unit of the plurality of entity units, wherein the second entity unit is different from the first entity unit.
In an exemplary embodiment of the present invention, the memory management method further includes: obtaining a trigger threshold corresponding to the first temperature state; obtaining a temperature value of the rewritable non-volatile memory module in the second temperature state; comparing the trigger threshold value with the temperature value; and judging whether the first temperature state and the second temperature state accord with the first condition according to the comparison result.
In an exemplary embodiment of the present invention, the memory management method further includes: obtaining first temperature state identification information corresponding to the first temperature state; obtaining second temperature state identification information corresponding to the second temperature state; performing a logic operation on the first temperature state identification information and the second temperature state identification information; and judging whether the first temperature state and the second temperature state accord with the first condition according to the execution result of the logic operation.
In an example embodiment of the present invention, the step of detecting the second temperature state of the rewritable nonvolatile memory module includes: receiving a write instruction from a host system; and responding to the writing instruction to judge whether the first temperature state and the second temperature state accord with the first condition.
In an exemplary embodiment of the present invention, the memory management method further includes: responsive to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit in the second temperature state to store second data indicated by the write instruction into the second physical unit; and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
In an exemplary embodiment of the present invention, the memory management method further includes: performing a second write operation on the first entity unit in the second temperature state to store second data indicated by the write instruction into the first entity unit; and in the data refreshing operation, the first data and the second data are read out from the first entity unit and stored into the second entity unit together.
In an exemplary embodiment of the present invention, the memory management method further includes: recording temperature state identification information corresponding to the first entity unit according to the first temperature state; in response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
In an exemplary embodiment of the present invention, the memory management method further includes: in the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first physical unit using a first electrical parameter; and in the second temperature state, instructing the rewritable nonvolatile memory module to program the at least one memory cell by using a second electrical parameter, wherein the first electrical parameter is different from the second electrical parameter.
The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for detecting a first temperature state of the rewritable nonvolatile memory module. The memory control circuit unit is further configured to perform a first write operation on a first physical unit of the plurality of physical units in the first temperature state to store first data into the first physical unit. After performing the first write operation, the memory control circuit unit is further configured to detect a second temperature state of the rewritable non-volatile memory module. In response to the first temperature state and the second temperature state meeting a first condition, the memory control circuit unit is further configured to perform a data refresh operation on the first physical unit in the second temperature state to restore the first data to a second physical unit of the plurality of physical units, wherein the second physical unit is different from the first physical unit.
In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: obtaining a trigger threshold corresponding to the first temperature state; obtaining a temperature value of the rewritable non-volatile memory module in the second temperature state; comparing the trigger threshold value with the temperature value; and judging whether the first temperature state and the second temperature state accord with the first condition according to the comparison result.
In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: obtaining first temperature state identification information corresponding to the first temperature state; obtaining second temperature state identification information corresponding to the second temperature state; performing a logic operation on the first temperature state identification information and the second temperature state identification information; and judging whether the first temperature state and the second temperature state accord with the first condition according to the execution result of the logic operation.
In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: responsive to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit in the second temperature state to store second data indicated by the write instruction into the second physical unit; and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: performing a second write operation on the first entity unit in the second temperature state to store second data indicated by the write instruction into the first entity unit; and in the data refreshing operation, instructing the rewritable nonvolatile memory module to read the first data together with the second data from the first entity unit and store the first data together with the second data into the second entity unit.
In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: recording temperature state identification information corresponding to the first entity unit according to the first temperature state; in response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: in the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first physical unit using a first electrical parameter; and in the second temperature state, instructing the rewritable nonvolatile memory module to program the at least one memory cell by using a second electrical parameter, wherein the first electrical parameter is different from the second electrical parameter.
The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory control circuit unit is used for detecting a first temperature state of the rewritable nonvolatile memory module. The memory management circuit is further configured to perform a first write operation on a first physical unit of the plurality of physical units in the first temperature state to store first data into the first physical unit. After performing the first write operation, the memory management circuit is further configured to detect a second temperature state of the rewritable non-volatile memory module. In response to the first temperature state and the second temperature state meeting a first condition, the memory management circuit is further configured to perform a data refresh operation on the first physical unit in the second temperature state to restore the first data to a second physical unit of the plurality of physical units, wherein the second physical unit is different from the first physical unit.
In an exemplary embodiment of the present invention, the first condition includes that a temperature difference value between a temperature value corresponding to the first temperature state and a temperature value corresponding to the second temperature state reaches a threshold value or falls within a specific range of values.
In an exemplary embodiment of the present invention, the memory management circuit is further configured to: obtaining a trigger threshold corresponding to the first temperature state; obtaining a temperature value of the rewritable non-volatile memory module in the second temperature state; comparing the trigger threshold value with the temperature value; and judging whether the first temperature state and the second temperature state accord with the first condition according to the comparison result.
In an exemplary embodiment of the present invention, the memory management circuit is further configured to: obtaining first temperature state identification information corresponding to the first temperature state; obtaining second temperature state identification information corresponding to the second temperature state; performing a logic operation on the first temperature state identification information and the second temperature state identification information; and judging whether the first temperature state and the second temperature state accord with the first condition according to the execution result of the logic operation.
In an example embodiment of the present invention, detecting the second temperature state of the rewritable non-volatile memory module comprises: receiving a write instruction from a host system; and responding to the writing instruction to judge whether the first temperature state and the second temperature state accord with the first condition.
In an exemplary embodiment of the present invention, the memory management circuit is further configured to: responsive to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit in the second temperature state to store second data indicated by the write instruction into the second physical unit; and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
In an exemplary embodiment of the present invention, the memory management circuit is further configured to: performing a second write operation on the first entity unit in the second temperature state to store second data indicated by the write instruction into the first entity unit; and in the data refreshing operation, instructing the rewritable nonvolatile memory module to read the first data together with the second data from the first entity unit and store the first data together with the second data into the second entity unit.
In an exemplary embodiment of the present invention, the memory management circuit is further configured to: recording temperature state identification information corresponding to the first entity unit according to the first temperature state; in response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
In an exemplary embodiment of the present invention, the memory management circuit is further configured to: in the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first physical unit using a first electrical parameter; and in the second temperature state, instructing the rewritable nonvolatile memory module to program the at least one memory cell by using a second electrical parameter, wherein the first electrical parameter is different from the second electrical parameter.
Based on the above, after performing a first write operation on the first physical unit to store the first data in the first temperature state of the rewritable nonvolatile memory module, the second temperature state of the rewritable nonvolatile memory module may be detected. In response to the first temperature state and the second temperature state meeting a first condition, a data refresh operation may be performed on the first physical unit in the second temperature state to restore the first data to a second physical unit different from the first physical unit. Therefore, the reliability of the rewritable nonvolatile memory module in data access under the environment with severe temperature change can be improved.
Drawings
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;
FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;
FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;
FIG. 7 is a schematic diagram of a first write operation shown in accordance with an example embodiment of the invention;
FIG. 8 is a schematic diagram of a data refresh operation shown in accordance with an exemplary embodiment of the present invention;
FIG. 9 is a schematic diagram of a data refresh operation and a second write operation according to an example embodiment of the invention;
FIG. 10 is a schematic diagram of a third write operation shown in accordance with an example embodiment of the invention;
FIG. 11 is a schematic diagram showing the triggering or non-triggering of a data refresh operation at different temperature change states, according to an example embodiment of the present invention;
FIG. 12 is a schematic diagram showing the triggering or non-triggering of a data refresh operation at different temperature change states, according to an example embodiment of the present invention;
fig. 13 is a flowchart of a memory management method according to an exemplary embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.
In an example embodiment, host system 11 may be coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.
In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by a wired or wireless connection through the data transmission interface 114.
In an example embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless fidelity (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.
In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.
FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to the motherboard of the host system.
Fig. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.
The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the PCI Express (Peripheral Component Interconnect Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may be a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) compliant standard, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.
The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.
The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.
In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is the lower physical program cell and the most significant bit (Most Significant Bit, MSB) of a memory cell is the upper physical program cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.
In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data byte area includes 32 physical sectors, and one physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, the data bit region may also include 8, 16 or a greater or lesser number of physical sectors, and the size of each physical sector may also be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).
Fig. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.
The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 51 is explained as follows, which is equivalent to the explanation of the operation of the memory control circuit unit 42.
In an example embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.
In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 51. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.
In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.
The host interface 52 is connected to the memory management circuit 51. Memory management circuitry 51 may communicate with host system 11 through host interface 52. The host interface 52 is used to receive and identify the commands and data transmitted by the host system 11. For example, instructions and data transmitted by host system 11 may be transmitted to memory management circuit 51 via host interface 52. In addition, the memory management circuitry 51 may communicate data to the host system 11 through the host interface 52. In the present example embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.
The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 is to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read command sequence includes information such as the read identification code and the memory address.
In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.
The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code. For example, the error checking and correction circuit 54 may support various encoding/decoding algorithms such as low density parity check codes (Low Density Parity Check code, LDPC codes) or BCH.
The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.
In an example embodiment, the memory control circuit unit 42 further includes a temperature sensor 57. The temperature sensor 57 is connected to the memory management circuit 51. The temperature sensor 57 is used for sensing the ambient temperature and providing a corresponding temperature value. In an example embodiment, the memory management circuit 51 may obtain the temperature status of the current rewritable nonvolatile memory module 43 according to the temperature value provided by the temperature sensor 57. This temperature state may be expressed in terms of a specific state parameter or directly in terms of a temperature value, the invention is not limited. In addition, the temperature sensor 57 may be provided inside or outside the memory control circuit unit 42, and the present invention is not limited.
In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of fig. 5 may include a flash memory management circuit.
FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602. One physical unit refers to one Virtual Block (VB). A virtual block may include a plurality of physical programming units. For example, a dummy block may include one or more physically erased cells.
The physical units 610 (0) -610 (a) in the storage area 601 are configured to store user data (e.g., user data from the host system 11 of fig. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).
The memory management circuit 51 may configure the logic units 612 (0) through 612 (C) to map the physical units 610 (0) through 610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units.
It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is mapped by a certain logic unit, the data stored in the entity unit currently contains valid data. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit does not contain any valid data.
The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.
In an example embodiment, the memory management circuit 51 may detect and record a temperature state (also referred to as a first temperature state) of a certain physical unit (also referred to as a first physical unit) in the rewritable nonvolatile memory module 43 when the physical unit is programmed to store data (also referred to as first data). Thereafter, in response to the current temperature state (also referred to as the second temperature state) of the rewritable nonvolatile memory module 43 and the first temperature state meeting a specific condition (also referred to as the first condition), the memory management circuit 51 may perform a data refresh (data refresh) operation on the first physical unit. Then, in the second temperature state (or other temperature states), when the first data is read from the second entity unit, since the temperature state when the first data is programmed to the second entity unit is the same as or similar to the temperature state when the first data is read from the second entity unit, the total number of error bits generated due to the excessive read-write temperature difference in the read first data can be reduced. Therefore, the data reliability of the rewritable nonvolatile memory module can be improved when the data access is performed under the environment with severe temperature change.
Fig. 7 is a schematic diagram of a first write operation according to an example embodiment of the invention. Referring to fig. 7, the memory management circuit 51 may set the physical unit 71 (i.e. the first physical unit) as an on unit (also referred to as an on block) to receive new data from the host system 11. For example, the entity unit 71 may be selected from the entity units 610 (a+1) to 610 (B) of fig. 6. On the other hand, the memory management circuit 51 may detect a temperature state (i.e., a first temperature state) of the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may receive the temperature value 710 from the temperature sensor 57. The temperature value 710 may reflect the ambient temperature sensed by the temperature sensor 57 at a point in time (also referred to as a first point in time). The memory management circuit 51 may obtain a first temperature state based on the temperature value 710.
In the first temperature state, the memory management circuit 51 may receive a write instruction 701 from the host system 11. The write instruction 701 may indicate stored data 702 (i.e., first data). For example, write instruction 701 may instruct to store data 702 to a particular logical unit. After receiving the write command 701, in the first temperature state, the memory management circuit 51 may perform a write operation (also referred to as a first write operation) on the physical unit 71. The first write operation may be used to store the data 702 indicated by the write instruction 701 into the physical unit 71. For example, the memory management circuit 51 may send at least one write command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to store the data 702 in the physical unit 71 in the first temperature state.
Corresponding to storing the data 702 to the entity unit 71, the memory management circuit 51 may update the table information 700. The table information 700 may be used to record the temperature status of at least one physical unit in the rewritable nonvolatile memory module 43 when it was last programmed. For example, the temperature state may be represented by temperature state identification information and recorded in the table information 700. The temperature state identification information may have different parameter values at different temperature states.
In an example embodiment of fig. 7, the memory management circuit 51 may update the temperature status identification information corresponding to the entity unit 71 in the table information 700 to the parameter value "101". The parameter 101 may be determined according to the temperature 710 and reflect the temperature state (i.e., the first temperature state) of the physical unit 71 when it is programmed to store the data 702. It should be noted that in another exemplary embodiment, the first temperature state may be represented by other parameter values or directly by the temperature value 710, which is not a limitation of the present invention.
Fig. 8 is a schematic diagram of a data refresh operation according to an example embodiment of the present invention. Referring to fig. 8, following the example embodiment of fig. 7, after performing the first write operation, the memory management circuit 51 may detect another temperature state (i.e., a second temperature state) of the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may receive the temperature value 810 from the temperature sensor 57. The temperature value 810 may reflect the ambient temperature sensed by the temperature sensor 57 at a point in time (also referred to as a second point in time). The second point in time is later than the first point in time. Between the first point in time and the second point in time, the temperature state of the rewritable non-volatile memory module 43 may change, for example, from a first temperature state to a second temperature state. The memory management circuit 51 may obtain a second temperature state based on the temperature value 810.
In an exemplary embodiment, the memory management circuit 51 may determine whether the first temperature state and the second temperature state meet a specific condition (i.e., the first condition). For example, the first condition may include that a temperature difference between a temperature value corresponding to the first temperature state (e.g., temperature value 710 of fig. 7) and a temperature value corresponding to the second temperature state (e.g., temperature value 810 of fig. 8) reaches a threshold value or that the temperature difference falls within a specific range of values.
In an exemplary embodiment, if the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state reaches a threshold value, the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition. For example, the threshold may be 70 degrees. If the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state reaches 70 degrees, the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition. It should be noted that the threshold value can be adjusted according to practical requirements, and the present invention is not limited thereto.
In an exemplary embodiment, if the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state falls within a specific value range, the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition. For example, this particular range of values may be between 60 degrees and 80 degrees. If the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state falls between 60 degrees and 80 degrees, the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition. It should be noted that the specific numerical range may be adjusted according to practical requirements, and the present invention is not limited thereto.
In an exemplary embodiment of fig. 8, it is assumed that the first temperature state and the second temperature state meet the first condition. In response to the first temperature state and the second temperature state meeting the first condition, the memory management circuit 51 may perform a data refresh operation on the physical unit 71 in the second temperature state. The data refresh operation is used to restore the data 702 previously stored in the physical unit 71 in the first temperature state to the physical unit 81 (i.e. the second physical unit) in the second temperature state. For example, the entity unit 81 may be selected from the entity units 610 (a+1) to 610 (B) of fig. 6, and the entity unit 81 is different from the entity unit 71. For example, the memory management circuit 51 may send at least one read command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to read the data 702 from the physical unit 71 in the second temperature state. The memory management circuit 51 may then send at least one write command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to restore the read data 702 to the physical unit 81 in the second temperature state.
Corresponding to the data refresh operation, the memory management circuit 51 may update the table information 700. For example, according to the temperature value 810, the memory management circuit 51 may update the temperature status identification information corresponding to the entity unit 81 in the table information 700 to the parameter value "010" to reflect the temperature status (i.e. the second temperature status) when the entity unit 81 is programmed to store the data 702. It should be noted that in another exemplary embodiment, the second temperature state may be represented by other parameter values or directly by the temperature value 810, which is not a limitation of the present invention.
In an example embodiment, the memory management circuit 51 may reset (reset) the temperature state identification information corresponding to the physical unit 71 corresponding to the data refresh operation. For example, the memory management circuit 51 may reset the temperature state identification information corresponding to the entity unit 71 in the table information 700 to the parameter value "000". Thereafter, the memory management circuit 51 may re-associate the physical unit 71 to the idle region 602 of FIG. 6 and may erase the physical unit 71.
In an example embodiment, a particular temperature state may correspond to a particular temperature range. For example, when the temperature of the rewritable nonvolatile memory module 43 falls within a certain temperature range, the memory management circuit 51 may determine the temperature state of the rewritable nonvolatile memory module 43 corresponding to the temperature range. Furthermore, different temperature states may correspond to different temperature ranges. For example, the first temperature state may correspond to a first temperature range and the second temperature state may correspond to a second temperature range. In an example embodiment, the data refresh operation may include re-storing all or part of the data in the first physical unit to the second physical unit, and the data re-stored to the second physical unit may include data previously stored into the first physical unit in one or more temperature states.
In the example embodiment of fig. 7, data 702 is stored or programmed into physical unit 71 in a first temperature state. During the time that the data 702 is stored in the physical unit 71, the temperature state of the rewritable nonvolatile memory module 43 is changed from the first temperature state to the second temperature state. That is, the temperature of the rewritable nonvolatile memory module 43 may gradually rise or fall while going from the previous temperature range to another temperature range, even further to the other temperature range. In an example embodiment of fig. 7, after the temperature state of the rewritable nonvolatile memory module 43 is changed to the second temperature state, if the data refresh operation is not performed, more errors may be entrained in the data 702 read from the physical unit 71 as the temperature of the rewritable nonvolatile memory module 43 is continuously changed (e.g. continuously increased or decreased). Such errors may reduce the efficiency of subsequent decoding of the data 702 and may even result in failure of the decoding of the data 702.
In an example embodiment of fig. 8, the memory management circuit 51 may perform the data refresh operation on the physical unit 71 as soon as possible when the temperature state of the rewritable nonvolatile memory module 43 enters the second temperature state, so as to restore the data 702 to the physical unit 81 in the second temperature state. At this time, there is a high probability that errors in the data 702 read from the physical unit 71 in the second temperature state are still in a controllable or acceptable state, so that the data 702 can be successfully decoded (e.g. all errors in the data 702 can be successfully corrected). After the data 702 is restored to the physical unit 81, the temperature of the rewritable nonvolatile memory module 43 may continuously rise or fall, even into another temperature range (also referred to as a third temperature range). In the temperature state corresponding to the third temperature range (also referred to as the third temperature state), errors in the data 702 read from the physical unit 81 may be more easily corrected compared to the data 702 read from the physical unit 71, so that the decoding efficiency of the data 702 is improved. Thus, the data reliability of the rewritable nonvolatile memory module 43 can be effectively improved when the data is accessed in an environment with a severe temperature change.
In an example embodiment, the data refresh operation may be triggered by a write instruction from the host system 11. For example, in an example embodiment, the memory management circuitry 51 may receive a write instruction from the host system 11. The memory management circuit 51 can determine whether the first temperature state and the second temperature state meet the first condition according to the writing instruction, so as to determine whether to execute the data refresh operation. In an exemplary embodiment, the data refresh operation may be performed while the memory storage device 10 is in an idle state, before power-off, after power-on, or at any time, and the present invention is not limited thereto.
Fig. 9 is a schematic diagram of a data refresh operation and a second write operation according to an example embodiment of the invention. Referring to fig. 9, following the example embodiment of fig. 7, after performing the first write operation, the memory management circuit 51 may detect the second temperature state of the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may receive the temperature value 910 from the temperature sensor 57. The temperature value 910 may reflect the ambient temperature sensed by the temperature sensor 57 at the second point in time. The second point in time is later than the first point in time. The memory management circuit 51 may obtain a second temperature state based on the temperature value 910.
Near the second point in time, the memory management circuit 51 may receive a write instruction 901 from the host system 11. The write instruction 901 may indicate that data 902 (also referred to as second data) is stored. For example, write instruction 901 may instruct to store data 902 to a particular logical unit. In response to receiving the write command 901, the memory management circuit 51 may determine whether the first temperature state and the second temperature state meet the first condition.
In the exemplary embodiment of fig. 9, it is assumed that the first temperature state and the second temperature state meet the first condition. In response to the first temperature state and the second temperature state meeting the first condition, the memory management circuit 51 may perform a data refresh operation on the physical unit 71 in the second temperature state. For example, in a data refresh operation, the memory management circuit 51 may send at least one read command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to read the data 702 from the physical unit 71 in the second temperature state. The memory management circuit 51 may then send at least one write command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to restore the read data 702 to the physical unit 91 (i.e. the second physical unit) in the second temperature state. For example, the entity unit 91 may be selected from the entity units 610 (a+1) to 610 (B) of fig. 6, and the entity unit 91 is different from the entity unit 71. Further, the memory management circuit 51 may update the table information 700 corresponding to the data refresh operation. For example, the memory management circuit 51 may reset the temperature status identification information corresponding to the entity unit 71. For example, the memory management circuit 51 may reset the temperature state corresponding to the entity unit 71 in the table information 700 to the parameter value "000".
On the other hand, in response to the first temperature state and the second temperature state meeting the first condition, the memory management circuit 51 may perform a write operation (also referred to as a second write operation) on the physical unit 91 according to the write command 901 in the second temperature state. The second write operation is used to store the data 902 indicated by the write instruction 901 into the physical unit 91. For example, in a second write operation, the memory management circuit 51 may send at least one write command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to store the data 902 in the physical unit 91 in the second temperature state. For example, in the entity unit 91, the data 902 may be stored before or after the data 702 (fig. 9 illustrates that the data 902 is stored after the data 702), which is not limited by the present invention.
The memory management circuit 51 may update the table information 700 corresponding to storing the data 902 to the entity unit 91. For example, according to the temperature value 910, the memory management circuit 51 may update the temperature status identification information corresponding to the entity unit 91 in the table information 700 to the parameter value "010" to reflect the temperature status (i.e. the second temperature status) when the entity unit 91 is programmed to store the data 902. It should be noted that in another exemplary embodiment, the second temperature state may be represented by other parameter values or directly by the temperature value 910, which is not a limitation of the present invention.
It should be noted that in an exemplary embodiment of fig. 7, the entity unit 71 is set as the on unit. Thereafter, in the example embodiment of fig. 8 or 9, the memory management circuit 51 may set the physical unit 81 or 91 as a new on unit instead of the physical unit 71. Thereafter, new data from the host system 11 may be stored to the entity unit 81 or 91.
In another example embodiment of FIG. 9, the entity unit 71 is still an on unit when the write command 901 is received. Thus, the memory management circuit 51 may store the data 902 indicated to be stored by the write instruction 901 in the entity unit 71 first. At this time, the entity unit 71 stores both data 702 and 902. Thereafter, in response to the first temperature state and the second temperature state meeting the first condition, the memory management circuit 51 may restore the data 702 and 902 (and the rest of the data in the physical unit 71) to the physical unit 91 in the data refresh operation in the second temperature state.
In an example embodiment, if the first temperature state and the second temperature state do not meet the first condition, the memory management circuit 51 may not perform the data refresh operation on the physical unit 71. In the event that the data refresh operation is not performed, the physical unit 71 may be maintained as an on unit to continue to receive new data from the host system 11 until the physical unit 71 is full.
Fig. 10 is a schematic diagram of a third write operation according to an example embodiment of the invention. Referring to fig. 10, following the example embodiment of fig. 7, after performing the first write operation, the memory management circuit 51 may detect the second temperature state of the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may receive the temperature value 1010 from the temperature sensor 57. The temperature value 1010 may reflect the ambient temperature sensed by the temperature sensor 57 at the second point in time. The second point in time is later than the first point in time. The memory management circuit 51 may obtain a second temperature state based on the temperature value 1010.
Near the second point in time, the memory management circuit 51 may receive a write instruction 1001 from the host system 11. Write instruction 1001 may indicate that data 1002 (i.e., second data) is stored. For example, write instruction 1001 may instruct to store data 1002 to a particular logical unit. In response to receipt of the write command 1001, the memory management circuit 51 may determine whether the first temperature state and the second temperature state satisfy the first condition.
In the exemplary embodiment of fig. 10, it is assumed that the first temperature state and the second temperature state do not satisfy the first condition. In response to the first temperature state and the second temperature state not meeting the first condition, the memory management circuit 51 may not perform the data refresh operation on the physical unit 71. Instead, in the second temperature state, the memory management circuit 51 may perform a write operation (also referred to as a third write operation) on the physical unit 71 according to the write command 1001. The third write operation is used to store the data 1002 indicated by the write command 1001 into the physical unit 71. For example, in a third write operation, the memory management circuit 51 may send at least one write command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to store the data 1002 in the physical unit 71 in the second temperature state. For example, in the entity unit 71, the data 1002 may be stored after the data 702, as shown in fig. 10.
The memory management circuit 51 may update the table information 700 corresponding to storing the data 1002 to the entity unit 71. For example, according to the temperature value 1010, the memory management circuit 51 may update the temperature state identification information corresponding to the entity unit 71 in the table information 700 from the parameter value "101" of fig. 7 to the parameter value "001". The parameter value "001" may reflect a temperature state (i.e., a second temperature state) of the entity unit 71 when it is programmed to store the data 1002. It should be noted that in another exemplary embodiment, the second temperature state may be represented by other parameter values or directly by the temperature value 1010, which is not a limitation of the present invention.
It should be noted that in the exemplary embodiment of fig. 10, the memory management circuit 51 does not perform the data refresh operation on the physical unit 71 in the second temperature state. Thus, when the temperature change of the rewritable nonvolatile memory module 43 is not large (for example, the temperature difference value does not reach the threshold value or the temperature difference value does not fall within a specific value range), the loss caused by excessively performing the data movement on the memory cell can be reduced.
It should be noted that the memory management circuit 51 may use one or more logic determination methods to determine whether the first temperature state and the second temperature state meet the first condition, for example, determine whether a temperature difference between a temperature value corresponding to the first temperature state and a temperature value corresponding to the second temperature state reaches a threshold value and/or determine whether the temperature difference falls within a specific range of values. Then, the memory management circuit 51 may decide whether to perform or trigger the data refresh operation according to the determination result.
Fig. 11 is a schematic diagram showing the triggering or non-triggering of a data refresh operation at different temperature change states according to an example embodiment of the present invention. Referring to fig. 11, the temperature status identification information corresponding to the first entity unit (e.g., entity unit 71 of fig. 7) may include parameter values "101", "001", "010" and "110". The parameter value "101" may reflect that the temperature of the first physical unit at the last time it was programmed falls between the temperature values T (5) to T (3). The parameter value "001" may reflect that the temperature of the first physical unit when it was last programmed falls between the temperature values T (3) to T (1). The parameter value "010" may reflect that the temperature of the first physical unit at the last time it was programmed falls between the temperature values T (2) to T (4). The parameter value "110" may reflect that the temperature of the first physical unit last programmed falls between the temperature values T (4) to T (6).
After a temperature change (e.g., from a first temperature state to a second temperature state), the memory management circuit 51 may obtain a trigger threshold THR and a temperature T of the rewritable nonvolatile memory module 43 in the second temperature state. The trigger threshold THR may be determined corresponding to a first temperature state of the first physical unit. For example, assuming that the first temperature state of the first physical unit is represented by the parameter 101 (i.e., the temperature of the first physical unit when it was last programmed falls between the temperature values T (5) and T (3)), the trigger threshold THR corresponding to the first physical unit may be set to be the same as or similar to the temperature value T (1), as shown in fig. 11. In other words, the triggering threshold THR may be used to determine whether the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state reaches a threshold value. The determined trigger threshold THR may be different according to different first temperature states of the first physical unit.
The memory management circuit 51 may compare the temperature value T with the trigger threshold THR. Then, the memory management circuit 51 can determine whether the first temperature state and the second temperature state meet the first condition according to the comparison result. For example, in an exemplary embodiment of fig. 11, if the temperature value T is greater than the triggering threshold value THR (equivalent to the temperature difference between the first temperature state and the second temperature state reaching the threshold value), the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition and trigger or initiate the data refresh operation. Alternatively, in another example embodiment of fig. 11, if the temperature value T is not greater than the triggering threshold value THR (equivalent to the temperature difference value between the first temperature state and the second temperature state not reaching the threshold value), the memory management circuit 51 may determine that the first temperature state and the second temperature state do not meet the first condition and not trigger or initiate the data refresh operation.
Fig. 12 is a schematic diagram showing the triggering or non-triggering of a data refresh operation at different temperature change states according to an example embodiment of the present invention. Referring to fig. 12, the temperature status identification information corresponding to the first entity unit (e.g., entity unit 71 of fig. 7) may include parameter values "101", "001", "010" and "110". After the temperature change, the memory management circuit 51 may obtain temperature state identification information (also referred to as first temperature state identification information) corresponding to the first temperature state of the first entity unit and temperature state identification information (also referred to as second temperature state identification information) corresponding to the second temperature state. The memory management circuit 51 may perform a logic operation with the first temperature state identification information and the second temperature state identification information. For example, the logical operation may include an Exclusive OR (XOR) operation. The memory management circuit 51 can determine whether the first temperature state and the second temperature state meet the first condition according to the execution result of the logic operation.
For example, in an example embodiment of fig. 12, it is assumed that the first temperature state identification information corresponding to the first temperature state includes a parameter value of "001" and the second temperature state identification information corresponding to the second temperature state includes a parameter value of "010". Based on the result of the logic operation (e.g., the result of the XOR operation is "011", which is not equal to a preset value "111") (equivalent to the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state not falling within the specific value range), the memory management circuit 51 may determine that the first temperature state and the second temperature state do not meet the first condition and not trigger or initiate the data refresh operation. Alternatively, in an example embodiment of fig. 12, it is assumed that the first temperature state identification information corresponding to the first temperature state includes a parameter value of "101" and the second temperature state identification information corresponding to the second temperature state includes a parameter value of "010". Based on the result of the logic operation (for example, the result of the XOR operation is "111", which is equal to the preset value "111") (which is equal to that the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state falls within the specific value range), the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition and trigger or initiate the data refresh operation. It should be noted that the logic determination methods mentioned in the exemplary embodiments of fig. 11 and fig. 12 are examples, and are not intended to limit the present invention.
In an example embodiment, the memory management circuit 51 may allow the data refresh operation to be initiated when the temperature state of the rewritable nonvolatile memory module 43 is changed and maintained in the second temperature state for more than a certain period of time. By doing so, it is possible to avoid the data refresh operation being performed too frequently due to frequent changes in the temperature state of the rewritable nonvolatile memory module 43.
In an example embodiment, the memory management circuit 51 may instruct the rewritable nonvolatile memory module 43 to perform the programming operation on the physical unit using different electrical parameters under different temperature states, so as to satisfy the electrical characteristics of the memory cells in the rewritable nonvolatile memory module 43 under different temperature states. For example, the electrical parameters may include a programming voltage (i.e., a pulse voltage) and/or a programming time, etc., and the invention is not limited thereto. For example, in the first temperature state, the memory management circuit 51 may instruct the rewritable nonvolatile memory module 43 to program at least one memory cell in the first physical unit using a specific electrical parameter (also referred to as a first electrical parameter). Thereafter, in the second temperature state, the memory management circuit 51 may instruct the rewritable nonvolatile memory module 43 to program the at least one memory cell in the first physical unit using a different electrical parameter (also referred to as a second electrical parameter). Therefore, the electronic characteristics of the memory cells in the rewritable nonvolatile memory module 43 in different temperature states can be satisfied by different electrical references, so that the programmed memory cells have better voltage states in the current temperature state.
Fig. 13 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Referring to fig. 13, in step S1301, a first temperature state of the rewritable nonvolatile memory module is detected. In step S1302, in the first temperature state, a first write operation is performed on a first physical unit in the rewritable nonvolatile memory module to store first data into the first physical unit. After the first write operation is performed, in step S1303, a second temperature state of the rewritable nonvolatile memory module is detected. In step S1304, it is determined whether the first temperature state and the second temperature state meet a first condition. In response to the first temperature state and the second temperature state meeting a first condition, in step S1305, a data refresh operation is performed on the first entity unit in the second temperature state to restore the first data to a second entity unit in the rewritable non-volatile memory module, wherein the second entity unit is different from the first entity unit. In addition, if the first temperature state and the second temperature state do not meet the first condition, step S1303 may be repeatedly performed.
However, the steps in fig. 13 are described in detail above, and will not be described again here. It should be noted that each step in fig. 13 may be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the method of fig. 13 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.
In summary, the exemplary embodiments of the present invention can perform the data refresh operation on the specific physical unit in the environment with severe temperature variation. Therefore, the reliability of the rewritable nonvolatile memory module in data access under the environment with severe temperature change can be improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (24)

1. A memory management method for a memory storage device, wherein the memory storage device comprises a rewritable non-volatile memory module comprising a plurality of physical units, and the memory management method comprises:
detecting a first temperature state of the rewritable non-volatile memory module;
performing a first write operation on a first entity unit of the plurality of entity units in the first temperature state to store first data into the first entity unit;
detecting a second temperature state of the rewritable non-volatile memory module after performing the first write operation; and
in response to the first temperature state and the second temperature state meeting a first condition, performing a data refresh operation on the first physical unit in the second temperature state to restore the first data to a second physical unit of the plurality of physical units, wherein the second physical unit is different from the first physical unit,
the first condition includes that a temperature difference value between a temperature value corresponding to the first temperature state and a temperature value corresponding to the second temperature state reaches a threshold value or falls within a specific numerical range.
2. The memory management method of claim 1, further comprising:
obtaining a trigger threshold corresponding to the first temperature state;
obtaining a temperature value of the rewritable non-volatile memory module in the second temperature state;
comparing the trigger threshold value with the temperature value; and
and judging whether the first temperature state and the second temperature state accord with the first condition or not according to the comparison result.
3. The memory management method of claim 1, further comprising:
obtaining first temperature state identification information corresponding to the first temperature state;
obtaining second temperature state identification information corresponding to the second temperature state;
performing a logic operation on the first temperature state identification information and the second temperature state identification information; and
and judging whether the first temperature state and the second temperature state accord with the first condition according to the execution result of the logic operation.
4. The memory management method of claim 1, wherein detecting the second temperature state of the rewritable non-volatile memory module comprises:
receiving a write instruction from a host system; and
And responding to the writing instruction to judge whether the first temperature state and the second temperature state accord with the first condition.
5. The memory management method of claim 4, further comprising:
responsive to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit in the second temperature state to store second data indicated by the write instruction into the second physical unit; and
and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
6. The memory management method of claim 4, further comprising:
performing a second write operation on the first entity unit in the second temperature state to store second data indicated by the write instruction into the first entity unit; and
in the data refreshing operation, the first data and the second data are read out from the first entity unit and stored into the second entity unit together.
7. The memory management method of claim 4, further comprising:
recording temperature state identification information corresponding to the first entity unit according to the first temperature state;
In response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and
updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
8. The memory management method of claim 1, further comprising:
in the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first physical unit using a first electrical parameter; and
and in the second temperature state, instructing the rewritable nonvolatile memory module to program the at least one memory cell by using a second electrical parameter, wherein the first electrical parameter is different from the second electrical parameter.
9. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module including a plurality of physical units; and
A memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is configured to detect a first temperature state of the rewritable nonvolatile memory module,
the memory control circuit unit is further configured to perform a first write operation on a first physical unit of the plurality of physical units in the first temperature state to store first data into the first physical unit,
after the first write operation is performed, the memory control circuit unit is further configured to detect a second temperature state of the rewritable nonvolatile memory module, and
in response to the first temperature state and the second temperature state meeting a first condition, the memory control circuit unit is further configured to perform a data refresh operation on the first physical unit in the second temperature state to restore the first data to a second physical unit of the plurality of physical units, wherein the second physical unit is different from the first physical unit,
the first condition includes that a temperature difference value between a temperature value corresponding to the first temperature state and a temperature value corresponding to the second temperature state reaches a threshold value or falls within a specific numerical range.
10. The memory storage device of claim 9, wherein the memory control circuit unit is further to:
obtaining a trigger threshold corresponding to the first temperature state;
obtaining a temperature value of the rewritable non-volatile memory module in the second temperature state;
comparing the trigger threshold value with the temperature value; and
and judging whether the first temperature state and the second temperature state accord with the first condition or not according to the comparison result.
11. The memory storage device of claim 9, wherein the memory control circuit unit is further to:
obtaining first temperature state identification information corresponding to the first temperature state;
obtaining second temperature state identification information corresponding to the second temperature state;
performing a logic operation on the first temperature state identification information and the second temperature state identification information; and
and judging whether the first temperature state and the second temperature state accord with the first condition according to the execution result of the logic operation.
12. The memory storage device of claim 9, wherein detecting the second temperature state of the rewritable non-volatile memory module comprises:
Receiving a write instruction from a host system; and
and responding to the writing instruction to judge whether the first temperature state and the second temperature state accord with the first condition.
13. The memory storage device of claim 12, wherein the memory control circuit unit is further to:
responsive to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit in the second temperature state to store second data indicated by the write instruction into the second physical unit; and
and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
14. The memory storage device of claim 12, wherein the memory control circuit unit is further to:
performing a second write operation on the first entity unit in the second temperature state to store second data indicated by the write instruction into the first entity unit; and
in the data refreshing operation, the rewritable nonvolatile memory module is instructed to read the first data together with the second data from the first entity unit and store the first data together with the second data into the second entity unit.
15. The memory storage device of claim 12, wherein the memory control circuit unit is further to:
recording temperature state identification information corresponding to the first entity unit according to the first temperature state;
in response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and
updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
16. The memory storage device of claim 9, wherein the memory control circuit unit is further to:
in the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first physical unit using a first electrical parameter; and
and in the second temperature state, instructing the rewritable nonvolatile memory module to program the at least one memory cell by using a second electrical parameter, wherein the first electrical parameter is different from the second electrical parameter.
17. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, and the memory control circuit unit comprises:
a host interface for connecting to a host system;
a memory interface to connect to the rewritable non-volatile memory module; and
a memory management circuit coupled to the host interface and the memory interface,
wherein the memory control circuit unit is configured to detect a first temperature state of the rewritable nonvolatile memory module,
the memory management circuit is further configured to perform a first write operation to a first physical unit of the plurality of physical units in the first temperature state to store first data into the first physical unit,
after performing the first write operation, the memory management circuit is further configured to detect a second temperature state of the rewritable non-volatile memory module, and
in response to the first temperature state and the second temperature state meeting a first condition, the memory management circuit is further configured to perform a data refresh operation on the first physical unit in the second temperature state to restore the first data to a second physical unit of the plurality of physical units, wherein the second physical unit is different from the first physical unit,
The first condition includes that a temperature difference value between a temperature value corresponding to the first temperature state and a temperature value corresponding to the second temperature state reaches a threshold value or falls within a specific numerical range.
18. The memory control circuit unit of claim 17, wherein the memory management circuit is further to:
obtaining a trigger threshold corresponding to the first temperature state;
obtaining a temperature value of the rewritable non-volatile memory module in the second temperature state;
comparing the trigger threshold value with the temperature value; and
and judging whether the first temperature state and the second temperature state accord with the first condition or not according to the comparison result.
19. The memory control circuit unit of claim 17, wherein the memory management circuit is further to:
obtaining first temperature state identification information corresponding to the first temperature state;
obtaining second temperature state identification information corresponding to the second temperature state;
performing a logic operation on the first temperature state identification information and the second temperature state identification information; and
and judging whether the first temperature state and the second temperature state accord with the first condition according to the execution result of the logic operation.
20. The memory control circuit unit of claim 17, wherein detecting the second temperature state of the rewritable non-volatile memory module comprises:
receiving a write instruction from a host system; and
and responding to the writing instruction to judge whether the first temperature state and the second temperature state accord with the first condition.
21. The memory control circuit unit of claim 20, wherein the memory management circuit is further to:
responsive to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit in the second temperature state to store second data indicated by the write instruction into the second physical unit; and
and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
22. The memory control circuit unit of claim 20, wherein the memory management circuit is further to:
performing a second write operation on the first entity unit in the second temperature state to store second data indicated by the write instruction into the first entity unit; and
In the data refreshing operation, the rewritable nonvolatile memory module is instructed to read the first data together with the second data from the first entity unit and store the first data together with the second data into the second entity unit.
23. The memory control circuit unit of claim 20, wherein the memory management circuit is further to:
recording temperature state identification information corresponding to the first entity unit according to the first temperature state;
in response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and
updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
24. The memory control circuit unit of claim 17, wherein the memory management circuit is further to:
in the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first physical unit using a first electrical parameter; and
And in the second temperature state, instructing the rewritable nonvolatile memory module to program the at least one memory cell by using a second electrical parameter, wherein the first electrical parameter is different from the second electrical parameter.
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