CN113284527B - Clock data recovery circuit, memory storage device and signal adjustment method - Google Patents

Abstract

The invention provides a clock data recovery circuit, a memory storage device and a signal adjustment method. The method comprises the following steps: detecting a phase difference between the first signal and the clock signal; generating a voting signal according to the phase difference and the first clock frequency; sequentially outputting a plurality of adjustment signals according to the voting signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the plurality of adjustment signals which are sequentially output.

Description

Clock data recovery circuit, memory storage device and signal adjustment method

Technical Field

The present invention relates to signal conditioning, and more particularly, to a clock data recovery circuit, a memory storage device, and a signal conditioning method.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.

Generally, memory storage devices have clock data recovery (Clock and Data Recovery, CDR) circuits built into them to correct data signals and clock signals. Along with the continuous rise of the transmission frequency of the data signal, the clock correction efficiency and jitter suppression of the clock data recovery circuit are also more important. In some cases, when the difference between the phase difference or the frequency difference between the data signal and the clock signal is large, the jitter tolerance (jitter tolerance) of the clock data recovery circuit may be reduced due to the too large instantaneous adjustment amount of the phase or the frequency.

Disclosure of Invention

The invention provides a clock data recovery circuit, a memory storage device and a signal adjustment method, which can improve jitter tolerance of the clock data recovery circuit.

Exemplary embodiments of the present invention provide a clock data recovery circuit including a phase detector, a voting circuit, a digital loop filter, and a phase interpolator. The phase detector is configured to detect a phase difference between a first signal and a clock signal. The voting circuit is coupled to the phase detector and configured to generate a voting signal based on the phase difference and a first clock frequency. The digital loop filter is connected to the voting circuit and is used for outputting a plurality of adjustment signals according to the voting signal and a second clock frequency in sequence, wherein the first clock frequency is different from the second clock frequency. The phase interpolator is connected to the phase detector and the digital loop filter and is used for generating the clock signal according to the plurality of adjusting signals which are output in sequence.

In an exemplary embodiment of the invention, the digital loop filter includes an accumulation circuit and a division circuit. The accumulation circuit is connected to the voting circuit. The dividing circuit is connected to the accumulating circuit. The accumulation circuit is used for determining a first adjustment code according to the voting signal and the first clock frequency. The dividing circuit is used for dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals according to the plurality of second adjusting codes.

In an example embodiment of the present invention, the digital loop filter further comprises a multiplexer. The multiplexer is connected to the dividing circuit and the phase interpolator and is used for sequentially outputting the plurality of adjustment signals to the phase interpolator according to the second clock frequency.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, a memory control circuit unit and a clock data recovery circuit. The connection interface unit is used for being connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The clock data recovery circuit is arranged in at least one of the connection interface unit, the rewritable nonvolatile memory module and the memory control circuit unit. The clock data recovery circuit is used for detecting a phase difference between the first signal and the clock signal. The clock data recovery circuit is further configured to generate a voting signal according to the phase difference and the first clock frequency. The clock data recovery circuit is further configured to sequentially output a plurality of adjustment signals according to the voting signal and the second clock frequency. The clock data recovery circuit is further configured to generate the clock signal according to the plurality of adjustment signals sequentially output. The first clock frequency is different from the second clock frequency.

In an exemplary embodiment of the invention, the clock data recovery circuit includes an accumulation circuit and a dividing circuit. The dividing circuit is connected to the accumulating circuit. The accumulation circuit is used for determining a first adjustment code according to the voting signal and the first clock frequency. The dividing circuit is used for dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals according to the plurality of second adjusting codes.

In an exemplary embodiment of the invention, the clock data recovery circuit further includes a multiplexer. The multiplexer is connected to the dividing circuit and is used for sequentially outputting the plurality of adjustment signals to a phase interpolator in the clock data recovery circuit according to the second clock frequency.

The exemplary embodiments of the present invention further provide a signal conditioning method for a memory storage device. The memory storage device has a rewritable nonvolatile memory module, and the signal adjustment method includes: detecting a phase difference between the first signal and the clock signal; generating a voting signal according to the phase difference and the first clock frequency; sequentially outputting a plurality of adjustment signals according to the voting signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the plurality of adjustment signals which are sequentially output.

In an exemplary embodiment of the present invention, the step of sequentially outputting the plurality of adjustment signals according to the voting signal and the second clock frequency includes: determining a first adjustment code according to the voting signal and the first clock frequency; and dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals according to the plurality of second adjusting codes.

In an exemplary embodiment of the present invention, the step of sequentially outputting the plurality of adjustment signals according to the voting signal and the second clock frequency further includes: the plurality of adjustment signals are sequentially output to a phase interpolator in the memory storage device according to the second clock frequency.

In an exemplary embodiment of the present invention, the plurality of adjustment signals sequentially output are used to gradually adjust the clock signal to meet a target phase difference or a target frequency difference.

The exemplary embodiments of the present invention further provide a clock data recovery circuit including a phase detector, a voting circuit, a bit loop filter, and a phase interpolator. The voting circuit is connected to the output of the phase detector. The digital loop filter is connected to the output of the voting circuit. The phase interpolator is connected to the output of the digital loop filter and the phase detector. The voting circuit operates at a first clock frequency. The digital loop filter operates at a second clock frequency. The first clock frequency is different from the second clock frequency.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, a memory control circuit unit and a clock data recovery circuit. The connection interface unit is used for being connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The clock data recovery circuit is arranged in at least one of the connection interface unit, the rewritable nonvolatile memory module and the memory control circuit unit. The voting circuit in the clock data recovery circuit operates at a first clock frequency. The digital loop filter in the clock data recovery circuit operates at a second clock frequency. The digital loop filter is connected to the output of the voting circuit. The first clock frequency is different from the second clock frequency.

In an example embodiment of the present invention, the first clock frequency is lower than the second clock frequency.

Based on the above, after measuring the phase difference between the first signal and the clock signal, the voting circuit may generate the voting signal according to the phase difference and the first clock frequency. The digital loop filter can sequentially output a plurality of adjustment signals according to the voting signal and a second clock frequency, and the first clock frequency is different from the second clock frequency. The phase interpolator may generate the clock signal according to the plurality of adjustment signals sequentially output. Thus, the jitter tolerance of the clock data recovery circuit can be improved.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention;

FIG. 1 is a schematic diagram of a clock data recovery circuit according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a digital loop filter according to an example embodiment of the invention;

FIG. 3 is a schematic diagram illustrating a plurality of adjustment signals being sequentially output according to an exemplary embodiment of the present invention;

FIG. 4 is a schematic diagram of an exemplary embodiment of an adjustment clock signal according to a plurality of adjustment signals sequentially output;

FIG. 5 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;

FIG. 6 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention;

FIG. 7 is a schematic diagram of a host system and a memory storage device according to another example embodiment of the invention;

FIG. 8 is a schematic block diagram of a memory storage device according to an example embodiment of the invention;

fig. 9 is a flowchart illustrating a signal conditioning method according to an exemplary embodiment of the present invention.

Description of the reference numerals

10, a clock data recovery circuit;

a phase detector;

a voting circuit;

a digital loop filter;

a phase interpolator;

15, a phase-locked loop circuit;

din, PS, UP, DN, PC (i), PC (1) through PC (n), PC (D), CLK (HS), CLK (LS), CLK (REF) signals;

an accumulation circuit;

a dividing circuit 22;

a multiplexer;

201,202, amplifiers;

211,212 accumulators;

221, adder;

t (0), T (1), T (01) to T (05) are time points;

50,70,80 memory storage devices;

51,71 a host system;

510, a system bus;

511 a processor;

512, random access memory;

513 read-only memory;

514, a data transmission interface;

input/output (I/O) devices;

60, a motherboard;

601, a U disk;

602, a memory card;

603, a solid state disk;

604, a wireless memory storage device;

605 a global positioning system module;

606 a network interface card;

607, wireless transmission means;

608, a keyboard;

609, a screen;

610, a horn;

72, SD card;

73:CF card;

74, embedded storage device;

741, an embedded multimedia card;

742 an embedded multi-chip package memory device;

801, a connection interface unit;

a memory control circuit unit 802;

803 a rewritable non-volatile memory module;

step S901, detecting a phase difference between the first signal and the clock signal;

s902, generating a voting signal according to the phase difference and the first clock frequency;

s903, outputting a plurality of adjustment signals according to the voting signal and a second clock frequency in sequence, wherein the first clock frequency is different from the second clock frequency;

step S904, generating the clock signal according to the plurality of adjustment signals sequentially output.

Detailed Description

The present invention is described below with reference to a number of exemplary embodiments, however, the present invention is not limited to the exemplary embodiments illustrated. Also, suitable combinations are allowed between the exemplary embodiments. The term "coupled" as used throughout this specification (including the claims) may refer to any direct or indirect means of coupling. For example, if a first device is described herein as being connected to a second device, it should be interpreted that the first device may be directly connected to the second device, or that the first device may be indirectly connected to the second device through other devices or some connection means. Further, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.

Fig. 1 is a schematic diagram of a clock data recovery circuit according to an exemplary embodiment of the invention. Referring to fig. 1, the clock data recovery circuit 10 can be used for receiving a signal (also referred to as a first signal) Din and generating a signal CLK (HS). The signal CLK (HS) is a clock signal.

The clock data recovery circuit 10 can detect the phase difference between the signals Din and CLK (HS) and adjust the signal CLK (HS) according to the phase difference. For example, the clock data recovery circuit 10 may adjust the phase and/or frequency of the signal CLK (HS) according to the phase and/or frequency of the signal Din. Thus, the clock data recovery circuit 10 can be used to lock the signals Din and CLK (HS) in a predetermined phase relationship. For example, the phase difference between signals Din and CLK (HS) may be locked at 0 degrees, 90 degrees, 180 degrees, 270 degrees, or 360 degrees. In an example embodiment, the signal Din may be a data signal. The locked signal CLK (HS) may also be used to analyze (e.g., sample) the signal Din to obtain bit data (e.g., bit 1/0) conveyed by the signal Din.

The clock data recovery circuit 10 includes a phase detector 11, a voting circuit 12, a digital loop filter 13, and a phase interpolator 14. The phase detector 11 may be configured to receive the signals Din and CLK (HS) and detect a phase difference between the signals Din and CLK (HS). The phase detector 11 may generate a signal PS based on the measured phase difference. In other words, the signal PS may reflect the phase difference between the signals Din and CLK (HS).

The voting circuit 12 is connected to the phase detector 11 and can receive the signal PS. Voting circuit 12 may generate a signal UP/DN based on signal PS. The signal UP/DN may be used to change the phase and/or frequency of the signal CLK (HS). For example, the signal UP may be used to advance at least one rising edge and/or at least one falling edge of the signal CLK (HS). The signal DN may be used to delay at least one rising edge and/or at least one falling edge of the signal CLK (HS). In an exemplary embodiment, the signal UP/DN is also referred to as a voting signal.

The digital loop filter 13 is connected to the voting circuit 12. Digital loop filter 12 may receive signal UP/DN and generate signal PC (i) based on signal UP/DN. The signal PC (i) may correspond to a code (or control code). This code (or control code) may be used to control the phase and/or frequency of the signal CLK (HS). In an example embodiment, the signal PC (i) is also referred to as an adjustment signal.

The phase interpolator 14 is connected to the digital loop filter 13, the phase detector 11 and the phase locked loop (Phase Locked Loop, PLL) circuit 15. The phase interpolator 14 is arranged to receive the signal PC (i) from the digital loop filter 13 and the signal CLK (REF) from the phase locked loop circuit 15. The signal CLK (REF) is also referred to as a reference clock signal. For example, the signal CLK (REF) may be used as a base of the phase interpolator 14. The phase interpolator 14 may perform phase interpolation on the signal CLK (REF) based on the signal PC (i) to generate the signal CLK (HS). In addition, the phase interpolator 14 may adjust the phase and/or frequency of the signal CLK (HS) based on the signal PC (i). The phase-locked loop circuit 15 may be included in the clock data recovery circuit 10 or may be independent of the clock data recovery circuit 10, and the invention is not limited thereto.

By the cooperation of the phase detector 11, the voting circuit 12, the digital loop filter 13 and the phase interpolator 14, the signals Din and CLK (HS) can be locked to the predetermined phase relationship for subsequent signal analysis. In addition, the signal CLK (HS) may also be provided to other circuit elements for use.

It should be noted that voting circuit 12 may operate at one clock frequency (also referred to as a first clock frequency) and digital loop filter 13 may operate at another clock frequency (also referred to as a second clock frequency). From another perspective, the digital loop filter 13 may operate at both the first clock frequency and the second clock frequency. The first clock frequency is different from the second clock frequency. For example, the first clock frequency may be lower than the second clock frequency. For example, the first clock frequency may be 20MHz and the second clock frequency may be 100MHz, and the present invention is not limited to the actual values of the first clock frequency and the second clock frequency.

In an exemplary embodiment, the voting circuit 12 may receive the signal CLK (LS) and use the frequency of the signal CLK (LS) as the first clock frequency. Voting circuit 12 may output signals UP/DN based on the frequency of signal CLK (LS) and signal PS. For example, voting circuit 12 may be triggered by the rising and/or falling edges of signal CLK (LS) to generate signal PS.

In an exemplary embodiment, the digital loop filter 13 may receive the signal CLK (HS) and use the frequency of the signal CLK (HS) as the second clock frequency. The digital loop filter 13 may output a signal UP/DN according to the frequency of the signal CLK (HS) and the signal UP/DN. For example, the digital loop filter 13 may be triggered by the rising and/or falling edges of the signal CLK (HS) to output the signal PC (i).

In an exemplary embodiment, the signal CLK (LS) is generated by frequency division of the signal CLK (HS), for example. For example, a Divider (Divider) may be used to divide the signal CLK (HS) to generate the signal CLK (LS). This frequency divider may be included in the clock data recovery circuit 10 or may be independent of the clock data recovery circuit 10.

In an exemplary embodiment, i has a value between 1 and n, and n is an integer greater than 1. The second clock frequency may be approximately n times the first clock frequency. In response to a signal UP/DN generated by the voting circuit 12, the digital loop filter 13 can sequentially output n signals PC (1) to PC (n) to the phase interpolator 14 according to the frequency of the signal UP/DN and the signal CLK (HS). The phase interpolator 14 may generate the signal CLK (HS) and/or adjust the phase (or frequency) of the signal CLK (HS) according to the n signals PC (1) -PC (n) sequentially output. Thus, the n signals PC (1) -PC (n) sequentially output can be used to gradually adjust the signal CLK (HS) to satisfy a phase difference (also referred to as a target phase difference) or a frequency difference (also referred to as a target frequency difference).

Fig. 2 is a schematic diagram of a digital loop filter according to an example embodiment of the invention. Referring to fig. 2, the digital loop filter 13 may include an accumulation circuit 21, a dividing circuit 22 and a multiplexer 23. The accumulation circuit 21 determines an adjustment code (also referred to as a first adjustment code) according to the signal UP/DN and the first clock frequency. The dividing circuit 22 is connected to the accumulating circuit 21 and the multiplexer 23. The dividing circuit 22 can divide the first adjustment code into a plurality of adjustment codes (also referred to as second adjustment codes) and generate signals PC (1) to PC (n) according to the plurality of second adjustment codes. The multiplexer 23 may sequentially output the signals PC (1) to PC (n) according to the second clock frequency.

From another perspective, a portion of the circuits of the digital loop filter 13 (i.e., the accumulating circuit 21 and the dividing circuit 22) operate at and operate according to a first clock frequency (e.g., generate signals PC (1) -PC (n)). The other part of the circuitry of the digital loop filter 13 (i.e. the multiplexer 23) is operated at and according to the second clock frequency (e.g. the output signal PC (i)).

In an example embodiment, the accumulation circuit 21 includes an amplifier 201, an amplifier 202, an accumulator 211, an accumulator 212, and an adder 221. The inputs of the amplifiers 201 and 202 may be connected to the output of the phase detector 11 of fig. 1 to receive the signal UP/DN. An input of the accumulator 211 may be connected to an output of the amplifier 202. The output of the accumulator 211 and the amplifier 201 may be connected to an input of the adder 221. An input of the accumulator 212 may be connected to an output of the adder 221. An output of the accumulator 212 may be connected to an input of the divider circuit 22.

In an example embodiment, amplifier 201 is also referred to as a proportional gain amplifier and amplifier 202 is also referred to as an integral gain amplifier. For example, the amplifier 201 may amplify the value corresponding to the signal UP/DN by N times, and the amplifier 202 may amplify the value corresponding to the signal UP/DN by M times. N is greater than M. For example, N may be 6 and/or M may be 4, and the values of N and M are not limited thereto. The value amplified M times by the amplifier 202 may be used to update the value stored by the accumulator 211. The adder 221 may add the value stored in the accumulator 211 to the value output from the amplifier 201 and update the value stored in the accumulator 212 according to the operation result. The value is the first adjustment code. The accumulation circuit 21 may receive the signal CLK (LS) and update the first adjustment code according to the frequency of the signal CLK (LS) (i.e., the first clock frequency). Then, the accumulating circuit 21 may transmit the signal corresponding to the first adjustment code to the dividing circuit 22.

Based on the output of the summation circuit 21, the segmentation circuit 22 can generate signals PC (1) through PC (n). Each of the signals PC (1) -PC (n) corresponds to a second adjustment code. In an exemplary embodiment, assuming that one first adjustment code can be used to adjust the signal CLK (HS) individually and once to satisfy a target phase difference or a target frequency difference, all the second adjustment codes corresponding to the signals PC (1) to PC (n) can adjust the signal CLK (HS) jointly and gradually to satisfy the target phase difference or the target frequency difference.

Fig. 3 is a schematic diagram illustrating a sequential output of a plurality of adjustment signals according to an exemplary embodiment of the present invention. Fig. 4 is a schematic diagram showing an adjustment clock signal according to a plurality of adjustment signals sequentially output according to an exemplary embodiment of the present invention.

Referring to fig. 3 and 4, it is assumed that a signal PC (D) (i.e., an adjustment signal) conventionally corresponding to the first adjustment code is outputted according to the triggering of the signal CLK (LS), and the signal PC (D) can instruct the phase interpolator 14 of fig. 1 to adjust the phase (or frequency) of the signal CLK (HS) from the current value PH (1) to the target value PH (2) at one time between the time points T (0) to T (1). The difference between the current value PH (1) and the target value PH (2) is Δph (i.e., the target phase difference or the target frequency difference).

In an exemplary embodiment, the signals PC (1) -PC (n) are sequentially output according to the triggering of the signal CLK (HS). According to the sequentially output signals PC (1) to PC (n), the phase (or frequency) of the signal CLK (HS) is gradually and steadily adjusted from the current value PH (1) to the target value PH (2) at time points T (01) to T (05). The difference between the current value PH (1) and the target value PH (2) is also Δph (i.e., the target phase difference or the target frequency difference).

In an example embodiment, n=5 is assumed. At time point T (01), in response to signal PC (1), the phase (or frequency) of signal CLK (HS) is adjusted from current value PH (1) to PH (1) +Δph× (1/5); at a time point T (02), in response to the signal PC (2), the phase (or frequency) of the signal CLK (HS) is adjusted to PH (1) +Δph× (2/5); at a time point T (03), in response to the signal PC (3), the phase (or frequency) of the signal CLK (HS) is adjusted to PH (1) +Δph× (3/5); at time point T (04), in response to signal PC (4), the phase (or frequency) of signal CLK (HS) is adjusted to PH (1) +Δph× (4/5); and, at the time point T (05), the phase (or frequency) of the signal CLK (HS) is adjusted to PH (1) +Δph=ph (2) in response to the signal PC (5).

Compared to the one-time adjustment of the signal CLK (HS) according to the signal PC (D), the phase (or frequency) of the signal CLK (HS) is stably adjusted to the target value PH (2) according to the sequentially output signals PC (1) to PC (n), so that the clock data recovery circuit 10 of fig. 1 has higher jitter tolerance. In particular, the advantages of phasing the signal CLK (HS) may be more pronounced the greater the ΔPH (i.e., the target phase difference or the target frequency difference).

In an example embodiment, the clock data recovery circuit 10 of fig. 1 may be disposed in a memory storage device to receive a signal Din from a host system. However, in another exemplary embodiment, the clock data recovery circuit 10 of fig. 1 may be disposed in other types of electronic devices, and is not limited to the memory storage device.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.

FIG. 5 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 6 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.

Referring to fig. 5 and 6, the host system 51 generally includes a processor 511, a random access memory (random access memory, RAM) 512, a Read Only Memory (ROM) 513, and a data transmission interface 514. The processor 511, the random access memory 512, the read only memory 513, and the data transmission interface 514 are all connected to a system bus 510.

In the exemplary embodiment, host system 51 is coupled to memory storage device 50 via data transfer interface 514. For example, host system 51 may store data to memory storage device 50 or read data from memory storage device 50 via data transfer interface 514. Further, the host system 51 is connected to the I/O device 52 via a system bus 510. For example, host system 51 may transmit output signals to I/O device 52 or receive input signals from I/O device 52 via system bus 510.

In an exemplary embodiment, the processor 511, the ram 512, the rom 513, and the data transmission interface 514 may be disposed on the motherboard 60 of the host system 51. The number of data transfer interfaces 514 may be one or more. The motherboard 60 may be connected to the memory storage device 50 via a wired or wireless connection via the data transfer interface 514. The memory storage 50 may be, for example, a USB flash disk 601, a memory card 602, a solid state disk (Solid State Drive, SSD) 603, or a wireless memory storage 604. The wireless memory storage 604 may be, for example, a near field wireless communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 60 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 605, a network interface card 606, a wireless transmission device 607, a keyboard 608, a screen 609, a speaker 610, etc. through the system bus 510. For example, in an exemplary embodiment, the motherboard 60 may access the wireless memory storage device 604 via the wireless transmission device 607.

In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, fig. 7 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 7, in another exemplary embodiment, the host system 71 may be a system such as a Digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 70 may be a Secure Digital (SD) card 72, a Compact Flash (CF) card 73 or an embedded memory storage device 74. The embedded memory device 74 includes embedded memory devices of various types such as embedded multimedia card (embeddedMulti Media Card, eMMC) 741 and/or embedded multi-chip package (embedded Multi Chip Package, eMMC) memory device 742 that directly connect the memory module to a substrate of the host system.

FIG. 8 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 8, the memory storage device 80 includes a connection interface unit 801, a memory control circuit unit 802, and a rewritable nonvolatile memory module 803. It should be noted that the clock data recovery circuit 10 of fig. 1 may be disposed in the connection interface unit 801 to receive the signal Din from the host system 51. Alternatively, the clock data recovery circuit 10 of fig. 1 may be disposed in the memory control circuit unit 802 and/or the rewritable nonvolatile memory module 803, which is not limited by the present invention.

The connection interface unit 801 is used to connect the memory storage device 80 to a host system. In the present exemplary embodiment, the connection interface unit 801 is compatible with the serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 801 may be a standard compliant with a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a High-Speed peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express) standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, s) interface standard, an ehcp interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 801 may be packaged in one chip with the memory control circuit unit 802, or the connection interface unit 801 may be disposed outside a chip including the memory control circuit unit 802.

The memory control circuit unit 802 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 803 according to instructions of the host system.

The rewritable nonvolatile memory module 803 is connected to the memory control circuit unit 802 and is used to store data written by the host system. The rewritable nonvolatile memory module 803 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 803 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 803 form a plurality of physical program units, and the physical program units form a plurality of physical erase units. Specifically, memory cells on the same word line constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In the present exemplary embodiment, the physical programming unit is the minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit is a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units typically include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Fig. 9 is a flowchart illustrating a signal conditioning method according to an exemplary embodiment of the present invention. Referring to fig. 9, in step S901, a phase difference between a first signal and a clock signal is detected. In step S902, a voting signal is generated according to the phase difference and the first clock frequency. In step S903, a plurality of adjustment signals are sequentially output according to the voting signal and the second clock frequency, wherein the first clock frequency is different from the second clock frequency. In step S904, the clock signal is generated according to the plurality of adjustment signals sequentially output.

However, the steps in fig. 9 are described in detail above, and will not be described again here. It should be noted that each step in fig. 9 may be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the method of fig. 9 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, in an exemplary embodiment of the invention, the voting circuit is operable at a first clock frequency and the digital loop filter is operable at a second, higher clock frequency to generate a plurality of adjustment signals in response to a voting signal. The adjusting signals can be used for adjusting the clock signals generated by the clock data recovery circuit to meet the target phase difference or the frequency difference in a plurality of times. Compared to the conventional one-time adjustment of the clock signal, the clock signal is adjusted in multiple times in the exemplary embodiment of the invention, so that the clock data recovery circuit has higher jitter tolerance.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (16)

1. A clock data recovery circuit, comprising:

a phase detector for detecting a phase difference between the first signal and the clock signal;

voting circuit, connect to stated phase detector and use for according to stated phase difference and first clock frequency produce the voting signal;

a digital loop filter connected to the voting circuit and configured to sequentially output a plurality of adjustment signals according to the voting signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and

a phase interpolator connected to the phase detector and the digital loop filter for generating the clock signal according to the plurality of adjustment signals sequentially output,

wherein the digital loop filter comprises:

an accumulation circuit connected to the voting circuit; and

a dividing circuit connected to the accumulating circuit,

the accumulation circuit is used for determining a first adjustment code according to the voting signal and the first clock frequency, and

the dividing circuit is used for dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals according to the plurality of second adjusting codes.

2. The clock data recovery circuit of claim 1, wherein the first clock frequency is lower than the second clock frequency.

3. The clock data recovery circuit of claim 1, wherein the digital loop filter further comprises:

and the multiplexer is connected to the dividing circuit and the phase interpolator and is used for outputting the plurality of adjustment signals to the phase interpolator in sequence according to the second clock frequency.

4. The clock data recovery circuit of claim 1, wherein the plurality of sequentially output adjustment signals are used to gradually adjust the clock signal to meet a target phase difference or a target frequency difference.

5. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module;

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

a clock data recovery circuit arranged in at least one of the connection interface unit, the rewritable nonvolatile memory module and the memory control circuit unit,

wherein the clock data recovery circuit is configured to detect a phase difference between the first signal and the clock signal,

the clock data recovery circuit is used for generating a voting signal according to the phase difference and a first clock frequency,

the clock data recovery circuit is used for outputting a plurality of adjusting signals according to the voting signal and the second clock frequency in sequence,

the clock data recovery circuit is used for generating the clock signal according to the plurality of adjustment signals which are sequentially output, and

the first clock frequency is different from the second clock frequency,

wherein the clock data recovery circuit comprises:

an accumulation circuit; and

a dividing circuit connected to the accumulating circuit;

the accumulation circuit is used for determining a first adjustment code according to the voting signal and the first clock frequency, and

the dividing circuit is used for dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals according to the plurality of second adjusting codes.

6. The memory storage device of claim 5, wherein the first clock frequency is lower than the second clock frequency.

7. The memory storage device of claim 5, wherein the clock data recovery circuit further comprises:

and the multiplexer is connected to the dividing circuit and used for outputting the plurality of adjustment signals to the phase interpolator in the clock data recovery circuit in sequence according to the second clock frequency.

8. The memory storage device of claim 5, wherein the plurality of adjustment signals output in sequence are used to gradually adjust the clock signal to meet a target phase difference or a target frequency difference.

9. A signal conditioning method for a memory storage device having a rewritable non-volatile memory module, the signal conditioning method comprising:

detecting a phase difference between the first signal and the clock signal;

generating a voting signal according to the phase difference and the first clock frequency;

sequentially outputting a plurality of adjustment signals according to the voting signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and

generating the clock signal according to the plurality of adjustment signals sequentially output,

wherein the step of sequentially outputting the plurality of adjustment signals according to the voting signal and the second clock frequency comprises:

determining a first adjustment code according to the voting signal and the first clock frequency; and

dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals according to the plurality of second adjusting codes.

10. The signal conditioning method of claim 9, wherein the first clock frequency is lower than the second clock frequency.

11. The signal conditioning method according to claim 9, wherein the step of sequentially outputting the plurality of conditioning signals according to the voting signal and the second clock frequency further comprises:

the plurality of adjustment signals are sequentially output to a phase interpolator in the memory storage device according to the second clock frequency.

12. The signal conditioning method according to claim 9, wherein the plurality of conditioning signals sequentially output are used to progressively condition the clock signal to meet a target phase difference or a target frequency difference.

13. A clock data recovery circuit comprising:

a phase detector;

voting circuitry connected to the phase detector;

a digital loop filter connected to the voting circuit; and

a phase interpolator coupled to the digital loop filter and the phase detector,

wherein the voting circuit operates at a first clock frequency,

the digital loop filter operates at a second clock frequency and

the first clock frequency is different from the second clock frequency,

wherein the digital loop filter comprises:

an accumulation circuit connected to the voting circuit; and

a dividing circuit connected to the accumulating circuit,

the accumulation circuit is used for determining a first adjustment code according to the voting signal generated by the voting circuit and the first clock frequency, and

the dividing circuit is used for dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals which are sequentially output to the phase interpolator according to the plurality of second adjusting codes.

14. The clock data recovery circuit of claim 13, wherein the first clock frequency is lower than the second clock frequency.

15. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module;

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

a clock data recovery circuit arranged in at least one of the connection interface unit, the rewritable nonvolatile memory module and the memory control circuit unit,

wherein the voting circuit in the clock data recovery circuit operates at a first clock frequency,

the digital loop filter in the clock data recovery circuit operates at a second clock frequency,

the digital loop filter is connected to the voting circuit, and

the first clock frequency is different from the second clock frequency,

wherein the digital loop filter comprises:

an accumulation circuit connected to the voting circuit; and

a dividing circuit connected to the accumulating circuit,

the accumulation circuit is used for determining a first adjustment code according to the voting signal generated by the voting circuit and the first clock frequency, and

the dividing circuit is used for dividing the first adjusting code into a plurality of second adjusting codes and generating a plurality of adjusting signals which are sequentially output to the phase interpolator according to the plurality of second adjusting codes.

16. The memory storage device of claim 15, wherein the first clock frequency is lower than the second clock frequency.