TWI584304B - Decoding method, memory storage device and memory control circuit unit - Google Patents

Description

Decoding method, memory storage device and memory control circuit unit

The present invention relates to a memory technology, and more particularly to a decoding method, a memory storage device, and a memory control circuit unit.

Digital cameras, mobile phones and MP3 players have grown very rapidly in recent years, and the demand for storage media has increased rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of non-volatile data, power saving, small size, and no mechanical structure, it is very suitable for various built-in examples. Portable multimedia device.

In general, after reading the data from the memory, the data may be decoded to verify the correctness of the data. Therefore, if there is an error in this data, the error can be corrected by the decoding program. A preset read voltage level is configured when the memory device is shipped. This preset read voltage level is used to read the data stored in this memory device. However, as the usage time and/or the degree of loss of the memory device increases, the data read by the preset read voltage level may contain more and more errors, even exceeding the error correction capability of the decoding program. Therefore, how to improve the correctness of the read data and/or the decoding capability of the memory by adjusting the preset read voltage level is one of the subjects studied by those skilled in the art.

The invention provides a decoding method, a memory storage device and a memory control circuit unit, which can improve decoding efficiency.

An exemplary embodiment of the present invention provides a decoding method for a rewritable non-volatile memory module including a plurality of memory cells, the decoding method comprising: reading the method based on a preset hard decision voltage level a plurality of first memory cells in the memory cell to obtain hard bit information; perform a hard decoding operation on the hard bit information; if the hard decoding operation fails, read the location based on a plurality of preset soft decision voltage levels Decoding a first memory cell to obtain soft bit information; performing a soft decoding operation on the soft bit information; if the soft decoding operation fails, reading the first memory cell based on a plurality of first test voltage levels Obtaining first soft bit information and reading the first memory cell based on the plurality of second test voltage levels to obtain second soft bit information; obtaining first evaluation parameters according to the first soft bit information and according to The second soft bit information obtains a second evaluation parameter, wherein the first evaluation parameter corresponds to a first total number of memory cells in the first memory cell that meet a first state condition, wherein the second evaluation parameter Corresponding to the first The total number of memory cells in the second line with a second status condition of the memory cell; and the predetermined voltage according to the first hard decision and the evaluation parameter of the second evaluation parameter update level.

In an exemplary embodiment of the present invention, the step of obtaining the first evaluation parameter according to the first soft bit information and obtaining the second evaluation parameter according to the second soft bit information includes: according to the The first soft bit information is used to count the total number of memory cells in the first memory cell belonging to the first transition region, wherein the first transition region includes any two voltages in the first test voltage level An area between the levels; and counting, according to the second soft bit information, a total number of memory cells in the first memory cell that belong to the second transition region, wherein the second transition region includes the The area between any two of the voltage levels in the second test voltage level.

In an exemplary embodiment of the present invention, the step of obtaining the first evaluation parameter according to the first soft bit information and obtaining the second evaluation parameter according to the second soft bit information includes: according to the The first soft bit information is used to count the total number of memory cells in the first memory cell that belong to the first steady state region, wherein the first steady state region includes the voltage with the highest voltage in the first test voltage level. An area outside the area between the level and the voltage level at which the voltage is the smallest; and counting the total number of memory cells in the first memory cell that belong to the second steady state area according to the second soft bit information, Wherein the second steady-state region includes a region outside a region between a voltage level at which the voltage of the second test voltage level is the highest and a voltage level at which the voltage is the smallest.

In an exemplary embodiment of the present invention, the first test voltage level corresponds to a first offset value, and the second test voltage level corresponds to a second offset value, where the first offset value is different And the second offset value, wherein the step of updating the preset hard decision voltage level according to the first evaluation parameter and the second evaluation parameter comprises: according to the first total number and the second total number a numerical relationship between the preset hard decision voltage levels, wherein the updated preset hard decision voltage level corresponds to the first offset value and the second offset value One.

In an exemplary embodiment of the present invention, the decoding method further includes: updating the preset soft decision voltage level according to the numerical relationship between the first total number and the second total number, where The updated preset soft decision voltage level corresponds to one of the first offset value and the second offset value.

Another exemplary embodiment of the present invention provides a memory storage device including a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is configured to be coupled to a host system. The rewritable non-volatile memory module includes a plurality of memory cells. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to send a first read instruction sequence to indicate Setting a hard decision voltage level to read a plurality of first memory cells in the memory cell to obtain hard bit information, wherein the memory control circuit unit is further configured to perform a hard decoding operation on the hard bit information, If the hard decoding operation fails, the memory control circuit unit is further configured to send a second read instruction sequence to instruct to read the first memory cell to obtain a soft bit based on a plurality of preset soft decision voltage levels. Meta-information, wherein the memory control circuit unit is further configured to perform a soft decoding operation on the soft bit information, wherein the memory control circuit unit is further configured to send the first test instruction if the soft decoding operation fails The sequence is configured to read the first memory cell based on the plurality of first test voltage levels to obtain first soft bit information and send a second test instruction sequence to indicate based on the plurality of second test voltages Reading the first memory cell to obtain second soft bit information, wherein the memory control circuit unit is further configured to obtain a first evaluation parameter according to the first soft bit information and according to the second soft The bit information obtains a second evaluation parameter, wherein the first evaluation parameter corresponds to a first total number of memory cells in the first memory cell that meet a first state condition, wherein the second evaluation parameter corresponds to the first a second total number of memory cells in the memory cell that meet the second state condition, wherein the memory control circuit unit is further configured to update the preset hard decision voltage according to the first evaluation parameter and the second evaluation parameter Level.

In an exemplary embodiment of the present invention, the memory control circuit unit obtains the first evaluation parameter according to the first soft bit information and obtains the second evaluation parameter according to the second soft bit information. The operation includes: counting, according to the first soft bit information, a total number of memory cells in the first memory cell that belong to a first transition region, wherein the first transition region includes the first Testing a region between any two voltage levels in the voltage level; and counting, according to the second soft bit information, a total number of memory cells in the first memory cell that belong to the second transition region, where The second transition region includes a region between any two of the second test voltage levels.

In an exemplary embodiment of the present invention, the memory control circuit unit obtains the first evaluation parameter according to the first soft bit information and obtains the second evaluation parameter according to the second soft bit information. The operation includes: counting, according to the first soft bit information, a total number of memory cells in the first memory cell whose threshold voltage belongs to the first steady state region, wherein the first steady state region includes the first test voltage An area outside the region between the voltage level of the voltage in the level and the voltage level at which the voltage is the smallest; and the threshold voltage in the first memory cell belongs to the second steady state according to the information of the second soft bit information a total number of memory cells of the region, wherein the second steady state region includes a region outside a region between a voltage level at which the voltage is the highest in the second test voltage level and a voltage level at which the voltage is the smallest.

In an exemplary embodiment of the present invention, the first test voltage level corresponds to a first offset value, and the second test voltage level corresponds to a second offset value, where the first offset value is different And the second offset value, wherein the operation of the memory control circuit unit to update the preset hard decision voltage level according to the first evaluation parameter and the second evaluation parameter comprises: according to the first Updating the preset hard decision voltage level by a numerical relationship between the total number and the second total number, wherein the updated preset hard decision voltage level corresponds to the first offset value and the first One of the two offset values.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to update the preset soft decision voltage level according to the numerical relationship between the first total number and the second total number. And the updated preset soft decision voltage level corresponds to one of the first offset value and the second offset value.

Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module including a plurality of memory cells, wherein the memory control circuit unit includes a host interface and a memory. Body interface, error checking and correction circuit and memory management circuit. The host interface is configured to be coupled to a host system. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface, the memory interface, and the error checking and correcting circuit, and the memory management circuit is configured to send a first read instruction sequence to indicate a preset hard decision Reading, by the voltage level, a plurality of first memory cells in the memory cell to obtain hard bit information, wherein the error checking and correction circuit is configured to perform a hard decoding operation on the hard bit information, if the hard decoding If the operation fails, the memory management circuit is further configured to send a second read instruction sequence to instruct the first memory cell to read the soft bit information based on the plurality of preset soft decision voltage levels, the error check And the correction circuit is further configured to perform a soft decoding operation on the soft bit information. If the soft decoding operation fails, the memory management circuit is further configured to send a first test instruction sequence to indicate that the first test voltage is based on the plurality of first test voltages. Reading the first memory cell to obtain first soft bit information and transmitting a second test instruction sequence to indicate that the first memory cell is read based on the plurality of second soft decision voltage levels to obtain a second Bit information, wherein the memory management circuit is further configured to obtain a first evaluation parameter according to the first soft bit information and obtain a second evaluation parameter according to the second soft bit information, wherein the first evaluation The parameter corresponds to a first total number of memory cells in the first memory cell that meet the first state condition, wherein the second evaluation parameter corresponds to a second of the first memory cells that meet the second state condition The memory management circuit is further configured to update the preset hard decision voltage level according to the first evaluation parameter and the second evaluation parameter.

In an exemplary embodiment of the present invention, the memory management circuit obtains the first evaluation parameter according to the first soft bit information and obtains the second evaluation parameter according to the second soft bit information. The operation includes: counting, according to the first soft bit information, a total number of memory cells in the first memory cell that belong to the first transition region, wherein the first transition region includes the first test voltage An area between any two of the voltage levels; and counting, based on the second soft bit information, a total number of memory cells in the first memory cell that belong to the second transition region, wherein the second The transition region includes an area between any two of the second test voltage levels.

In an exemplary embodiment of the present invention, the first transition region is a voltage level at which the voltage of the first test voltage level is the highest and a voltage level at which the voltage of the first test voltage level is the smallest. An area between the second transition state is a region between a voltage level at which the voltage of the second test voltage level is the highest and a voltage level at which the voltage of the second test voltage level is the smallest.

In an exemplary embodiment of the present invention, the memory management circuit obtains the first evaluation parameter according to the first soft bit information and obtains the second evaluation parameter according to the second soft bit information. The operation includes: counting, according to the first soft bit information, a total number of memory cells in the first memory cell that belong to the first steady state region, wherein the first steady state region includes the first test voltage An area outside the region between the voltage level at which the voltage is the highest and the voltage level at which the voltage is the smallest; and the threshold voltage in the first memory cell belongs to the second steady region according to the information of the second soft bit information a total number of memory cells, wherein the second steady state region includes a region outside a region between a voltage level at which the voltage is the highest in the second test voltage level and a voltage level at which the voltage is the smallest.

In an exemplary embodiment of the present invention, the first steady-state region is located outside a region between a voltage level at which the voltage is the largest and a voltage level at which the voltage is the smallest in the first test voltage level, wherein the The second steady state region is located outside the region between the voltage level at which the voltage is the highest in the second test voltage level and the voltage level at which the voltage is the smallest.

In an exemplary embodiment of the present invention, the first test voltage level corresponds to a first offset value, and the second test voltage level corresponds to a second offset value, where the first offset value is different And the operation of the memory management circuit to update the preset hard decision voltage level according to the first evaluation parameter and the second evaluation parameter, according to the second offset value, according to the first total a numerical relationship between the second total number to update the preset hard decision voltage level, wherein the updated preset hard decision voltage level corresponds to the first offset value and the second offset One of the values of the shift.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to update the preset soft decision voltage level according to the numerical relationship between the first total number and the second total number. The updated preset soft decision voltage level corresponds to one of the first offset value and the second offset value.

Based on the above, after the soft decoding process fails, at least two sets of test voltage levels are used to read the same memory cell. A corresponding plurality of evaluation parameters are then obtained, wherein each of the evaluation parameters corresponds to the total number of memory cells in the memory cell that meet certain state conditions. Based on these evaluation parameters, the preset hard decision voltage level can be updated. Thereby, the decoding efficiency can be improved.

The above described features and advantages of the invention will be apparent from the following description.

In general, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). Typically, the memory storage device is used with a host system to enable the host system to write data to or from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention.

Referring to FIG. 1 and FIG. 2, the host system 11 generally includes a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 are all coupled to the system bus 110.

In the exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 can store data to or from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 is coupled to the I/O device 12 through the system bus bar 110. For example, host system 11 can transmit output signals to or receive input signals from I/O device 12 via system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. The motherboard 20 can be coupled to the memory storage device 10 via a data transmission interface 114 via a wired or wireless connection. The memory storage device 10 can be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory. A memory storage device based on various wireless communication technologies, such as a storage device (for example, iBeacon). In addition, the motherboard 20 can also be coupled to the Global Positioning System (GPS) module 205, the network interface card 206, the wireless transmission device 207, the keyboard 208, the screen 209, the speaker 210, etc. through the system bus bar 110. I/O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is any system that can substantially cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is illustrated by a computer system, FIG. 3 is a schematic diagram of the host system and the memory storage device according to another exemplary embodiment of the present invention. Referring to FIG. 3, in another exemplary embodiment, the host system 31 can also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 can be used for Various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 are used. The embedded storage device 34 includes an embedded multimedia card (embedded MMC) 341 and/or an embedded multi-chip package (eMCP) storage device 342 and the like, and directly couples the memory module to the host system. Embedded storage device on the substrate.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.

Referring to FIG. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable non-volatile memory module 406.

In the present exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394. Standard, high-speed Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface Standard, Ultra High Speed II (UHS-II) interface standard, Memory Stick (MS) interface standard, Multi-Chip Package interface standard, Multimedia Memory Card (Multi Media Card) , MMC) interface standard, eMMC interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standard. The connection interface unit 402 can be packaged in a wafer with the memory control circuit unit 404, or the connection interface unit 402 can be disposed outside a wafer including the memory control circuit unit 404.

The memory control circuit unit 404 is configured to execute a plurality of logic gates or control commands implemented in a hard type or a firmware type and perform data in the rewritable non-volatile memory module 406 according to an instruction of the host system 11. Write, read, and erase operations.

The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and is used to store data written by the host system 11. The rewritable non-volatile memory module 406 can be a single-level memory cell (SLC) NAND-type flash memory module (ie, one memory cell can store one bit of flash memory) Module), Multi Level Cell (MLC) NAND flash memory module (ie, a flash memory module that can store 2 bits in a memory cell), and complex memory cells ( Triple Level Cell, TLC) NAND flash memory module (ie, a flash memory module that can store 3 bits in a memory cell), other flash memory modules, or other memory with the same characteristics Body module.

Each of the memory cells of the rewritable non-volatile memory module 406 stores one or more bits in response to a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage is also referred to as "writing data to the memory cell" or "stylized memory cell". As the threshold voltage changes, each of the memory cells of the rewritable non-volatile memory module 406 has a plurality of storage states. By applying the read voltage, it can be determined which storage state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the invention.

Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, and an error check and correction circuit 508.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and when the memory storage device 10 operates, such control commands are executed to perform operations such as writing, reading, and erasing of data. The operation of the memory management circuit 502 will be described below, which is equivalent to the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in a firmware version. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and such control instructions are programmed into the read-only memory. When the memory storage device 10 is in operation, such control commands are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control command of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 (for example, the memory module is dedicated to storing system data). In the system area). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit first executes the boot code to store the rewritable non-volatile memory. The control commands in the body module 406 are loaded into the random access memory of the memory management circuit 502. After that, the microprocessor unit will run these control commands to perform data writing, reading and erasing operations.

In addition, in another exemplary embodiment, the control command of the memory management circuit 502 can also be implemented in a hardware format. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells of the rewritable non-volatile memory module 406 or a group thereof. The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable non-volatile memory module 406 to obtain target data from the rewritable non-volatile memory module 406. The memory erase circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406. The data processing circuit is configured to process data to be written to the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may each include one or more code codes or instruction codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding writes and reads. Take the erase and other operations. In an exemplary embodiment, the memory management circuit 502 can also provide other types of instruction sequences to the rewritable non-volatile memory module 406 to indicate that the corresponding operations are performed.

The host interface 504 is coupled to the memory management circuit 502 and is configured to receive and identify instructions and data transmitted by the host system 11. That is to say, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the present exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, and the MS standard. , MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.

The memory interface 506 is coupled to the memory management circuit 502 and is used to access the rewritable non-volatile memory module 406. That is, the data to be written to the rewritable non-volatile memory module 406 is converted to a format acceptable to the rewritable non-volatile memory module 406 via the memory interface 506. Specifically, if the memory management circuit 502 is to access the rewritable non-volatile memory module 406, the memory interface 506 will transmit a corresponding sequence of instructions. For example, the sequences of instructions may include a sequence of write instructions indicating write data, a sequence of read instructions indicating target data, a sequence of erase instructions indicating erased material, and instructions for indicating various memory operations (eg, changing reads) The corresponding instruction sequence of the voltage level or the garbage collection procedure, etc.). These sequences of instructions are generated, for example, by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 via the memory interface 506. These sequences of instructions may include one or more signals or data on the bus. These signals or materials may include instruction codes or code. For example, in the read command sequence, information such as the read identification code, the memory address, and the like are included.

The error checking and correction circuit 508 is coupled to the memory management circuit 502 and is used to perform error checking and correction procedures to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error check and correction circuit 508 generates a corresponding error correcting code (ECC) for the data corresponding to the write command. And/or error detecting code (EDC), and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correction code and/or error check code to the rewritable non-volatile In the memory module 406. Thereafter, when the memory management circuit 502 reads the target data from the rewritable non-volatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error check and correction circuit 508 An error check and correction procedure is performed on the read data based on the error correction code and/or the error check code.

In the present exemplary embodiment, the error checking and correction circuit 508 performs encoding and decoding of data using a low density parity code (LDPC). However, in another exemplary embodiment, the error checking and correction circuit 508 may also perform encoding and decoding of data using various codes such as a BCH code, a convolutional code, or a turbo code. It is common knowledge for those skilled in the art to perform encoding and decoding of data using any of the above codes, and thus will not be described herein.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510 and a power management circuit 512.

The buffer memory 510 is coupled to the memory management circuit 502 and is used to temporarily store data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10.

FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the invention. It must be understood that when describing the operation of the physical unit of the rewritable non-volatile memory module 406, the operation of the physical unit with the words "select" and "group" is a logical concept. That is, the actual location of the physical unit of the rewritable non-volatile memory module 406 is not changed, but the physical unit of the rewritable non-volatile memory module 406 is logically operated.

In the present exemplary embodiment, the memory cells of the rewritable non-volatile memory module 406 constitute a plurality of physical stylized units, and the physical stylized units constitute a plurality of physical erasing units. Specifically, the memory cells on the same word line form one or more entity stylized units. If each memory cell can store more than 2 bits, the entity stylized units on the same word line can be classified into at least a lower entity stylized unit and an upper physical stylized unit. For example, a Least Significant Bit (LSB) of a memory cell belongs to a lower entity stylized unit, and a Most Significant Bit (MSB) of a memory cell belongs to an upper entity stylized unit. In general, in MLC NAND flash memory, the write speed of the lower stylized unit will be greater than the write speed of the upper stylized unit, and / or the reliability of the lower stylized unit is higher than the upper The reliability of the entity stylized unit.

In this exemplary embodiment, the physical stylized unit is the smallest unit that is stylized. That is, the entity stylized unit is the smallest unit that writes data. For example, an entity stylized unit is a physical page or a sector. If the entity stylized unit is a physical page, then the entity stylized units typically include a data bit area and a redundancy bit field. The data bit area contains a plurality of physical fans for storing user data, and the redundant bit area is used for storing system data (for example, error correction codes). In this exemplary embodiment, the data bit area includes 32 physical fans, and one physical fan has a size of 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or a greater or lesser number of solid fans, and the size of each of the physical fans may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erase. That is, each physical erase unit contains one of the smallest number of erased memory cells. For example, the physical erase unit is a physical block.

Referring to FIG. 6, the memory management circuit 502 logically groups the physical units 610(0)-610(B) of the rewritable non-volatile memory module 406 into a storage area 601 and a replacement area 602. The physical units 610(0)-610(A) in the storage area 601 are used to store data, and the physical units 610(A+1)~610(B) in the replacement area 602 are used to replace the damage in the storage area 601. Physical unit. For example, the replacement of a physical unit is in units of one physical erase unit. In the present exemplary embodiment, each of the physical units 610(0)-610(B) refers to at least one physical stylized unit. Alternatively, in another exemplary embodiment, each of the physical units 610(0)-610(B) may also include any number of memory cells.

The memory management circuit 502 configures the logic units 612(0)-612(C) to map at least a portion of the physical units 610(0)-610(A) in the storage area 601. In the present exemplary embodiment, the host system 11 accesses the data in the storage area 601 through a logical address (LA). Therefore, each of the logical units 612(0) to 612(C) is Refers to a logical address. However, in another exemplary embodiment, each of the logic units 612(0)-612(C) may also refer to a logical stylized unit, a logical erase unit, or a plurality of consecutive or discontinuous The logical address is composed, depending on the actual needs. Moreover, each of logic units 612(0)-612(C) can be mapped to one or more physical units.

In the present exemplary embodiment, the memory management circuit 502 records the mapping relationship (also referred to as a logical-entity mapping relationship) between the logical unit and the physical unit in at least one logical-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data storage for the memory storage device 10 according to the logical-entity mapping table. take.

FIG. 7 is a schematic diagram of reading hard bit information according to an exemplary embodiment of the invention. This exemplary embodiment is an example of a SLC NAND type flash memory in which the horizontal axis represents the threshold voltage of the memory cell and the vertical axis represents the number of memory cells. However, in another exemplary embodiment, FIG. 7 can also be used to represent a threshold voltage distribution of a portion of an MLC NAND or TLC NAND type flash memory.

Referring to FIG. 7, after a plurality of memory cells (hereinafter also referred to as first memory cells) in the programmable rewritable non-volatile memory module 406, the threshold voltage of each memory cell to be programmed belongs to One of the distributions 710 and 720. For example, if a memory cell is used to store the bit "1", the threshold voltage of the memory cell will fall in the distribution 710; and if a memory cell is used to store the bit "0", the memory cell The threshold voltage will fall on the distribution 720.

It is worth mentioning that in the present exemplary embodiment, each memory cell is used to store one bit, so there are two possibilities for the distribution of threshold voltages of such memory cells (for example, distributions 710 and 720). However, in other exemplary embodiments, if a memory cell is used to store a plurality of bits, there may be four corresponding threshold voltage distributions (for example, MLC NAND type flash memory) and eight types (for example, , TLC NAND type flash memory) or any other possibility. Moreover, the invention does not limit the bits represented by each of the distributions. For example, in another exemplary embodiment of FIG. 7, distribution 710 is representative of bit "0" and distribution 720 is representative of bit "1."

Generally, in order to read the data stored by the first memory cells, the memory management circuit 502 sends a read command sequence (hereinafter also referred to as a first read command sequence) to a rewritable non-volatile Memory module 406. The first sequence of read instructions is used to indicate that data is read from the physical addresses of the first memory cells based on a voltage level. In an exemplary embodiment, this voltage level is also referred to as a preset hard decision voltage level. In accordance with this reading instruction sequence, rewritable non-volatile memory module 406 will apply a read voltage (e.g., voltage level V _H1) to the first memory cell and transmits the obtained data to the memory management circuitry 502. For example, the voltage level V _{H1 is} the preset hard decision voltage level. If the threshold voltage of a certain memory cell is less than the applied voltage level V _H1 (for example, the threshold voltage belongs to the memory cell of the distribution 710), the memory management circuit 502 reads the bit "1"; if a memory cell The threshold voltage is greater than the applied voltage level V _H1 (eg, the threshold voltage belongs to the memory cell of the distribution 720), and the memory management circuit 502 reads the bit "0".

However, as the time and/or loss of usage of the rewritable non-volatile memory module 406 increases, memory cells in the rewritable non-volatile memory module 406 may experience degradation. For example, after the memory cells belonging to the distributions 710 and 720 have a performance degradation, the distributions 710 and 720 may gradually approach each other or even overlap each other. For example, distributions 711 and 721 in FIG. 7 are used to represent distributions 710 and 720 after performance degradation, respectively. After the performance degradation occurs, if the first memory cells are continuously used to store data and the same preset hard decision voltage level (for example, voltage level V _H1 ) is used to read the first memory cells, read The information you arrive may contain many errors. Taking the distributions 711 and 721 in FIG. 7 as an example, the memory cells in the oblique line region still belong to the distribution 711, but the threshold voltage thereof is higher than the voltage level V _H1 . Therefore, if the first memory cells are continuously read using the voltage level V _H1 , some of the memory cells that actually store the bit "1" (for example, the memory cells in the oblique region in the distribution 711) are misjudged as The bit "0" is stored.

Therefore, after reading the data by presetting the hard decision voltage level (eg, voltage level V _H1 ), the error checking and correction circuit 508 decodes the data to attempt to correct errors that may exist in the data. Here, the data read by the hard decision voltage level is also referred to as hard bit information (for example, the hard bit HB _{1 of} FIG. 7), and the operation of decoding the hard bit information is also referred to as a hard decoding operation. Those skilled in the art will appreciate how the error checking and correction circuit 508 can perform hard decoding operations using low density parity check codes or the like, and what hardware structure the error checking and correction circuit 508 needs to accomplish to perform the hard decoding operations required to perform. . For example, a hard decoding operation may include a parity check operation for generating a syndrome and a bit flipping algorithm for determining error bits, a minimum sum-sum calculation. Method and/or sum-product algorithm, etc. Error checking and correction circuit 508 then determines if the hard decoding operation performed was successful (or failed). If the hard decoding operation is successful (e.g., all errors in the data are corrected), the error checking and correction circuit 508 outputs the decoded data. If the hard decoding operation fails (e.g., the error in the material cannot be completely corrected), the error checking and correction circuit 508 enters the soft decoding mode.

In the soft decoding mode, the memory management circuit 502 transmits another read command sequence (hereinafter also referred to as a second read command sequence) to indicate reading from the first memory cells based on the plurality of voltage levels. data. In an exemplary embodiment, the voltage levels are also referred to as preset soft decision voltage levels. For example, such preset soft decision voltage levels may correspond to preset hard decision voltage levels previously used. According to the second read command sequence, the rewritable non-volatile memory module 406 sequentially applies a plurality of read voltages to the first memory cells and returns the obtained data to the memory management circuit 502.

FIG. 8 is a schematic diagram of reading soft bit information according to an exemplary embodiment of the invention.

Referring to FIG. 8 , following the example embodiment of FIG. 7 , in the soft decoding mode, the rewritable non-volatile memory module 406 is based on a plurality of preset soft decision voltage levels (eg, voltage level V _{S1 ).} ~V _S5 ) to sequentially read the first memory cells and return the obtained data. The voltage levels V _S1 ~V _S5 can be used in any order. After reading the first memory cell to a certain person based on the voltage level V _S1 ~ V _S5, if this threshold voltage of the memory cell is less than the voltage value of the minimum voltage level V _S4 (i.e., in the region of 801), data "11111" or "100" will be returned; if the threshold voltage of the memory cell is between the voltage level V _S4 and the voltage level V _S2 (ie located in the area 802), the data "01111" or "101" will be If the threshold voltage of the memory cell is between the voltage level V _S2 and the voltage level V _S1 (ie, located in the area 803), the data "00111" or "111" will be returned; if the memory cell The threshold voltage is between the voltage level V _S1 and the voltage level V _S3 (ie, located in the region 804), and the data "00011" or "011" is returned; if the threshold voltage of the memory cell is between the voltage level V Between _S3 and the voltage level V _S5 (ie, in the region 805), the data "00001" or "001" is returned; and if the threshold voltage of the memory cell is higher than the voltage level V _{S5 having the} highest voltage value (ie, Located in area 806), the data "00000" or "000" will be returned.

In an exemplary embodiment, one of the preset soft decision voltage levels (eg, voltage level V _{S3 in} FIG. 8 ) may be equal to or close to a predetermined hard decision voltage level (eg, FIG. 7 ) The voltage level in V _H1 ). The voltage difference between any two adjacent preset soft decision voltage levels may be the same preset value. In addition, the total number of preset soft decision voltage levels may also be more (eg, 7 or 9 etc.) or less (eg, 3).

After reading the data by preset soft decision voltage levels (eg, voltage levels V _S1 ~V _S5 ), error checking and correction circuit 508 decodes the data to attempt to correct possible errors in the data. Here, the data read by the plurality of soft decision voltage levels is also referred to as soft bit information (for example, the soft bit information 831 including the soft bits SB ₁ to SB ₅ in FIG. 8 or a partial soft bit) The soft bit information 832) generated by the logical operation of the element, and the operation of decoding the soft bit information is also referred to as a soft decoding operation. Those skilled in the art will appreciate how the error checking and correction circuit 508 can perform soft decoding operations using low density parity check codes or the like, and what hardware structure the error checking and correction circuit 508 needs to have to perform the soft decoding operations required to perform. . For example, the soft decoding operation may further include operations to update channel information such as log likelihood ratio (LRR). Moreover, the soft decoding operation may include decoding operations that are the same or different from at least a portion of the hard decoding operation.

In particular, relative to the hard bit information, since the soft bit information corresponding to each memory cell can provide more channel information, the error correction capability of the soft decoding operation tends to be higher than the error correction capability of the hard decoding operation. Error checking and correction circuit 508 then determines if the executed soft decoding operation was successful (or failed). If the soft decoding operation is successful (e.g., all errors in the data are corrected), the error checking and correction circuit 508 outputs the decoded data.

If the soft decoding operation still fails (eg, the error in the data still cannot be completely corrected), the memory management circuit 502 sends a plurality of test instruction sequences to indicate that the first memory cell is read based on the plurality of test voltage groups. Corresponding soft bit information. Each test voltage group includes a plurality of test voltage levels, and each test voltage group (or test voltage level therein) corresponds to an offset value. This offset value is, for example, recorded in a lookup table and used to shift the preset hard decision voltage level (or preset soft decision voltage level) to generate a corresponding test voltage group. In addition, the total number of test voltage levels in each test voltage group is the same.

Based on the obtained soft bit information, the memory management circuit 502 obtains a plurality of evaluation parameters. Each evaluation parameter corresponds to the total number of memory cells in the first memory cell that meet a particular state condition. Based on such evaluation parameters, the memory management circuit 502 updates the preset hard decision voltage level. For example, in the exemplary embodiment of FIG. 7, according to such evaluation parameters, the preset hard decision voltage level may be updated from the voltage level V _H1 to the voltage level V _H2 . It can be seen from Fig. 7 that the error contained in the data read based on the voltage level V _H2 (for example, the total number of error bits) has a relatively high probability that it is significantly less than that read based on the voltage level V _H1 . The error contained in the data. In addition, the operation of updating the preset hard decision voltage level from the voltage level V _H1 to the voltage level V _H2 can also be regarded as an operation of tracking the optimal read voltage level. In addition, the preset soft decision voltage level can also be updated corresponding to updating the preset hard decision voltage level. For example, based on the plurality of evaluation parameters obtained, a plurality of test voltage levels in a test voltage group corresponding to an offset value may be set to a new preset soft decision voltage level.

9A-9C are schematic diagrams of tracking an optimal read voltage level, according to an exemplary embodiment of the invention.

Referring to FIG. 9A, after the soft decoding operation fails, the memory management circuit 502 obtains an offset value according to the lookup table and obtains a plurality of test voltage levels belonging to a certain test voltage group according to the offset value (for example, Voltage level V _{C1_1} ~V _{C1_5} ). Relative to the preset test voltage level (eg, voltage levels V _S1 ~ V _S5 ), the test voltage levels (eg, voltage _levels V _{C1_1} ~ V _{C1_5} ) obtained from the offset values are respectively on the horizontal axis. Shift + Δ to the right. For example, the voltage _levels V _{C1_1 VV C1_5} are increased by a voltage value of Δ(mV) with respect to the voltage _levels V _S1 VV _S5 , respectively. The memory management circuit 502 sends a sequence of test instructions to indicate that the first memory cell is read based on the voltage _levels V _{C1_1} ~ V _{C1_5} . The memory management circuit 502 then obtains the corresponding soft bit information 931 (or soft bit information 932).

Based on the soft bit information 931 (or soft bit information 932), the memory management circuit 502 counts the total number of memory cells in the first memory cell whose threshold voltage belongs to a transition state region. Wherein, the transition region includes a region between any two of the voltage _levels V _{C1_1 VV C1_5} . In the present exemplary embodiment, the transition region refers to the region R _T1 between the voltage of the test voltage group (ie, the voltage level V _{C1_5} ) and the voltage minimum (ie, the voltage level V _{C1_4} ). Alternatively, in another exemplary embodiment, the transition region may also refer to a region R _{T1 '} between the voltage _levels V _{C1_2} and V _{C1_3} . For example, the memory management circuit 502 can count the total number of memory cells corresponding to the soft bit information "101", "111", "011", and "001" to obtain the total number of memory cells whose threshold voltage belongs to the region R _T1 . Alternatively, the memory management circuit 502 may also count the total number of memory cells corresponding to the soft bit information "111" and "011" to obtain the total number of memory cells whose threshold voltage belongs to the region R _{T1 '} . The memory management circuit 502 then records the calculated total or a corresponding value as an evaluation parameter corresponding to the test voltage group (or offset value + Δ).

Referring to FIG. 9B, the memory management circuit 502 obtains another offset value according to the lookup table and obtains a plurality of test voltage levels belonging to a certain test voltage group according to the offset value (for example, the voltage level V _{C2_1} ~ V _{C2_5} ). With respect to the voltage _levels V _S1 VV _S5 , the voltage _levels V _{C2_1 VV C2_5} are shifted to the right by +2 _Δ on the horizontal axis. For example, the voltage _levels V _{C2_1 VV C2_5} are increased by a voltage value of 2 Δ (mV) with respect to the voltage _levels V _S1 VV _S5 , respectively. The memory management circuit 502 sends a sequence of test instructions to indicate that the first memory cell is read based on the voltage _levels V _{C2_1} ~ V _{C2_5} . The memory management circuit 502 then obtains the corresponding soft bit information 941 (or soft bit information 942).

Based on the soft bit information 941 (or soft bit information 942), the memory management circuit 502 counts the total number of memory cells in the first memory cell whose threshold voltage belongs to a transition region. Wherein, the transition region includes a region between any two of the voltage _levels V _{C2_1} ~ V _{C2_5} . In the present exemplary embodiment, the memory management circuit 502 counts the total number of memory cells corresponding to the soft bit information "101", "111", "011", and "001" to obtain the threshold voltage belonging to the region R _T2 (ie, The total number of memory cells between voltage _levels V _{C2_4} and V _{C2_5} ). Alternatively, in another exemplary embodiment, the memory management circuit 502 counts the total number of memory cells corresponding to the soft bit information "111" and "011" to obtain a threshold voltage falling at the voltage _levels V _{C2_2} and V _{C2_3} . The total number of memory cells between. The memory management circuit 502 then records the calculated total or a corresponding value as an evaluation parameter corresponding to the test voltage group (or offset value +2 Δ).

Referring to FIG. 9C, the memory management circuit 502 can further obtain another offset value according to the lookup table and obtain a plurality of test voltage levels belonging to a certain test voltage group according to the offset value (for example, the voltage level V _{C3_1} ~V _{C3_5} ). With respect to the voltage _levels V _S1 VV _S5 , the voltage _levels V _{C3_1 VV C3_5} are shifted to the right by +3 _Δ on the horizontal axis. For example, the voltage _levels V _{C3_1 VV C3_5} are increased by a voltage value of 3 Δ (mV) with respect to the voltage _levels V _S1 VV _S5 , respectively. The memory management circuit 502 sends a sequence of test instructions to indicate that the first memory cell is read based on the voltage _levels V _{C3_1} ~ V _{C3_5} and the corresponding soft bit information 951 (or soft bit information 952) is obtained.

Based on the soft bit information 951 (or soft bit information 952), the memory management circuit 502 again counts the total number of memory cells in the first memory cell whose threshold voltage belongs to a transition region. Wherein, the transition region includes a region between any two of the voltage _levels V _{C3_1 VV C3_5} . In the present exemplary embodiment, the memory management circuit 502 counts the total number of memory cells corresponding to the soft bit information "101", "111", "011", and "001" to obtain the threshold voltage belonging to the region R _T3 (ie, the total number of memory cells of the region between the voltage level _V C3_4 _V C3_5) a. Alternatively, in another exemplary embodiment, the memory management circuit 502 counts the total number of memory cells corresponding to the soft bit information "111" and "011" to obtain a threshold voltage falling at the voltage _levels V _{C3_2} and V _{C3_3} . The total number of memory cells between. The memory management circuit 502 then records the calculated total or a corresponding value as an evaluation parameter corresponding to the test voltage group (or offset value +3 Δ). And so on, corresponding to more test voltage groups (or offset values +4 Δ, -Δ, -2 Δ, etc.), more evaluation parameters can also be determined.

The memory management circuit 502 updates the preset hard decision voltage level based on the numerical relationship between the obtained evaluation parameters. For example, if the values of the evaluation parameters are positively correlated to the respective totals, the memory management circuit 502 compares the plurality of evaluation parameters obtained and selects the offset values corresponding to the smallest of the evaluation parameters. The memory management circuit 502 then updates the preset hard decision voltage level based on the selected offset value.

FIG. 10A is a schematic diagram showing the correspondence between the number of memory cells and an offset value according to an exemplary embodiment of the invention.

Referring to FIG. 10A, in the exemplary embodiment of FIG. 7 to FIG. 9C, the total number of memory cells whose threshold voltage belongs to the transition region R _T1 is N ₁ , and the total number of memory cells whose threshold voltage belongs to the transition region R _T2 is N _{2 .} And the total number of memory cells whose threshold voltage belongs to the transition region R _T3 is N ₃ . N ₁ corresponds to the offset value + Δ, N ₂ corresponds to the offset value + ₂ Δ, and N ₃ corresponds to the offset value + ₃ Δ. 9A, 9B, and 9C, N ₁ will be greater than N ₂ and N ₂ will be greater than N ₃ . Thus, the memory management circuit 502 may be voltage level V _H1 plus 3Δ obtained voltage level V _H2. In addition, in an exemplary embodiment, the memory management circuit 502 can also directly set the voltage level V _{C3_1} to the voltage level V _H2 .

In an exemplary embodiment, the memory management circuit 502 can also count the total number of memory cells in the first memory cell whose threshold voltage belongs to a stable state region. Wherein, the steady state region includes an area outside the region between the largest voltage group and the lowest voltage group in a certain test voltage group. In particular, in a plurality of regions divided by test voltage levels in the same test voltage group, the steady state region does not overlap with the transition region. For example, in an exemplary embodiment of FIG. 9A, the steady state region refers to a region R _S1 other than region R _T1 . Alternatively, in another exemplary embodiment of FIG. 9A, the steady state region refers to a region R _{S1 '} other than the region R _{T1 ′} . In addition, in another exemplary embodiment of FIG. 9A, the transition region and the steady state region divided by the same test voltage group may also be the region R _{T1 ′} and the region R _{S1 , respectively} . Therein, there is a gap between the region R _T1′ and its left and right regions R _S1 , respectively, rather than being continuous. The memory management circuit 502 can count the total number of memory cells whose threshold voltage belongs to the region R _S1 (or the region R _{S1 '} ) and determine the corresponding evaluation parameters. For example, in an exemplary embodiment of FIG. 9B, the steady state region refers to region R _S2 other than region R _T2 . The memory management circuit 502 can count the total number of memory cells whose threshold voltage belongs to the region R _S2 and determine the corresponding evaluation parameters. For example, in an exemplary embodiment of FIG. 9C, the steady state region refers to region R _S3 other than region R _T3 . The memory management circuit 502 can count the total number of memory cells whose threshold voltage belongs to the region R _S3 and determine the corresponding evaluation parameters. The memory management circuit 502 can then update the preset hard decision voltage level based on the numerical relationship between the evaluation parameters. For example, if the values of the evaluation parameters are positively correlated with the respective totals, the memory management circuit 502 compares the obtained plurality of evaluation parameters and selects an offset value corresponding to the largest of the evaluation parameters. The memory management circuit 502 then updates the preset hard decision voltage level based on the selected offset value. In addition, the area division manner of FIG. 9A can also be applied to FIGS. 9B and 9C, and the present invention is not limited thereto.

FIG. 10B is a schematic diagram showing the correspondence between the number of memory cells and an offset value according to another exemplary embodiment of the present invention.

Referring to FIG. 10B, in another exemplary embodiment of FIG. 7 to FIG. 9C, the total number of memory cells whose threshold voltage belongs to the steady-state region R _S1 is N _{1 ′} , and the threshold voltage belongs to the total number of memory cells of the steady-state region R _S2 . The total number of memory cells that are N _{2 '} and whose threshold voltage belongs to the steady-state region R _S3 is N _{3 '} . N _{1 '} corresponds to the offset value + Δ, N _{2 '} corresponds to the offset value + ₂ Δ, and N _{3 '} corresponds to the offset value + ₃ Δ. Since N _{1 ' is} negatively related to N ₁ , N _{2 ' is} negatively related to N ₂ , and N _{3 ' is} negatively related to N ₃ , N _{3 '} is greater than N _{2 '} and N _{2 '} is greater than N _{1 '} . Thus, the memory management circuit 502 may be the same voltage level V _H1 plus 3Δ obtained voltage level V _H2.

After updating the preset hard decision voltage level, the memory management circuit 502 sends a read command sequence to instruct to read the first memory cell based on the updated preset hard decision voltage level to obtain the corresponding hard bit. News. For example, referring again to FIG. 7, the rewritable non-volatile memory module 406 reads the first memory cell based on the voltage level V _H2 and returns the hard bit information including the hard bit HB ₂ . The error in the hard bit information read based on the voltage level V _H2 can be significantly reduced compared to the hard bit information read based on the voltage level V _H1 . The error checking and correction circuit 508 then performs a hard decoding operation on the hard bit information and determines whether the decoding was successful. If the decoding is successful, the error checking and correction circuit 508 outputs the decoded data. If the decoding fails, the error checking and correction circuit 508 will enter the soft decoding mode again.

In the soft decoding mode, the memory management circuit 502 sends a read command sequence to instruct to read the first memory cell based on the updated plurality of preset soft decision voltage levels to obtain corresponding soft bit information. For example, in the exemplary embodiment of FIGS. 9A-9C, the updated preset soft decision voltage level may include all or at least one of the voltage _levels V _{C3_1 VV C3_5} in FIG. 9C. The rewritable non-volatile memory module 406 reads the first memory cell and returns the corresponding soft bit information based on the updated plurality of preset soft decision voltage levels. Error checking and correction circuit 508 then performs a soft decoding operation on this soft bit information and determines if the decoding was successful. If the soft decoding operation is successful, the error checking and correction circuit 508 outputs the decoded data. If the soft decoding operation fails, the error checking and correction circuit 508 determines that the decoding has failed.

FIG. 11 is a schematic diagram of a transition region and a steady state region according to an exemplary embodiment of the invention.

Referring to FIG. 11, for the TLC NAND type flash memory, the threshold voltage distribution of the first memory cell may include the distributions 1101 to 1108. The memory cells belonging to the distributions 1101 to 1108 are used to store the bytes "111", "011", "001", "000", "010", "110", "100", and "101", respectively. For the lower entity stylized unit 1110 containing such memory cells (ie, the physical unit considered to be the first bit in the stored byte), the transition region includes regions R _T11 and R _T12 , and the steady state The area includes areas R _S11 and R _S12 . For the upper physical stylization unit 1120 (ie, the physical unit considered to be the second bit in the storage byte) including the memory cells, the transition region includes regions R _T13 , R _{T14 ,} and R _T15 . The steady state region includes regions R _S13 , R _{S14 ,} and R _S15 . For an extra entity stylization unit 1130 (ie, a physical unit considered to be the third bit in the storage byte) containing such memory cells, the transition region includes regions R _T16 and R _T17 , The steady state region includes regions R _S16 and R _S17 .

In the exemplary embodiment of FIG. 11, each of the transition regions (eg, region R _T11 ) and the corresponding steady state region (eg, region R _S11 ) may have upper and lower limits of the threshold voltage. It is worth mentioning that the distributions 711 and 721 in FIGS. 7 to 9C can also be regarded as any two adjacent distributions in FIG. 11 (for example, distributions 1101 and 1102 or 1102 and 1103, etc.). In addition, since each transition region and the corresponding steady-state region are divided based on the applied test voltage level, according to different test voltage groups, each transition region divided in FIG. 11 and corresponding stable The state area may move to the left, move to the right, widen or narrow, and so on. Moreover, in accordance with the exemplary embodiment of FIG. 11, those of ordinary skill in the art will also be aware of how to base a particular test voltage in the threshold voltage distribution of other types of flash memory (eg, MLC NAND type flash memory). The group divides the corresponding transition region and steady state region, and will not be described here.

FIG. 12 is a flowchart of a decoding method according to an exemplary embodiment of the present invention.

Referring to FIG. 12, in step S1201, a plurality of first memory cells are read based on a preset hard decision voltage level to obtain hard bit information and perform a hard decoding operation on the hard bit information. In step S1202, it is determined whether the hard decoding operation is successful (or failed). If the hard decoding operation is successful, in step S1203, the decoded codeword is output. If the hard decoding operation fails, in step S1204, the first memory cell is read based on the plurality of preset soft decision voltage levels to obtain soft bit information and perform soft decoding operation on the soft bit information. In step S1205, it is determined whether the soft decoding operation is successful (or failed). If the soft decoding operation is successful, in step S1203, the decoded codeword is output. If the soft decoding operation fails, in step S1206, the first memory cell is read based on the plurality of first test voltage levels to obtain the first soft bit information, and the first memory cell is read based on the plurality of second test voltage levels. Obtain the second soft bit information. In step S1207, a first evaluation parameter is obtained according to the first soft bit information and a second evaluation parameter is obtained according to the second soft bit information. In step S1208, the preset hard decision voltage level is updated according to the first evaluation parameter and the second evaluation parameter.

FIG. 13 is a flowchart of a decoding method according to another exemplary embodiment of the present invention.

Referring to FIG. 13, in step S1301, a plurality of first memory cells are read based on a preset hard decision voltage level to obtain hard bit information and perform a hard decoding operation on the hard bit information. In step S1302, it is determined whether the hard decoding operation is successful (or failed). If the hard decoding operation is successful, in step S1303, the decoded codeword is output. If the hard decoding operation fails, in step S1304, the first memory cell is read based on the plurality of preset soft decision voltage levels to obtain soft bit information and perform soft decoding operation on the soft bit information. In step S1305, it is determined whether the soft decoding operation is successful (or failed). If the soft decoding operation is successful, in step S1303, the decoded codeword is output. If the soft decoding operation fails, it is determined in step S1306 whether there is an unchecked offset value. If there is still an unchecked offset value, in step S1307, the first memory cell is read based on a plurality of test voltage levels to obtain soft bit information. For example, such test voltage levels are corresponding to an offset value selected to be checked.

In step S1308, an evaluation parameter is obtained based on the soft bit information obtained in step S1307. In step S1309, it is determined whether the evaluation parameter obtained in step S1308 is better than a predetermined evaluation parameter. For example, if the value of the evaluation parameter is positively correlated with the total number of memory cells whose threshold voltage belongs to a transition region, and the obtained evaluation parameter is smaller than the preset evaluation parameter, step S1309 may determine YES and proceed to step S1310 to obtain the obtained The evaluation parameters are set to preset evaluation parameters. On the other hand, if the value of the evaluation parameter is positively correlated with the total number of memory cells whose threshold voltage belongs to the transition region, and the obtained evaluation parameter is greater than the preset evaluation parameter, step S1309 may determine NO and return to step S1306. Returning to step S1306, the next offset value can be checked (eg, a plurality of test voltage levels are determined based on the next offset value). It is worth mentioning that if the step S1307 is the first execution (that is, the preset evaluation parameters have not been set), the evaluation parameters obtained in step S1308 are directly set as the preset evaluation parameters in step S1310.

In step S1311, the preset hard decision voltage level is updated according to the preset evaluation parameter. For example, the preset hard decision voltage level is set to the optimal read voltage level according to the offset value corresponding to the preset evaluation parameter. Then, step S1301 and the like are repeatedly executed, and will not be described here. In addition, after checking for more offset values, if the process proceeds to step S1306 again, all the offset values have been checked (ie, the evaluation parameters corresponding to each of the available offset values have been obtained). In step S1306, it is determined that the decoding has failed. For example, if the error checking and correction circuit 508 determines that the decoding has failed, the memory management circuit 502 sends a read error message to the host system 11.

FIG. 14 is a flowchart of a decoding method according to another exemplary embodiment of the present invention.

Referring to FIG. 14, in step S1401, a plurality of first memory cells are read based on a preset hard decision voltage level to obtain hard bit information and a hard decoding operation is performed on the hard bit information. In step S1402, it is determined whether the hard decoding operation is successful (or failed). If the hard decoding operation is successful, in step S1403, the decoded codeword is output. If the hard decoding operation fails, in step S1404, the first memory cell is read based on the plurality of preset soft decision voltage levels to obtain soft bit information and perform soft decoding operation on the soft bit information. In step S1405, it is determined whether the soft decoding operation is successful (or failed). If the soft decoding operation is successful, in step S1403, the decoded codeword is output. If the soft decoding operation fails, it is determined in step S1406 whether the optimum read voltage level has been found. If not, in step S1407, it is determined whether or not there is an unchecked offset value.

If there is still an unchecked offset value, in step S1408, the first memory cell is read based on the plurality of test voltage levels to obtain soft bit information. For example, such test voltage levels are corresponding to an offset value selected to be checked. In step S1409, an evaluation parameter is obtained based on the soft bit information obtained in step S1408 and returns to step S1407 to check again whether there is an unchecked offset value. If so, steps S1408 and S1409 are repeatedly executed. If it is determined in step S1407 that all the offset values have been checked (ie, the evaluation parameters corresponding to each of the available offset values have been obtained), in step S1410, the updated plurality of evaluation parameters are updated. Preset hard decision voltage levels. For example, an offset value can be selected based on the numerical relationship between the evaluation parameters, and an optimal read voltage level can be set according to the offset value. The operation of selecting the offset value and setting the optimum read voltage level based on the numerical relationship between the plurality of evaluation parameters has been described in detail above, and will not be described herein. After step S1410, step S1401 and the like are repeatedly executed. Further, if it is executed again to step S1406, since the optimum read voltage level has been used in step S1401 of repeated execution, step S1411 is executed to determine that the decoding has failed.

However, the steps in FIGS. 12 to 14 have been described in detail above, and will not be described again herein. It should be noted that the steps in FIG. 12 to FIG. 14 can be implemented as a plurality of codes or circuits, and the present invention is not limited thereto. In addition, the methods of FIG. 12 to FIG. 14 may be used in combination with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, after the soft decoding process fails, at least two sets of test voltage levels are used to read the same memory cell. A corresponding plurality of evaluation parameters are then obtained, wherein each of the evaluation parameters corresponds to the total number of memory cells in the memory cell that meet certain state conditions. Based on these evaluation parameters, the preset hard decision voltage level can be updated. Thereby, the efficiency of finding the optimal read voltage level in the decoding operation can be improved, thereby improving the decoding efficiency.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ Memory storage device 11‧‧‧ Host system 110‧‧‧System bus 111‧‧‧Processor 112‧‧‧ Random access memory 113‧‧‧Reading memory 114‧‧‧ Data transmission Interface 12‧‧‧ Input/Output (I/O) device 20‧‧‧ Motherboard 201‧‧‧Visconet 202‧‧ Memory Card 203‧‧‧Solid Hard Disk 204‧‧‧Wireless Memory Storage Device 205‧ ‧‧Global Positioning System Module 206‧‧‧Network Interface Card 207‧‧‧Wireless Transmission 208‧‧‧Keyboard 209‧‧‧Screen 210‧‧‧ Speaker 32‧‧‧SD Card 33‧‧‧CF Card 34 ‧‧‧Embedded storage device 341‧‧‧Embedded multimedia card 342‧‧ Embedded multi-chip package storage device 402‧‧‧Connecting interface unit 404‧‧‧Memory control circuit unit 406‧‧‧Rewritable Volatile memory module 502‧‧‧ memory management circuit 504‧‧‧ host interface 506‧‧‧ memory interface 508‧‧‧ error checking and correction circuit 510‧‧‧ buffer memory 512‧‧‧ power management circuit 601‧‧‧Storage Area 602‧‧‧Replacement Area 610(0)~610(B) ‧‧‧Solid units 612(0)~612(C)‧‧‧Logical units 710, 711, 720, 721, 1101~1108‧‧‧Distribution 801~806, R _T1 , R _S1 , R _{T1 '} , R _{S1 '} , R _T2 , R _S2 , R _T3 , R _S3 , R _T11 , R _S11 , R _T12 , R _S12 , R _T13 , R _S13 , R _T14 , R _S14 , R _T15 , R _S15 , R _T16 , R _S16 , R _T17 , R _S17 ‧‧‧Area 831, 832, 931, 932, 941, 942, 951, 952‧‧‧soft bit information R _T1 , R _S1 , R _{T1 '} , R _{S1 '} , R _T2 , R _S2 , R _T3 , R _S3 ‧ ‧ ‧ 1110 ‧ ‧ Entity stylized unit 1120 ‧ ‧ entity stylized unit 1130 ‧ ‧ additional entity stylized unit S1201 ‧ ‧ steps (based on a preset hard decision voltage The bit reads a plurality of first memory cells to obtain hard bit information and performs a hard decoding operation on the hard bit information.) S1202‧‧‧Step (whether the hard decoding operation is successful) S1203‧‧‧Steps (output decoding successful codewords) S1204‧‧‧ steps (reading the first memory cell based on multiple preset soft decision voltage levels to obtain soft bit information and performing soft decoding operation on the soft bit information) S1205‧‧ steps (soft Whether the code operation is successful) S1206‧‧‧ steps (reading the first memory cell based on the plurality of first test voltage levels to obtain the first soft bit information and reading the first memory cell based on the plurality of second test voltage levels Obtaining the second soft bit information) S1207‧‧ steps (calculating the first evaluation parameter according to the first soft bit information and calculating the second evaluation parameter according to the second soft bit information) S1208‧‧‧ steps (according to the first The evaluation parameter and the second evaluation parameter update the preset hard decision voltage level. S1301‧‧‧ steps (reading a plurality of first memory cells based on a preset hard decision voltage level to obtain hard bit information and hard bits Information execution hard decoding operation) S1302‧‧‧Step (whether the hard decoding operation is successful) S1303‧‧‧Step (output decoded successful codeword) S1304‧‧‧Steps (based on multiple preset soft decision voltage levels read A memory cell obtains soft bit information and performs soft decoding operations on soft bit information.) S1305‧‧‧Step (whether the soft decoding operation is successful) S1306‧‧‧Steps (whether there are unchecked offset values) S1307‧ ‧ ‧ steps (based on multiple tests Pressing the first memory cell to obtain soft bit information) S1308‧‧‧Steps (calculating an evaluation parameter based on the obtained soft bit information) S1309‧‧‧Steps (determining whether the calculated evaluation parameters are better than one Set the evaluation parameters) S1310‧‧‧ steps (set the calculated evaluation parameters as preset evaluation parameters) S1311‧‧‧ steps (update the preset hard decision voltage level according to the preset evaluation parameters) S1312‧‧ steps (based on A preset hard decision voltage level reads a plurality of first memory cells to obtain hard bit information and performs a hard decoding operation on the hard bit information.) S1401‧‧‧Step (Decision decoding failure) S1402‧‧ steps (hard S1403‧‧‧Step (output decoded successful codeword) S1404‧‧‧Steps (Reading the first memory cell based on multiple preset soft decision voltage levels to obtain soft bit information and soft bits Meta-information performs soft decoding operation) S1405‧‧‧Step (whether the soft decoding operation is successful) S1406‧‧‧Step (whether the best read voltage level has been found) S1407‧‧‧Steps (Is there still an unchecked offset? Value) S1408‧‧ steps (Reading the first memory cell based on multiple test voltage levels to obtain soft bit information) S1409‧‧‧Steps (calculate an evaluation parameter based on the obtained soft bit information) S1410‧‧‧ steps (according to the calculated Evaluation parameters to update the preset hard decision voltage level) S1411‧‧‧ steps (decision decoding failure)

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention. FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention. FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the invention. FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the invention. FIG. 7 is a schematic diagram of reading hard bit information according to an exemplary embodiment of the invention. FIG. 8 is a schematic diagram of reading soft bit information according to an exemplary embodiment of the invention. 9A-9C are schematic diagrams of tracking an optimal read voltage level, according to an exemplary embodiment of the invention. FIG. 10A is a schematic diagram showing the correspondence between the number of memory cells and an offset value according to an exemplary embodiment of the invention. FIG. 10B is a schematic diagram showing the correspondence between the number of memory cells and an offset value according to another exemplary embodiment of the present invention. FIG. 11 is a schematic diagram of a transition region and a steady state region according to an exemplary embodiment of the invention. FIG. 12 is a flowchart of a decoding method according to an exemplary embodiment of the present invention. FIG. 13 is a flowchart of a decoding method according to another exemplary embodiment of the present invention. FIG. 14 is a flowchart of a decoding method according to another exemplary embodiment of the present invention.

S1201‧‧‧ steps (reading a plurality of first memory cells based on a preset hard decision voltage level to obtain hard bit information and performing hard decoding operations on hard bit information)

S1202‧‧‧Steps (whether the hard decoding operation is successful)

S1203‧‧‧Steps (outputting decoded codewords successfully)

S1204‧‧‧ steps (reading the first memory cell based on a plurality of preset soft decision voltage levels to obtain soft bit information and performing soft decoding operation on the soft bit information)

S1205‧‧‧Step (whether the soft decoding operation is successful)

S1206‧ ‧ steps (reading the first memory cell based on the plurality of first test voltage levels to obtain the first soft bit information and reading the first memory cell based on the plurality of second test voltage levels to obtain the second soft Bit information)

S1207‧‧‧ steps (acquiring the first evaluation parameter according to the first soft bit information and obtaining the second evaluation parameter according to the second soft bit information)

S1208‧‧‧ steps (update the preset hard decision voltage level according to the first evaluation parameter and the second evaluation parameter)

Claims (21)

A decoding method for a rewritable non-volatile memory module including a plurality of memory cells, the decoding method comprising: reading a plurality of first of the memory cells based on a predetermined hard decision voltage level The memory cell obtains a hard bit information; performs a hard decoding operation on the hard bit information; if the hard decoding operation fails, reads the first memory cells based on a plurality of preset soft decision voltage levels to obtain a Soft bit information; performing a soft decoding operation on the soft bit information; if the soft decoding operation fails, reading the first memory cells based on the plurality of first test voltage levels to obtain a first soft bit information And reading the first memory cells to obtain a second soft bit information based on the plurality of second test voltage levels; obtaining a first evaluation parameter according to the first soft bit information and according to the second soft bit Obtaining a second evaluation parameter, wherein the first evaluation parameter corresponds to a first total number of memory cells of the first memory cells that meet a first state condition, wherein the second evaluation parameter corresponds to the first Memory cell matches one A second two-state conditions the total number of memory cells; and updating based on the first evaluation parameter and the evaluation parameter of the second predetermined voltage level hard decision. The decoding method of claim 1, wherein the obtaining the first evaluation parameter according to the first soft bit information and obtaining the second evaluation parameter according to the second soft bit information comprises: according to the first A soft bit information is used to count a total number of memory cells in the first memory cell that belong to a first transition region, wherein the first transition region includes any two of the first test voltage levels An area between the levels; and counting, according to the second soft bit information, a total number of memory cells in the first memory cell that belong to a second transition region, wherein the second transition region includes the The area between any two of the voltage levels in the second test voltage level. The decoding method of claim 2, wherein the first transition region is a voltage level at which the voltage of the first test voltage level is the highest and a voltage at which the voltage of the first test voltage level is the smallest. An area between the levels, wherein the second transition area is an area between a voltage level at a voltage of the second test voltage level and a voltage level at which the voltage of the second test voltage level is the smallest . The decoding method of claim 1, wherein the obtaining the first evaluation parameter according to the first soft bit information and obtaining the second evaluation parameter according to the second soft bit information comprises: according to the first A soft bit information is used to count a total number of memory cells in the first memory cell belonging to a first steady state region, wherein the first steady state region includes a voltage having a maximum voltage among the first test voltage levels An area outside the area between the level and the voltage level at which the voltage is the smallest; and a total number of memory cells in the first memory cell whose threshold voltage belongs to a second steady state area according to the second soft bit information The second steady-state region includes an area outside a region between a voltage level at which the voltage of the second test voltage level is the highest and a voltage level at which the voltage is the smallest. The decoding method of claim 4, wherein the first steady-state region is located outside a region between a voltage level at which the voltage of the first test voltage level is the highest and a voltage level at which the voltage is the smallest. The second steady-state region is located outside the region between the voltage level at which the voltage is the highest and the voltage level at which the voltage is the smallest among the second test voltage levels. The decoding method of claim 1, wherein the first test voltage levels correspond to a first offset value, wherein the second test voltage levels correspond to a second offset value, wherein The first offset value is different from the second offset value, wherein the step of updating the preset hard decision voltage level according to the first evaluation parameter and the second evaluation parameter comprises: according to the first total number and the second A predetermined value relationship between the totals is used to update the preset hard decision voltage level, wherein the updated preset hard decision voltage level corresponds to one of the first offset value and the second offset value. The decoding method of claim 6, further comprising: updating the preset soft decision voltage levels according to the numerical relationship between the first total number and the second total number, wherein the updated The preset soft decision voltage level corresponds to one of the first offset value and the second offset value. A memory storage device includes: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module including a plurality of memory cells; and a memory control circuit unit coupled The connection control unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to send a first read command sequence to indicate that the read is based on a predetermined hard decision voltage level And storing, by the memory control circuit unit, a hard decoding operation, where the hard decoding operation fails, the memory is The body control circuit unit is further configured to send a second read command sequence to instruct to read the first memory cells based on the plurality of preset soft decision voltage levels to obtain a soft bit information, wherein the memory control circuit unit Further performing a soft decoding operation on the soft bit information, wherein if the soft decoding operation fails, the memory control circuit unit is further configured to send a first test instruction sequence to Reading the first memory cells based on the plurality of first test voltage levels to obtain a first soft bit information and transmitting a second test instruction sequence to indicate that the plurality of second test voltage levels are read based on the plurality of second test voltage levels The first memory cell obtains a second soft bit information, wherein the memory control circuit unit is further configured to obtain a first evaluation parameter according to the first soft bit information and obtain a first information according to the second soft bit information a second evaluation parameter, wherein the first evaluation parameter corresponds to a first total number of memory cells in the first memory cells that meet a first state condition, wherein the second evaluation parameter corresponds to the first memory cells a second total number of memory cells of the second state condition, wherein the memory control circuit unit is further configured to update the preset hard decision voltage level according to the first evaluation parameter and the second evaluation parameter. The memory storage device of claim 8, wherein the memory control circuit unit obtains the first evaluation parameter according to the first soft bit information and obtains the second evaluation according to the second soft bit information. The operation of the parameter includes: counting, according to the first soft bit information, a total number of memory cells in the first memory cell that belong to a first transition region, wherein the first transition region includes the first test An area between any two voltage levels in the voltage level; and counting, according to the second soft bit information, a total number of memory cells in the first memory cell that belong to a second transition region, wherein the The second transition region includes an area between any two of the second test voltage levels. The memory storage device of claim 9, wherein the first transition region is a voltage level at a maximum voltage among the first test voltage levels and a minimum voltage among the first test voltage levels a region between the voltage levels, wherein the second transition region is between a voltage level at which the voltage of the second test voltage level is the highest and a voltage level at which the voltage of the second test voltage level is the smallest Area. The memory storage device of claim 8, wherein the memory control circuit unit obtains the first evaluation parameter according to the first soft bit information and obtains the second evaluation according to the second soft bit information. The operation of the parameter includes: counting, according to the first soft bit information, a total number of memory cells in the first memory cell that belong to a first steady state region, wherein the first steady state region includes the first test An area outside the region between the voltage level at which the voltage is the highest and the voltage level at which the voltage is the smallest; and the threshold voltage in the first memory cells according to the second soft bit information belongs to a second stable a total number of memory cells of the state region, wherein the second steady state region includes an area outside a region between a voltage level at which the voltage of the second test voltage level is the highest and a voltage level at which the voltage is the smallest. The memory storage device of claim 11, wherein the first steady-state region is located between a voltage level at which the voltage of the first test voltage level is the highest and a voltage level at which the voltage is the smallest. In addition, the second steady-state region is located outside the region between the voltage level at which the voltage is the largest and the voltage level at which the voltage is the smallest among the second test voltage levels. The memory storage device of claim 8, wherein the first test voltage levels correspond to a first offset value, wherein the second test voltage levels correspond to a second offset value The first offset value is different from the second offset value, wherein the operation of the memory control circuit unit to update the preset hard decision voltage level according to the first evaluation parameter and the second evaluation parameter includes: Updating the preset hard decision voltage level by a numerical relationship between the first total number and the second total number, wherein the updated preset hard decision voltage level corresponds to the first offset value and the second One of the offset values. The memory storage device of claim 13, wherein the memory control circuit unit is further configured to update the preset soft decision voltages according to the numerical relationship between the first total number and the second total number. a level, wherein the updated preset soft decision voltage levels correspond to one of the first offset value and the second offset value. A memory control circuit unit for controlling a rewritable non-volatile memory module including a plurality of memory cells, wherein the memory control circuit unit comprises: a host interface for coupling to a host system; a memory interface for coupling to the rewritable non-volatile memory module; an error checking and correcting circuit; and a memory management circuit coupled to the host interface, the memory interface, and the error a check and correction circuit, wherein the memory management circuit is configured to send a first read command sequence to instruct to read a plurality of first memory cells in the memory cells to obtain a hard based on a predetermined hard decision voltage level Bit information, wherein the error checking and correcting circuit is configured to perform a hard decoding operation on the hard bit information, wherein if the hard decoding operation fails, the memory management circuit is further configured to send a second read command sequence to Instructing to read the first memory cells based on the plurality of preset soft decision voltage levels to obtain a soft bit information, wherein the error checking and correction circuit is further used to the soft bit Executing a soft decoding operation, wherein if the soft decoding operation fails, the memory management circuit is further configured to send a first test instruction sequence to indicate that the first memory cells are read based on the plurality of first test voltage levels Obtaining a first soft bit information and sending a second test instruction sequence to indicate that the first memory cells are read based on the plurality of second soft decision voltage levels to obtain a second soft bit information, wherein the memory The management circuit is further configured to obtain a first evaluation parameter according to the first soft bit information and obtain a second evaluation parameter according to the second soft bit information, wherein the first evaluation parameter corresponds to the first memory cells a first total number of memory cells that meet a first state condition, wherein the second evaluation parameter corresponds to a second total of the first memory cells that meet a second state condition, wherein the memory management The circuit is further configured to update the preset hard decision voltage level according to the first evaluation parameter and the second evaluation parameter. The memory control circuit unit of claim 15, wherein the memory management circuit obtains the first evaluation parameter according to the first soft bit information and obtains the second evaluation according to the second soft bit information. The operation of the parameter includes: counting, according to the first soft bit information, a total number of memory cells in the first memory cell that belong to a first transition region, wherein the first transition region includes the first test An area between any two voltage levels in the voltage level; and counting, according to the second soft bit information, a total number of memory cells in the first memory cell that belong to a second transition region, wherein the The second transition region includes an area between any two of the second test voltage levels. The memory control circuit unit of claim 16, wherein the first transition region is a voltage level at a voltage of the first test voltage level and a voltage in the first test voltage levels. An area between the minimum voltage levels, wherein the second transition region is a voltage level at which the voltage of the second test voltage level is the highest and a voltage level at which the voltage of the second test voltage level is the smallest. The area between. The memory control circuit unit of claim 15, wherein the memory management circuit obtains the first evaluation parameter according to the first soft bit information and obtains the second evaluation according to the second soft bit information. The operation of the parameter includes: counting, according to the first soft bit information, a total number of memory cells in the first memory cell that belong to a first steady state region, wherein the first steady state region includes the first test An area outside the region between the voltage level at which the voltage is the highest and the voltage level at which the voltage is the smallest; and the threshold voltage in the first memory cells according to the second soft bit information belongs to a second stable a total number of memory cells of the state region, wherein the second steady state region includes an area outside a region between a voltage level at which the voltage of the second test voltage level is the highest and a voltage level at which the voltage is the smallest. The memory control circuit unit of claim 18, wherein the first steady-state region is located between the voltage level at which the voltage of the first test voltage level is the highest and the voltage level at which the voltage is the smallest. In addition, the second steady-state region is located outside the region between the voltage level at which the voltage is the largest and the voltage level at which the voltage is the smallest among the second test voltage levels. The memory control circuit unit of claim 15, wherein the first test voltage levels correspond to a first offset value, wherein the second test voltage levels correspond to a second offset a value, wherein the first offset value is different from the second offset value, wherein the operation of the memory management circuit to update the preset hard decision voltage level according to the first evaluation parameter and the second evaluation parameter comprises: Updating the preset hard decision voltage level by a numerical relationship between the first total number and the second total number, wherein the updated preset hard decision voltage level corresponds to the first offset value and the second One of the offset values. The memory control circuit unit of claim 20, wherein the memory management circuit is further configured to update the preset soft decision voltages according to the numerical relationship between the first total number and the second total number. a level, wherein the updated preset soft decision voltage levels correspond to one of the first offset value and the second offset value.