WO2016155368A1

WO2016155368A1 - Rram-based nonvolatile sram memory cell

Info

Publication number: WO2016155368A1
Application number: PCT/CN2015/098219
Authority: WO
Inventors: 韩小炜
Original assignee: 山东华芯半导体有限公司
Priority date: 2015-03-30
Filing date: 2015-12-22
Publication date: 2016-10-06
Also published as: CN104715791A

Abstract

An RRAM cell-based nonvolatile SRAM memory cell comprises a conventional six-transistor SRAM cell (6T-SRAM) and two 1T1R RRAM cells. The 6T-SRAM comprises: two N-type transistors (NAL, NAR), respectively connected to a data line (Q, QB) and a bit line (BL, BLB) on a same side. Four transistors (PL, NL, PR, NR) form two cross-coupled inverters, and outputs of the inverters are a first data line (Q) and a second data line (QB). Each of the two RRAM cells comprises a resistance-variable resistor (RL, RR) and a transistor (RNSL, RNSR). A cathode of the resistance-variable resistor (RL, RR) is connected to a corresponding data line (Q, QB) on a same side, an anode of the resistance-variable resistor (RL, RR) is connected to a source of the corresponding transistor (RNSL, RNSR), a drain of the transistor (RNSL, RNSR) is connected to a bit line (BLB, BL) on an opposite side, and a gate of the transistor (RNSL, RNSR) is connected to a resistance word line (RWL). The storage cell can maintain the advantages of data storage, low power consumption of a standby mode of a memory and simple operations even in a case in which automatic data recovery and power-off are implemented.

Description

A non-volatile SRAM memory cell based on RRAM

Technical field

The present invention relates to the field of memory design. In particular, the present invention relates to a non-volatile SRAM (nvSRAM) unit based on an RRAM cell.

Background technique

With the continuous advancement of process technology, the static power consumption caused by leakage accounts for a larger proportion of the memory power of System-On-Chip (SOC), which is especially important for mobile chips that value power consumption. It is a problem. In addition, code storage and low-capacity data storage chips for many commercial and industrial applications require faster non-volatile storage technologies than FLASH and EEPROM.

Currently used battery backup SRAM (BBSRAM, Battery Backup SRAM) cannot be applied in mobile SOC and batteryless solutions because it requires a board-level battery or a battery and SRAM package.

In addition, there are solutions for SRAM combined with embedded FLASH. However, due to the limitation of FLASH programming and reading mode, it takes a long time to read and write data in FLASH into SRAM and FLASH itself, so it is not suitable for applications with high speed requirements.

In academia, there is a technology that combines non-volatile memory technology with traditional SRAM technology, such as integrating FLASH or some emerging technologies such as MRAM, PCRAM, RRAM, etc. in SRAM to form a non-SRAM+NVM Volatile SRAM unit. The "SRAM+NVM" non-volatile SRAM unit stores the data in the SRAM unit in the non-volatile unit at the same time, so the information is not lost after power-off, and the data is automatically restored to the SRAM unit after power-on. in. This greatly reduces the standby mode power consumption of the mobile SOC memory, and can also meet high-speed non-volatile storage applications.

However, the various bonding techniques in the prior art have complicated steps and long operation time. Therefore, there is a need for a memory unit that can solve the above technical problems.

Summary of the invention

In view of the problems in the prior art, the present invention provides a new RRAM cell based non-volatile SRAM memory cell. The RRAM cell-based nonvolatile SRAM memory cell according to the present invention is capable of It realizes the advantages of automatic data recovery, storage data retention under power-off, low power consumption in memory standby mode, and convenient operation.

The present invention is achieved by the following aspects:

According to a first aspect of the present invention, there is provided a RRAM-based nonvolatile SRAM memory cell comprising a six transistor SRAM cell 6T-SRAM and two RRAM cells;

Wherein, the six-transistor SRAM cell 6T-SRAM comprises:

The two N-type transistors are a first N-type transistor and a second N-type transistor, wherein the first N-type transistor is connected to the first data line and the first bit line, and the second N-type transistor is connected to the second data line and the Two bit line;

Four transistors, the four transistors forming two cross-coupled inverters, the outputs of the two cross-coupled inverters being a first data line and a second data line, respectively;

Wherein the two RRAM units comprise:

a first RRAM cell comprising a first resistive resistor and a first transistor, wherein a cathode of the first resistive resistor is coupled to the first data line, and an anode of the first resistive resistor is coupled to a source of the first transistor a drain of the first transistor is coupled to a second bit line, a gate of the first transistor being coupled to a resistive word line;

a second RRAM cell comprising a second resistive resistor and a second transistor, wherein a cathode of the second resistive resistor is coupled to the second data line, and an anode of the second resistive resistor is coupled to a source of the second transistor The drain of the second transistor is connected to the first bit line, and the gate of the first transistor is connected to the resistance word line.

According to a preferred embodiment of the RRAM-based nonvolatile SRAM memory cell of the present invention, the first resistive resistor has a high resistance state and a low resistance state, and the second resistive resistor also has a high resistance state and a low Resistance state.

A preferred embodiment of a RRAM-based non-volatile SRAM memory cell in accordance with the present invention,

When the first resistive resistor is in a low resistance state and the second resistive resistor is in a high impedance state, when re-powering, the first data line Q recovers data “0”, and the second data line QB recovers data “1”; as well as

When the first resistive resistor is in a high impedance state and the second resistive resistor is in a low resistance state, the first data line Q recovers data "1" and the second data line QB recovers data "0" upon power-on.

A preferred embodiment of the RRAM-based non-volatile SRAM memory cell in accordance with the present invention, The two cross-coupled inverters are cross-coupled first inverters and second inverters, wherein the input of the first inverter is a second data line, and the output of the first inverter is a first data line The input of the second inverter is the first data line, and the output of the second inverter is the second data line.

According to a second aspect of the present invention, there is provided a RRAM-based nonvolatile SRAM memory cell comprising a six transistor SRAM cell 6T-SRAM and two 1T1R RRAM cells;

The six-transistor SRAM cell 6T-SRAM includes two N-type access transistors and four logic transistors in two cross-coupled inverters; the two ends of the N-type access transistor are respectively connected to the data lines and bits on the same side. line;

The RRAM cells respectively comprise a resistive resistor R and a select transistor T; the anode of the resistive resistor R is connected to the source terminal of the select transistor T, and the resistive resistor R has two states of a high resistance state and a low resistance state; RRAM The drain end of the unit is connected to the bit line on the opposite side, the cathode is connected to the data line on the same side, and the gate end is connected to the resistance word line.

Preferably, the two N-type access transistors are respectively a first N-type access transistor NAL connecting the first bit line BL and the first data line Q, and connecting the second bit line BLB and the second data line QB. The second N-type access transistor NAR.

Further, the four logic transistors are respectively a first logic transistor PL and a second logic transistor NL that are connected to the first data line Q, and a third logic transistor PR and a fourth logic transistor that are connected to the second data line QB. NR.

Further, the two RRAM cells are respectively a first RRAM cell (1T1R1) and a second RRAM cell (1T1Rr); the first resistive resistor RL and the second resistive resistor RR in the first and second RRAM cells are respectively connected The first data line Q and the second data line QB on the same side.

Further, when the first resistive resistor RL is in a high impedance state and the second resistive resistor RR is in a low resistance state, the first data line Q recovers data “1” when the power is turned back on, and the second data line QB recovers data “ 0"; conversely, the first data line Q recovers data "0" and the second data line QB recovers data "1".

Compared with the prior art, the RRAM-based non-volatile SRAM memory unit of the present invention has the following beneficial technical effects:

The invention adds two 1T1R RRAM cells in a conventional 6T-SRAM memory cell, and simultaneously stores data in the SRAM cell in two 1T1R RRAM cells. The state of the resistive resistors in the two 1T1R RRAM cells is reversed by the cross-connection of the drains of the two transistors in the two 1T1R RRAM cells. That is, regardless of whether the stored data is "0" or "1", one of the two 1T1R RRAM cells is in a high impedance state and one is in a low resistance state. Thus, at power-on, the magnitude of the ground resistance of the data lines on both sides is different. The charging and discharging speed is different, so the original data will be automatically restored to the SRAM unit.

In addition, the read and write operations of the RRAM-based nonvolatile SRAM memory cell of the present invention, like the conventional 6T-SRAM memory cell, retain the high speed read and write characteristics of the 6T-SRAM memory cell. Moreover, during the storage operation, the information in the 6T-SRAM memory cell is simultaneously backed up and stored in the resistance resistors of the two 1T1R RRAM cells. In this way, the information is not lost after power-off, and the automatic recovery after power-on is realized, and the emerging non-volatile memory technology RRAM is integrated in the traditional SRAM.

In addition, in applications where speed is not critical, the memory operation can be implemented in one step after the end of the SRAM cell write operation, so there is no need to charge and discharge the first bit line and the second bit line. This saves power consumption and reduces storage operation time.

DRAWINGS

The RRAM-based non-volatile SRAM memory cell of the present invention will be further described below with reference to the accompanying drawings, in which:

1 is a block diagram showing the structure of a nonvolatile SRAM memory cell in accordance with a preferred embodiment of the present invention.

2 is a timing diagram of read and write operations of a nonvolatile SRAM memory cell in accordance with a preferred embodiment of the present invention.

3 is a timing diagram of a storage and recovery operation of a non-high speed application of a nonvolatile SRAM memory cell in accordance with a preferred embodiment of the present invention.

4 is a timing diagram of a storage and recovery operation of a high speed application of a nonvolatile SRAM memory cell in accordance with a preferred embodiment of the present invention.

detailed description

The present invention will be further described in detail below in conjunction with specific embodiments. Those of ordinary skill in the art will understand that the following description is illustrative and not limiting.

The present invention provides a RRAM-based nonvolatile SRAM memory cell nvSRAM. As shown in FIG. 1, a nonvolatile SRAM memory cell nvSRAM of a preferred embodiment of the present invention includes a conventional 6-transistor SRAM cell 6T-SRAM and two 1T1R RRAM cells (1T1R1 and 1T1Rr).

As can be seen from Figure 1, a typical conventional 6-transistor SRAM cell includes two N-type transistors (hereinafter referred to as "N-type access transistors") (NAL, NAR) and four of the two cross-coupled inverters. (hereinafter referred to as "logic transistor") (PL, NL, PR, NR). As can be seen from Figure 1, the N-type access transistor NAL is connected to the a data line Q and a first bit line BL, the N-type access transistor NAR is connected to the second data line QB and the second bit line BLB; and the logic transistors PL, NL, PR, NR form two cross-coupling inversions The inputs of the two cross-coupled inverters are a second data line QB and a first data line Q, respectively, and the outputs are a first data line Q and a second data line QB, respectively.

In addition, as can also be seen from FIG. 1, the two 1T1R RRAM cells each include a resistive resistor R and a transistor (hereinafter referred to as "select transistor") T, wherein the anode of the resistive resistor R is connected to the source of the select transistor T. pole. Thus, the 1T1R RRAM cell has three ports: the cathode of the resistive resistor R, the gate of the select transistor T, and the drain of the select transistor T. The three ports are respectively connected to the data line on the corresponding side, the resistance word line, and the bit line on the opposite side. That is, the three ports of the 1T1R1 unit, that is, the cathode of the resistive resistor RL, the gate of the selection transistor RNSL, and the drain of the selection transistor RNSL are connected to the first data line Q, the resistance word line RWL, and the second bit line BLB, respectively. And, the three ports of the 1T1Rr unit, that is, the cathode of the resistance variable resistor RR, the gate of the selection transistor RNSR, and the drain of the selection transistor RNSR are connected to the second data line QB, the resistance word line RWL, and the first bit line BL, respectively.

The resistive resistors RL and RR have high resistance and low resistance, respectively. In addition, as is well known to those skilled in the art, when the voltage V _R <=-V _RESET across the resistive resistor R, the resistive resistor R is RESET to a high impedance state, at which time the resistive resistor memorizes "1". When the resistive voltage V _R across the resistor R> = V _SET, SET resistive resistor R is low resistance state, then the resistive resistive memory "0."

In the nonvolatile SRAM of the preferred embodiment of the present invention shown in FIG. 1, when the resistive resistor RL is in a high resistance state and the resistive resistor RR is in a low resistance state, if the power is turned back on, the first data line Q restores the data "1", and the second data line QB restores the data "0". On the other hand, when the resistive resistor RL is in the low resistance state and the resistive resistor RR is in the high impedance state, if the power is turned back on, the first data line Q recovers the data “0”, and the second data line QB recovers the data “1”.

The nonvolatile SRAM memory cell nvSRAM of the preferred embodiment of the present invention includes four modes of operation: a write operation, a read operation, a store operation, and a restore operation.

The read and write operations are the same as the traditional 6T-SRAM memory cells, thus preserving the high-speed read and write characteristics of the SRAM memory cells.

The storage operation stores the information in the 6T-SRAM memory cell at the same time in the resistive resistor RL of the 1T1R1 RRAM and the resistive resistor RR of the 1T1Rr RRAM, so as to ensure that the information is not lost after power-off. For high speed applications, the data can be backed up using the idle time of the memory. For applications that are not particularly demanding in speed, they can be used in every Back up data after a write operation. Thus, not only the number of times of charging of the first bit line BL and the second bit line BLB is reduced, power consumption is reduced, and the storage operation can be completed in one step to increase the storage speed.

The recovery operation automatically restores the information in the resistive resistors RL and RR to the 6T-SRAM memory cell when power is restored.

The mode of operation of the non-volatile SRAM memory cell nvSRAM of the preferred embodiment of the present invention will now be further illustrated in conjunction with FIGS. 2 through 4.

2 illustrates a timing chart of write operations and read operations of a nonvolatile SRAM memory cell nvSRAM of a preferred embodiment of the present invention. As an example, a timing diagram for reading "1" and writing "1" operations is shown in FIG.

When the write "1" operation is performed, the first bit line BL and the second bit line BLB are first precharged to VDDQ, respectively. Then, data "1" and data "0" are written to the first bit line BL and the second bit line BLB, respectively. Next, the word line WL is turned on, and data "1" and data "0" are written to the first data line Q and the second data line QB, respectively.

When the read "1" operation is performed, the first bit line BL and the second bit line BLB are first precharged to VDDQ, respectively. Then, open WL. Using the principle of charge sharing, the charge on the second bit line BLB flows to the second data line QB, resulting in more power on the first bit line BL than the second bit line BLB, and the voltage difference between the two is ΔV (as shown in FIG. 2). The sense amplifier shown is fed into the periphery of the SRAM array to read the data "1".

3 illustrates a timing chart of a memory operation and a recovery operation of a non-high speed application of a nonvolatile SRAM memory cell nvSRAM of a preferred embodiment of the present invention. As an example, a storage operation and a recovery operation timing chart after writing "1" are illustrated in FIG.

Storage operation

After writing "1", the first bit line BL and the second bit line BLB continue to hold the voltages VDDQ and GND. The resistance word line RWL is charged to the voltage V _RWL .

At this time, the voltages of the three bit lines BLB, the first data line Q, and the resistance word line RWL of the three ports of the 1T1R1 cell are GND, VDDQ, and V _RWL , respectively. Thus, the voltage across the resistive resistor RL satisfies V _RL <=-V _RESET , and the resistive resistor RL is asserted to a high impedance state.

The voltages of the first bit line BL, the second data line QB, and the resistance word line RWL of the three ports of the 1T1Rr unit are VDDQ, GND, and V _RWL , respectively. Thus, the voltage across the resistive resistor RR satisfies V _RR >=V _SET , and the resistive resistor RR is set to a low-resistance state by SET.

After the RESET and SET operations are completed, the 6T-SRAM cell storage data is backed up and stored in the nonvolatile cell resistance resistors RL and RR.

Recovery operation

After power-off, the voltages of the first bit line Q and the second bit line QB both become GND. Before re-powering up, the resistance word line RWL is first turned on, then VDDQ begins to climb, and the first bit line Q and the second bit line QB are charged. Since the ground resistance of the first bit line Q is greater than the second bit line QB, the first bit line Q is charged faster than the second bit line QB. The cross-coupled inverter in the SRAM cell amplifies V _Q-QB , recovering data "1" and "0" to the first data line Q and the second data line QB, respectively, to complete the recovery operation.

4 illustrates a timing chart of a memory operation and a recovery operation of a nonvolatile SRAM memory cell nvSRAM high speed application of a preferred embodiment of the present invention. As an example, a storage operation and a recovery operation timing chart after writing "1" are illustrated in FIG.

Storage operation

When the memory is in an idle state, the storage operation is completed in two steps.

Step 1: Charge both the first bit line BL and the second bit line BLB to VDDQ. Then, the resistance word line RWL is charged to V _RWL . After writing "1", the voltages of the first data line Q and the second data line QB are VDDQ and GND, respectively. At this time, the voltages of the three terminals of the 1T1R1 unit, that is, the second bit line BLB, the first data line Q, and the resistance word line RWL are VDDQ, VDDQ, and V _RWL , respectively. Thus, the voltage across the resistive resistor RL does not satisfy V _RL <=-V _RESET , and the resistive resistor RL maintains the original resistive state. The voltages of the first bit line BL, the second data line QB, and the resistance word line RWL of the three ports of the 1T1Rr unit are VDDQ, GND, and V _RWL , respectively. Thus, the voltage across the resistive resistor RR satisfies V _RR >=V _SET , and the resistive resistor RR is set to a low resistance state by SET.

The second step: discharging the first bit line BL and the second bit line BLB to GND. Then, the resistance word line RWL is charged to V _RWL . At this time, the voltages of the three terminals of the 1T1R1 unit, that is, the second bit line BLB, the first data line Q, and the resistance word line RWL are GND, VDDQ, and V _RWL , respectively. Thus, the voltage across the resistive resistor RL satisfies V _RL <=-V _RESET , and the resistive resistor RL is RESET to a high impedance state. The voltages at the three ends of the first bit line BL, the second data line QB, and the resistance word line RWL of the three ports of the 1T1Rr unit are GND, GND, and V _RWL , respectively. Thus, the voltage across the resistive resistor RR does not satisfy V _RR >= V _SET , and the resistive resistor RR maintains the original resistive state. After the SET and RESET operations are completed, the SRAM cell stores the data and is backed up to the nonvolatile cell resistance resistors RL and RR.

Recovery operation

The recovery operation of the power-down at the time of high-speed application is the same as the recovery operation of the power-down at the time of low-speed application, and can be understood by referring to the description of the recovery operation in FIG.

Some embodiments of the invention have been illustrated above, but it should be appreciated that embodiments of the invention are not limited thereto. Various modifications may be made to the invention without departing from the spirit and scope of the invention.

Claims

A non-volatile SRAM memory cell based on RRAM, comprising a six-transistor SRAM cell 6T-SRAM and two RRAM cells;

Wherein, the six-transistor SRAM cell 6T-SRAM comprises:

The two N-type transistors are a first N-type transistor and a second N-type transistor, wherein the first N-type transistor is connected to the first data line and the first bit line, and the second N-type transistor is connected to the second data line and the Two bit line;

Four transistors, the four transistors forming two cross-coupled inverters, the outputs of the two cross-coupled inverters being a first data line and a second data line, respectively;

Wherein the two RRAM units comprise:

a first RRAM cell comprising a first resistive resistor and a first transistor, wherein a cathode of the first resistive resistor is coupled to the first data line, and an anode of the first resistive resistor is coupled to a source of the first transistor a drain of the first transistor is coupled to a second bit line, a gate of the first transistor being coupled to a resistive word line;

a second RRAM cell comprising a second resistive resistor and a second transistor, wherein a cathode of the second resistive resistor is coupled to the second data line, and an anode of the second resistive resistor is coupled to a source of the second transistor The drain of the second transistor is connected to the first bit line, and the gate of the first transistor is connected to the resistance word line.
The RRAM-based nonvolatile SRAM memory cell of claim 1 , wherein the first resistive resistor has a high resistance state and a low resistance state, and the second resistive resistor also has a high resistance state. And low resistance.
The RRAM-based nonvolatile SRAM memory unit of claim 2, wherein

When the first resistive resistor is in a low resistance state and the second resistive resistor is in a high impedance state, when re-powering, the first data line Q recovers data “0”, and the second data line QB recovers data “1”; as well as

When the first resistive resistor is in a high impedance state and the second resistive resistor is in a low resistance state, the first data line Q recovers data "1" and the second data line QB recovers data "0" upon power-on.
The RRAM-based nonvolatile SRAM memory cell of claim 1 or 2, wherein the two cross-coupled inverters are cross-coupled first and second inverters, wherein The input of the first inverter is a second data line, the output of the first inverter is a first data line, the input of the second inverter is a first data line, and the output of the second inverter is a second data line.
A non-volatile SRAM memory cell based on RRAM, comprising a six-transistor SRAM cell 6T-SRAM and two RRAM cells;

The six-transistor SRAM cell 6T-SRAM includes two N-type access transistors and four logic transistors in two cross-coupled inverters; the two ends of the N-type access transistor are respectively connected to the data lines and bits on the same side. line;

The RRAM cells respectively comprise a resistive resistor R and a select transistor T; the anode of the resistive resistor R is connected to the source terminal of the select transistor T, and the resistive resistor R has two states of a high resistance state and a low resistance state; RRAM The drain end of the unit is connected to the bit line on the opposite side, the cathode is connected to the data line on the same side, and the gate end is connected to the resistance word line.
The RRAM-based nonvolatile SRAM memory cell of claim 5, wherein the two N-type access transistors are respectively connected to the first bit line BL and the first data line Q An N-type access transistor NAL, and a second N-type access transistor NAR connecting the second bit line BLB and the second data line QB.
A RRAM-based nonvolatile SRAM memory cell as claimed in claim 6, wherein said four logic transistors are respectively a first logic transistor PL and a common first data line Q The second logic transistor NL, and the third logic transistor PR and the fourth logic transistor NR that are connected to the second data line QB.
A RRAM-based nonvolatile SRAM memory cell as claimed in claim 6, wherein said two RRAM cells are a first RRAM cell (1T1R1) and a second RRAM cell (1T1Rr), respectively; The first resistive resistor RL and the second resistive resistor RR in the first and second RRAM cells are respectively connected to the first data line Q and the second data line QB on the same side.
A RRAM-based nonvolatile SRAM memory cell as claimed in claim 8, wherein when the first resistive resistor RL is in a high impedance state and the second resistive resistor RR is in a low resistance state, When the power is on, the first data line Q recovers the data "1", and the second data line QB recovers the data "0"; otherwise, the first data line Q recovers the data "0", and the second data line QB restores the data "1".