CN106448725A - Read/write splitting memory cell based on FinFET (fin field-effect transistor) devices - Google Patents
Read/write splitting memory cell based on FinFET (fin field-effect transistor) devices Download PDFInfo
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Abstract
本发明公开了一种基于FinFET器件的读写分离存储单元，其特征在于包括第一FinFET管、第二FinFET管、第三FinFET管、第四FinFET管、第五FinFET管、第六FinFET管和第七FinFET管，第一FinFET管和第二FinFET管均为P型FinFET管，第三FinFET管、第四FinFET管、第五FinFET管、第六FinFET管和第七FinFET管均为N型FinFET管，第一FinFET管和第二FinFET管的鳍的数量均为2，第三FinFET管、第四FinFET管、第五FinFET管、第六FinFET管和第七FinFET管的鳍的数量均为1；优点是电路结构简单，采用数量较少的晶体管来实现存储单元功能，读操作和写操作分开，读写互不干扰，延时、功耗和功耗延时积均较小。
The invention discloses a read-write separation storage unit based on a FinFET device, which is characterized in that it comprises a first FinFET tube, a second FinFET tube, a third FinFET tube, a fourth FinFET tube, a fifth FinFET tube, a sixth FinFET tube and The seventh FinFET tube, the first FinFET tube and the second FinFET tube are all P-type FinFET tubes, the third FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube are all N-type FinFET tubes The number of fins in the first FinFET tube and the second FinFET tube is 2, and the number of fins in the third FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube is 1 The advantage is that the circuit structure is simple, a small number of transistors are used to realize the function of the storage unit, the read operation and the write operation are separated, the read and write do not interfere with each other, and the delay, power consumption and power consumption delay product are all small.
Description
技术领域technical field
本发明涉及一种存储单元，尤其是涉及一种基于FinFET器件的读写分离存储单元。The invention relates to a storage unit, in particular to a read-write separation storage unit based on a FinFET device.
背景技术Background technique
随着工艺尺寸进入纳米级，功耗成为集成电路设计者不得不关注的问题。在大部分的数字系统中存储器的功耗占据总电路功耗的比例越来越大。静态随机存取存储器(SRAM，Static Random Access Memory)，在存储器中是一个重要的组成部分，因而设计低功耗SRAM具有重要的研究意义。静态随机存取存储器主要由存储阵列及其他外围电路构成，而存储阵列由存储单元构成，存储单元是静态随机存取存储器的核心，存储单元直接决定静态随机存取存储器的性能。As the process size enters the nanometer level, power consumption has become a problem that IC designers have to pay attention to. In most digital systems, memory power consumption accounts for an increasing proportion of total circuit power consumption. Static Random Access Memory (SRAM, Static Random Access Memory) is an important component in memory, so designing low-power SRAM has important research significance. The SRAM is mainly composed of a storage array and other peripheral circuits, and the storage array is composed of a storage unit, which is the core of the SRAM, and the storage unit directly determines the performance of the SRAM.
延时、功耗和功耗延时积是体现存储单元性能的主要三个因素，优化这三个因素可以优化存储单元的性能从而提高静态随机存取存储器整体系统的性能，其中，功耗延时积为功耗和延时的乘积，单位为焦耳，因此功耗延时积是能量的衡量，可以作为一个开关器件性能的度量。在功耗延时积基本不变的情况下，面积也是制约电路性能的一个重要因素。Delay, power consumption, and power consumption delay product are the three main factors that reflect the performance of the storage unit. Optimizing these three factors can optimize the performance of the storage unit and improve the performance of the overall SRAM system. Among them, the power consumption delay The time product is the product of power consumption and delay, and the unit is joules. Therefore, the power consumption delay product is a measure of energy and can be used as a measure of the performance of a switching device. Under the condition that the power consumption delay product is basically unchanged, the area is also an important factor restricting the circuit performance.
FinFET管(鳍式场效晶体管，Fin Field-Effect Transistor)是一种新的互补式金氧半导体(CMOS)晶体管，具有功耗低，面积小的优点。鉴此，设计一种在不影响电路性能的情况下，电路面积、延时、功耗和功耗延时积均较小的基于FinFET器件的读写分离存储单元具有重要意义。FinFET tube (Fin Field-Effect Transistor, Fin Field-Effect Transistor) is a new complementary metal oxide semiconductor (CMOS) transistor, which has the advantages of low power consumption and small area. In view of this, it is of great significance to design a read-write separation memory unit based on FinFET devices with small circuit area, delay, power consumption and power consumption delay product without affecting the circuit performance.
发明内容Contents of the invention
本发明所要解决的技术问题是提供一种在不影响电路性能的情况下，电路面积、延时、功耗和功耗延时积均较小的基于FinFET器件的读写分离存储单元。The technical problem to be solved by the present invention is to provide a read-write separation storage unit based on FinFET devices with small circuit area, delay, power consumption and power consumption delay product without affecting circuit performance.
本发明解决上述技术问题所采用的技术方案为：一种基于FinFET器件的读写分离存储单元，包括第一FinFET管、第二FinFET管、第三FinFET管、第四FinFET管、第五FinFET管、第六FinFET管和第七FinFET管，所述的第一FinFET管和所述的第二FinFET管均为P型FinFET管，所述的第三FinFET管、所述的第四FinFET管、所述的第五FinFET管、所述的第六FinFET管和所述的第七FinFET管均为N型FinFET管，所述的第一FinFET管和所述的第二FinFET管的鳍的数量均为2，所述的第三FinFET管、所述的第四FinFET管、所述的第五FinFET管、所述的第六FinFET管和所述的第七FinFET管的鳍的数量均为1；所述的第一FinFET管的源极和所述的第二FinFET管的源极均接入电源，所述的第一FinFET管的漏极、所述的第二FinFET管的前栅、所述的第二FinFET管的背栅、所述的第三FinFET管的漏极、所述的第四FinFET管的前栅和所述的第五FinFET管的漏极连接且其连接端为所述的读写分离存储单元的输出端，所述的第一FinFET管的前栅、所述的第一FinFET管的背栅、所述的第二FinFET管的漏极、所述的第三FinFET管的前栅、所述的第四FinFET管的漏极、所述的第六FinFET管的漏极和所述的第七FinFET管的前栅连接且其连接端为所述的读写分离存储单元的反相输出端；所述的第三FinFET管的源极、所述的第三FinFET管的背栅、所述的第四FinFET管的背栅、所述的第四FinFET管的源极和所述的第七FinFET管的源极均接地；所述的第五FinFET管的前栅、所述的第五FinFET管的背栅、所述的第六FinFET管的背栅和所述的第六FinFET管的前栅连接且其连接线为所述的读写分离存储单元的写字线；所述的第五FinFET管的源极为所述的读写分离存储单元的写位线；所述的第六FinFET管的源极为所述的读写分离存储单元的写位线反向控制端；所述的第七FinFET管的漏极为所述的读写分离存储单元的读位线；所述的第七FinFET管的背栅为所述的读写分离存储单元的读字线。The technical solution adopted by the present invention to solve the above technical problems is: a read-write separation storage unit based on FinFET devices, including a first FinFET tube, a second FinFET tube, a third FinFET tube, a fourth FinFET tube, and a fifth FinFET tube , the sixth FinFET tube and the seventh FinFET tube, the first FinFET tube and the second FinFET tube are P-type FinFET tubes, the third FinFET tube, the fourth FinFET tube, the The fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube are all N-type FinFET tubes, and the number of fins in the first FinFET tube and the second FinFET tube is 2. The number of fins in the third FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube is 1; The source of the first FinFET and the source of the second FinFET are connected to the power supply, the drain of the first FinFET, the front gate of the second FinFET, the The back gate of the second FinFET, the drain of the third FinFET, the front gate of the fourth FinFET, and the drain of the fifth FinFET are connected, and the connection terminal is the read Write the output terminal of the separated storage unit, the front gate of the first FinFET, the back gate of the first FinFET, the drain of the second FinFET, the front gate of the third FinFET The gate, the drain of the fourth FinFET, the drain of the sixth FinFET and the front gate of the seventh FinFET are connected, and the connection end is the reverse side of the read-write separation memory unit. phase output terminal; the source of the third FinFET, the back gate of the third FinFET, the back gate of the fourth FinFET, the source of the fourth FinFET and the The sources of the seventh FinFET tubes are grounded; the front gate of the fifth FinFET tube, the back gate of the fifth FinFET tube, the back gate of the sixth FinFET tube, and the sixth FinFET tube The front gate of the tube is connected and its connection line is the write word line of the read-write separation memory unit; the source of the fifth FinFET tube is the write bit line of the read-write separation memory unit; the sixth The source of the FinFET tube is the reverse control terminal of the write bit line of the read-write separation memory unit; the drain of the seventh FinFET tube is the read bit line of the read-write separation memory unit; the seventh The back gate of the FinFET tube is the read word line of the read-write separation memory unit.
所述的第一FinFET管、所述的第二FinFET管、所述的第三FinFET管、所述的第四FinFET管、所述的第五FinFET管和所述的第六FinFET管均为低阈值FinFET管，所述的第七FinFET管为高阈值FinFET管。The first FinFET tube, the second FinFET tube, the third FinFET tube, the fourth FinFET tube, the fifth FinFET tube and the sixth FinFET tube are all low The threshold FinFET tube, the seventh FinFET tube is a high threshold FinFET tube.
所述的第一FinFET管、所述的第二FinFET管、所述的第三FinFET管、所述的第四FinFET管、所述的第五FinFET管和所述的第六FinFET管均的阈值电压均为0.1v，所述的第七FinFET管的阈值电压为0.6v。Threshold values of the first FinFET, the second FinFET, the third FinFET, the fourth FinFET, the fifth FinFET, and the sixth FinFET The voltages are all 0.1v, and the threshold voltage of the seventh FinFET tube is 0.6v.
与现有技术相比，本发明的优点在于通过第一FinFET管、第二FinFET管、第三FinFET管、第四FinFET管、第五FinFET管、第六FinFET管和第七FinFET管这七个FinFET管构成基于FinFET器件的读写分离存储单元，第一FinFET管和第二FinFET管均为P型FinFET管，第三FinFET管、第四FinFET管、第五FinFET管、第六FinFET管和第七FinFET管均为N型FinFET管，第一FinFET管和第二FinFET管的鳍的数量均为2，第三FinFET管、第四FinFET管、第五FinFET管、第六FinFET管和第七FinFET管的鳍的数量均为1；第一FinFET管的源极和第二FinFET管的源极均接入电源，第一FinFET管的漏极、第二FinFET管的前栅、第二FinFET管的背栅、第三FinFET管的漏极、第四FinFET管的前栅和第五FinFET管的漏极连接且其连接端为读写分离存储单元的输出端，第一FinFET管的前栅、第一FinFET管的背栅、第二FinFET管的漏极、第三FinFET管的前栅、第四FinFET管的漏极、第六FinFET管的漏极和第七FinFET管的前栅连接且其连接端为读写分离存储单元的反相输出端；第三FinFET管的源极、第三FinFET管的背栅、第四FinFET管的背栅、第四FinFET管的源极和第七FinFET管的源极均接地；第五FinFET管的前栅、第五FinFET管的背栅、第六FinFET管的背栅和第六FinFET管的前栅连接且其连接线为读写分离存储单元的写字线；第五FinFET管的源极为读写分离存储单元的写位线；第六FinFET管的源极为读写分离存储单元的写位线反向控制端；第七FinFET管的漏极为读写分离存储单元的读位线；第七FinFET管的背栅为读写分离存储单元的读字线；本发明的基于FinFET器件的读写分离存储单元读写操作分离，写字线WRWL为高电平，第五FinFET管和第六FinFET管导通，写位线WRBL进行读操作，写位线WRBL和写位线反向控制端之间形成电位差，读位线RDWL为高电平时，第七FinFET管作为分栅管用于读操作，读操作完成通过写操作控制进行写操作，不会破坏存储单元数据，从而存储单元有更多的优化空间用于提高写噪声容限，其内包含的FinFET管的背栅接至高电压/低电压，或者接为同栅，可调整各晶体管的性能，从而改善存储单元的噪声容，本发明的基于FinFET器件的读写分离存储单元具有正确的工作逻辑，并且其电路结构简单，采用数量较少的晶体管来实现存储单元功能，读操作和写操作分开，读写互不干扰，延时、功耗和功耗延时积均较小；Compared with the prior art, the present invention has the advantage that the first FinFET tube, the second FinFET tube, the third FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube FinFET tubes constitute a read-write separation storage unit based on FinFET devices. The first FinFET tube and the second FinFET tube are both P-type FinFET tubes. The third FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube and the The seven FinFET tubes are all N-type FinFET tubes, the number of fins of the first FinFET tube and the second FinFET tube is 2, the third FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube The number of fins of the tube is 1; the source of the first FinFET and the source of the second FinFET are connected to the power supply, the drain of the first FinFET, the front gate of the second FinFET, and the The back gate, the drain of the third FinFET tube, the front gate of the fourth FinFET tube and the drain of the fifth FinFET tube are connected and the connection end is the output end of the read-write separation memory unit, the front gate of the first FinFET tube, the The back gate of a FinFET tube, the drain of the second FinFET tube, the front gate of the third FinFET tube, the drain of the fourth FinFET tube, the drain of the sixth FinFET tube and the front gate of the seventh FinFET tube are connected and connected The end is the inverting output end of the read-write separation memory unit; the source of the third FinFET, the back gate of the third FinFET, the back gate of the fourth FinFET, the source of the fourth FinFET and the back gate of the seventh FinFET The sources are all grounded; the front gate of the fifth FinFET, the back gate of the fifth FinFET, the back gate of the sixth FinFET, and the front gate of the sixth FinFET are connected, and the connection line is the write word line of the read-write separation memory unit ; The source of the fifth FinFET tube is the write bit line of the read-write separation storage unit; the source of the sixth FinFET tube is the reverse control terminal of the write bit line of the read-write separation storage unit; the drain of the seventh FinFET tube is the read-write separation storage unit The read bit line of the unit; the back gate of the seventh FinFET tube is the read word line of the read-write separation memory unit; the read-write separation memory unit based on the FinFET device of the present invention is separated from the read-write operation, the write word line WRWL is high level, and the first The fifth FinFET tube and the sixth FinFET tube are turned on, the write bit line WRBL performs a read operation, and the write bit line WRBL and the reverse control terminal of the write bit line A potential difference is formed between them. When the read bit line RDWL is at a high level, the seventh FinFET tube is used as a sub-gate tube for the read operation. After the read operation is completed, the write operation is controlled by the write operation, and the data of the storage unit will not be destroyed, so that the storage unit has more A lot of optimization space is used to improve the write noise tolerance. The back gate of the FinFET tube contained in it is connected to high voltage/low voltage, or connected to the same gate, which can adjust the performance of each transistor, thereby improving the noise tolerance of the memory unit. The invented read-write separation storage unit based on FinFET devices has correct working logic, and its circuit structure is simple, and a small number of transistors are used to realize the function of the storage unit. , power consumption and power consumption delay product are small;
当第一FinFET管、第二FinFET管、第三FinFET管、第四FinFET管、第五FinFET管和第六FinFET管均为低阈值FinFET管，第七FinFET管为高阈值FinFET管时。第一FinFET管、第二FinFET管、第五FinFET管和第六FinFET管均为低阈值FinFET管且均为共栅连接模式，保证电路速度。第三FinFET管和第四FinFET管背栅接地，降低电路功耗。第七FinFET管为高阈值FinFET管保证电路功能正确且功耗较低。When the first FinFET, the second FinFET, the third FinFET, the fourth FinFET, the fifth FinFET and the sixth FinFET are all low-threshold FinFETs, and the seventh FinFET is a high-threshold FinFET. The first FinFET tube, the second FinFET tube, the fifth FinFET tube and the sixth FinFET tube are all low-threshold FinFET tubes and are all in a common-gate connection mode to ensure circuit speed. The back gates of the third FinFET tube and the fourth FinFET tube are grounded to reduce power consumption of the circuit. The seventh FinFET tube is a high-threshold FinFET tube to ensure correct circuit function and low power consumption.
当第一FinFET管、第二FinFET管、第三FinFET管、第四FinFET管、第五FinFET管和第六FinFET管均的阈值电压均为0.1v，第七FinFET管的阈值电压为0.6v时，阈值电压为0.1v时，FinFET管运行速度快；阈值电压为0.6v时，FinFET管功耗较低。When the threshold voltages of the first FinFET, the second FinFET, the third FinFET, the fourth FinFET, the fifth FinFET and the sixth FinFET are all 0.1v, and the threshold voltage of the seventh FinFET is 0.6v , when the threshold voltage is 0.1v, the FinFET tube runs fast; when the threshold voltage is 0.6v, the FinFET tube consumes less power.
附图说明Description of drawings
图1为BSIMIMG工艺库中经典存储单元的电路图；Figure 1 is a circuit diagram of a classic memory cell in the BSIMIMG process library;
图2为本发明的基于FinFET器件的读写分离存储单元的电路图；Fig. 2 is the circuit diagram of the read-write separation storage unit based on FinFET device of the present invention;
图3为标准电压(1v)下，本发明的基于FinFET器件的读写分离存储单元在BSIMIMG标准工艺下的仿真波形图；Fig. 3 is under the standard voltage (1v), the emulation waveform diagram of the read-write separation storage unit based on FinFET device of the present invention under the BSIMIMG standard process;
图4为超阈值电压(0.8v)下，本发明的基于FinFET器件的读写分离存储单元在BSIMIMG标准工艺下的仿真波形图。FIG. 4 is a simulation waveform diagram of the read-write separation memory unit based on the FinFET device of the present invention under the BSIMIMG standard process under the ultra-threshold voltage (0.8v).
具体实施方式detailed description
以下结合附图实施例对本发明的基于FinFET器件的读写分离存储单元作进一步详细描述。The read-write separation storage unit based on the FinFET device of the present invention will be further described in detail below with reference to the embodiments of the accompanying drawings.
实施例一：如图2所示，一种基于FinFET器件的读写分离存储单元，包括第一FinFET管M1、第二FinFET管M2、第三FinFET管M3、第四FinFET管M4、第五FinFET管M5、第六FinFET管M6和第七FinFET管M7，第一FinFET管M1和第二FinFET管M2均为P型FinFET管，第三FinFET管M3、第四FinFET管M4、第五FinFET管M5、第六FinFET管M6和第七FinFET管M7均为N型FinFET管，第一FinFET管M1和第二FinFET管M2的鳍的数量均为2，第三FinFET管M3、第四FinFET管M4、第五FinFET管M5、第六FinFET管M6和第七FinFET管M7的鳍的数量均为1；第一FinFET管M1的源极和第二FinFET管M2的源极均接入电源，第一FinFET管M1的漏极、第二FinFET管M2的前栅、第二FinFET管M2的背栅、第三FinFET管M3的漏极、第四FinFET管M4的前栅和第五FinFET管M5的漏极连接且其连接端为读写分离存储单元的输出端，第一FinFET管M1的前栅、第一FinFET管M1的背栅、第二FinFET管M2的漏极、第三FinFET管M3的前栅、第四FinFET管M4的漏极、第六FinFET管M6的漏极和第七FinFET管M7的前栅连接且其连接端为读写分离存储单元的反相输出端；第三FinFET管M3的源极、第三FinFET管M3的背栅、第四FinFET管M4的背栅、第四FinFET管M4的源极和第七FinFET管M7的源极均接地；第五FinFET管M5的前栅、第五FinFET管M5的背栅、第六FinFET管M6的背栅和第六FinFET管M6的前栅连接且其连接线为读写分离存储单元的写字线WRWL；第五FinFET管M5的源极为读写分离存储单元的写位线WRBL；第六FinFET管M6的源极为读写分离存储单元的写位线反向控制端第七FinFET管M7的漏极为读写分离存储单元的读位线RDBL；第七FinFET管M7的背栅为读写分离存储单元的读字线RDWL。Embodiment 1: As shown in Figure 2, a read-write separation storage unit based on FinFET devices includes a first FinFET tube M1, a second FinFET tube M2, a third FinFET tube M3, a fourth FinFET tube M4, and a fifth FinFET tube The tube M5, the sixth FinFET tube M6 and the seventh FinFET tube M7, the first FinFET tube M1 and the second FinFET tube M2 are all P-type FinFET tubes, the third FinFET tube M3, the fourth FinFET tube M4, and the fifth FinFET tube M5 , the sixth FinFET tube M6 and the seventh FinFET tube M7 are both N-type FinFET tubes, the number of fins of the first FinFET tube M1 and the second FinFET tube M2 is 2, the third FinFET tube M3, the fourth FinFET tube M4, The number of fins of the fifth FinFET M5, the sixth FinFET M6 and the seventh FinFET M7 is 1; the source of the first FinFET M1 and the source of the second FinFET M2 are connected to the power supply, and the first FinFET The drain of the tube M1, the front gate of the second FinFET tube M2, the back gate of the second FinFET tube M2, the drain of the third FinFET tube M3, the front gate of the fourth FinFET tube M4, and the drain of the fifth FinFET tube M5 The connection end is the output end of the read-write separation memory unit, the front gate of the first FinFET tube M1, the back gate of the first FinFET tube M1, the drain of the second FinFET tube M2, and the front gate of the third FinFET tube M3 , the drain of the fourth FinFET M4, the drain of the sixth FinFET M6 and the front gate of the seventh FinFET M7 are connected, and the connection end is the inverting output end of the read-write separation memory unit; the third FinFET M3 The source, the back gate of the third FinFET M3, the back gate of the fourth FinFET M4, the source of the fourth FinFET M4 and the source of the seventh FinFET M7 are all grounded; the front gate of the fifth FinFET M5, The back gate of the fifth FinFET tube M5, the back gate of the sixth FinFET tube M6 and the front gate of the sixth FinFET tube M6 are connected, and the connecting line is the write word line WRWL of the read-write separation memory unit; the source of the fifth FinFET tube M5 is The write bit line WRBL of the read-write separation memory unit; the source of the sixth FinFET tube M6 is the reverse control terminal of the write bit line of the read-write separation memory unit The drain of the seventh FinFET M7 is the read bit line RDBL of the read-write separation memory unit; the back gate of the seventh FinFET M7 is the read word line RDWL of the read-write separation memory unit.
实施例二：如图2所示，一种基于FinFET器件的读写分离存储单元，包括第一FinFET管M1、第二FinFET管M2、第三FinFET管M3、第四FinFET管M4、第五FinFET管M5、第六FinFET管M6和第七FinFET管M7，第一FinFET管M1和第二FinFET管M2均为P型FinFET管，第三FinFET管M3、第四FinFET管M4、第五FinFET管M5、第六FinFET管M6和第七FinFET管M7均为N型FinFET管，第一FinFET管M1和第二FinFET管M2的鳍的数量均为2，第三FinFET管M3、第四FinFET管M4、第五FinFET管M5、第六FinFET管M6和第七FinFET管M7的鳍的数量均为1；第一FinFET管M1的源极和第二FinFET管M2的源极均接入电源，第一FinFET管M1的漏极、第二FinFET管M2的前栅、第二FinFET管M2的背栅、第三FinFET管M3的漏极、第四FinFET管M4的前栅和第五FinFET管M5的漏极连接且其连接端为读写分离存储单元的输出端，第一FinFET管M1的前栅、第一FinFET管M1的背栅、第二FinFET管M2的漏极、第三FinFET管M3的前栅、第四FinFET管M4的漏极、第六FinFET管M6的漏极和第七FinFET管M7的前栅连接且其连接端为读写分离存储单元的反相输出端；第三FinFET管M3的源极、第三FinFET管M3的背栅、第四FinFET管M4的背栅、第四FinFET管M4的源极和第七FinFET管M7的源极均接地；第五FinFET管M5的前栅、第五FinFET管M5的背栅、第六FinFET管M6的背栅和第六FinFET管M6的前栅连接且其连接线为读写分离存储单元的写字线WRWL；第五FinFET管M5的源极为读写分离存储单元的写位线WRBL；第六FinFET管M6的源极为读写分离存储单元的写位线反向控制端第七FinFET管M7的漏极为读写分离存储单元的读位线RDBL；第七FinFET管M7的背栅为读写分离存储单元的读字线RDWL。Embodiment 2: As shown in FIG. 2, a read-write separation storage unit based on FinFET devices includes a first FinFET tube M1, a second FinFET tube M2, a third FinFET tube M3, a fourth FinFET tube M4, and a fifth FinFET tube. The tube M5, the sixth FinFET tube M6 and the seventh FinFET tube M7, the first FinFET tube M1 and the second FinFET tube M2 are all P-type FinFET tubes, the third FinFET tube M3, the fourth FinFET tube M4, and the fifth FinFET tube M5 , the sixth FinFET tube M6 and the seventh FinFET tube M7 are both N-type FinFET tubes, the number of fins of the first FinFET tube M1 and the second FinFET tube M2 is 2, the third FinFET tube M3, the fourth FinFET tube M4, The number of fins of the fifth FinFET M5, the sixth FinFET M6 and the seventh FinFET M7 is 1; the source of the first FinFET M1 and the source of the second FinFET M2 are connected to the power supply, and the first FinFET The drain of the tube M1, the front gate of the second FinFET tube M2, the back gate of the second FinFET tube M2, the drain of the third FinFET tube M3, the front gate of the fourth FinFET tube M4, and the drain of the fifth FinFET tube M5 The connection end is the output end of the read-write separation memory unit, the front gate of the first FinFET tube M1, the back gate of the first FinFET tube M1, the drain of the second FinFET tube M2, and the front gate of the third FinFET tube M3 , the drain of the fourth FinFET M4, the drain of the sixth FinFET M6 and the front gate of the seventh FinFET M7 are connected, and the connection end is the inverting output end of the read-write separation memory unit; the third FinFET M3 The source, the back gate of the third FinFET M3, the back gate of the fourth FinFET M4, the source of the fourth FinFET M4 and the source of the seventh FinFET M7 are all grounded; the front gate of the fifth FinFET M5, The back gate of the fifth FinFET tube M5, the back gate of the sixth FinFET tube M6 and the front gate of the sixth FinFET tube M6 are connected, and the connecting line is the write word line WRWL of the read-write separation memory unit; the source of the fifth FinFET tube M5 is The write bit line WRBL of the read-write separation memory unit; the source of the sixth FinFET tube M6 is the reverse control terminal of the write bit line of the read-write separation memory unit The drain of the seventh FinFET M7 is the read bit line RDBL of the read-write separation memory unit; the back gate of the seventh FinFET M7 is the read word line RDWL of the read-write separation memory unit.
本实施例中，第一FinFET管M1、第二FinFET管M2、第三FinFET管M3、第四FinFET管M4、第五FinFET管M5和第六FinFET管M6均为低阈值FinFET管，第七FinFET管M7为高阈值FinFET管。In this embodiment, the first FinFET tube M1, the second FinFET tube M2, the third FinFET tube M3, the fourth FinFET tube M4, the fifth FinFET tube M5, and the sixth FinFET tube M6 are all low-threshold FinFET tubes, and the seventh FinFET tube M6 is a low-threshold FinFET tube. The tube M7 is a high-threshold FinFET tube.
实施例三：如图2所示，一种基于FinFET器件的读写分离存储单元，包括第一FinFET管M1、第二FinFET管M2、第三FinFET管M3、第四FinFET管M4、第五FinFET管M5、第六FinFET管M6和第七FinFET管M7，第一FinFET管M1和第二FinFET管M2均为P型FinFET管，第三FinFET管M3、第四FinFET管M4、第五FinFET管M5、第六FinFET管M6和第七FinFET管M7均为N型FinFET管，第一FinFET管M1和第二FinFET管M2的鳍的数量均为2，第三FinFET管M3、第四FinFET管M4、第五FinFET管M5、第六FinFET管M6和第七FinFET管M7的鳍的数量均为1；第一FinFET管M1的源极和第二FinFET管M2的源极均接入电源，第一FinFET管M1的漏极、第二FinFET管M2的前栅、第二FinFET管M2的背栅、第三FinFET管M3的漏极、第四FinFET管M4的前栅和第五FinFET管M5的漏极连接且其连接端为读写分离存储单元的输出端，第一FinFET管M1的前栅、第一FinFET管M1的背栅、第二FinFET管M2的漏极、第三FinFET管M3的前栅、第四FinFET管M4的漏极、第六FinFET管M6的漏极和第七FinFET管M7的前栅连接且其连接端为读写分离存储单元的反相输出端；第三FinFET管M3的源极、第三FinFET管M3的背栅、第四FinFET管M4的背栅、第四FinFET管M4的源极和第七FinFET管M7的源极均接地；第五FinFET管M5的前栅、第五FinFET管M5的背栅、第六FinFET管M6的背栅和第六FinFET管M6的前栅连接且其连接线为读写分离存储单元的写字线WRWL；第五FinFET管M5的源极为读写分离存储单元的写位线WRBL；第六FinFET管M6的源极为读写分离存储单元的写位线反向控制端第七FinFET管M7的漏极为读写分离存储单元的读位线RDBL；第七FinFET管M7的背栅为读写分离存储单元的读字线RDWL。Embodiment 3: As shown in FIG. 2 , a read-write separation storage unit based on FinFET devices includes a first FinFET tube M1, a second FinFET tube M2, a third FinFET tube M3, a fourth FinFET tube M4, and a fifth FinFET tube. The tube M5, the sixth FinFET tube M6 and the seventh FinFET tube M7, the first FinFET tube M1 and the second FinFET tube M2 are all P-type FinFET tubes, the third FinFET tube M3, the fourth FinFET tube M4, and the fifth FinFET tube M5 , the sixth FinFET tube M6 and the seventh FinFET tube M7 are both N-type FinFET tubes, the number of fins of the first FinFET tube M1 and the second FinFET tube M2 is 2, the third FinFET tube M3, the fourth FinFET tube M4, The number of fins of the fifth FinFET M5, the sixth FinFET M6 and the seventh FinFET M7 is 1; the source of the first FinFET M1 and the source of the second FinFET M2 are connected to the power supply, and the first FinFET The drain of the tube M1, the front gate of the second FinFET tube M2, the back gate of the second FinFET tube M2, the drain of the third FinFET tube M3, the front gate of the fourth FinFET tube M4, and the drain of the fifth FinFET tube M5 The connection end is the output end of the read-write separation memory unit, the front gate of the first FinFET tube M1, the back gate of the first FinFET tube M1, the drain of the second FinFET tube M2, and the front gate of the third FinFET tube M3 , the drain of the fourth FinFET M4, the drain of the sixth FinFET M6 and the front gate of the seventh FinFET M7 are connected, and the connection end is the inverting output end of the read-write separation memory unit; the third FinFET M3 The source, the back gate of the third FinFET M3, the back gate of the fourth FinFET M4, the source of the fourth FinFET M4 and the source of the seventh FinFET M7 are all grounded; the front gate of the fifth FinFET M5, The back gate of the fifth FinFET tube M5, the back gate of the sixth FinFET tube M6 and the front gate of the sixth FinFET tube M6 are connected, and the connecting line is the write word line WRWL of the read-write separation memory unit; the source of the fifth FinFET tube M5 is The write bit line WRBL of the read-write separation memory unit; the source of the sixth FinFET tube M6 is the reverse control terminal of the write bit line of the read-write separation memory unit The drain of the seventh FinFET M7 is the read bit line RDBL of the read-write separation memory unit; the back gate of the seventh FinFET M7 is the read word line RDWL of the read-write separation memory unit.
本实施例中，第一FinFET管M1、第二FinFET管M2、第三FinFET管M3、第四FinFET管M4、第五FinFET管M5和第六FinFET管M6均为低阈值FinFET管，第七FinFET管M7为高阈值FinFET管。In this embodiment, the first FinFET tube M1, the second FinFET tube M2, the third FinFET tube M3, the fourth FinFET tube M4, the fifth FinFET tube M5, and the sixth FinFET tube M6 are all low-threshold FinFET tubes, and the seventh FinFET tube M6 is a low-threshold FinFET tube. The tube M7 is a high-threshold FinFET tube.
本实施例中，第一FinFET管M1、第二FinFET管M2、第三FinFET管M3、第四FinFET管M4、第五FinFET管M5和第六FinFET管M6均的阈值电压均为0.1v，第七FinFET管M7的阈值电压为0.6v。In this embodiment, the threshold voltages of the first FinFET M1, the second FinFET M2, the third FinFET M3, the fourth FinFET M4, the fifth FinFET M5, and the sixth FinFET M6 are all 0.1v. The threshold voltage of the seven FinFET tube M7 is 0.6v.
为了验证本发明的基于FinFET器件的读写分离存储单元的优益性，在BSIMIMG标准工艺下，电路的输入频率为400MHz、800MHz、1GHz、2G的条件下,使用电路仿真工具HSPICE对本发明的基于FinFET器件的读写分离存储单元和图1所示的BSIMIMG工艺库中经典六管存储单元这两种电路的性能进行仿真对比，其中，BSIMIMG工艺库对应的电源电压为1V。标准电压(1v)下，本发明的基于FinFET器件的读写分离存储单元基于BSIMIMG标准工艺仿真波形图如图3所示；超阈值电压(0.8v)下，本发明的基于FinFET器件的读写分离存储单元基于BSIMIMG标准工艺仿真波形图如图4所示。分析图3和图4可知，本发明的基于FinFET器件的读写分离存储单元具有正确的工作逻辑。In order to verify the superiority of the read-write separation storage unit based on the FinFET device of the present invention, under the BSIMIMG standard process, the input frequency of the circuit is 400MHz, 800MHz, 1GHz, 2G conditions, use the circuit simulation tool HSPICE to the present invention based on The performance of the read-write separation memory unit of the FinFET device and the classic six-tube memory unit in the BSIMIMG process library shown in Figure 1 is simulated and compared. The power supply voltage corresponding to the BSIMIMG process library is 1V. Under the standard voltage (1v), the reading and writing separation storage unit based on the FinFET device of the present invention is based on the BSIMIMG standard process simulation waveform diagram as shown in Figure 3; under the super threshold voltage (0.8v), the reading and writing based on the FinFET device of the present invention The simulation waveform diagram of the separated storage unit based on the BSIMIMG standard process is shown in Figure 4. Analysis of Fig. 3 and Fig. 4 shows that the read-write separation memory unit based on the FinFET device of the present invention has correct working logic.
表1为在BSIMIMG标准工艺下，输入频率为400MHz时，本发明的基于FinFET器件的读写分离存储单元和图1所示的BSIMIMG工艺库中经典六管存储单元两种电路的性能比较图。Table 1 is a performance comparison diagram of two circuits of the classic six-tube memory unit in the BSIMIMG process library shown in FIG.
表1Table 1
从表1中可以得出：本发明的基于FinFET器件的读写分离存储单元与和图1所示的BSIMIMG工艺库中经典六管存储单元相比，延时降低了7.4％，平均总功耗降低了1.7％，功耗延时积降低了8.8％。From Table 1, it can be drawn that the read-write separation storage unit based on the FinFET device of the present invention is compared with the classic six-tube storage unit in the BSIMIMG process library shown in Figure 1, the delay is reduced by 7.4%, and the average total power consumption 1.7% reduction and 8.8% reduction in power delay product.
表2为在BSIMIMG标准工艺下，输入频率为400MHz时，本发明的基于FinFET器件的读写分离存储单元和图1所示的BSIMIMG工艺库中经典六管存储单元两种电路的性能比较图。Table 2 is a performance comparison diagram of two circuits of the classic six-tube memory unit in the BSIMIMG process library shown in FIG.
表2Table 2
从表2中可以得出：本发明的基于FinFET器件的读写分离存储单元与和图1所示的BSIMIMG工艺库中经典六管存储单元相比，延时降低了7.4％，平均总功耗降低了2.4％，功耗延时积降低了9.5％。From Table 2, it can be drawn that the read-write separation storage unit based on the FinFET device of the present invention is compared with the classic six-tube storage unit in the BSIMIMG process library shown in Figure 1, the delay is reduced by 7.4%, and the average total power consumption 2.4% reduction and 9.5% reduction in power delay product.
表3为在BSIMIMG标准工艺下，输入频率为1G Hz时，本发明的基于FinFET器件的读写分离存储单元和图1所示的BSIMIMG工艺库中经典六管存储单元两种电路的性能比较图。Table 3 is a performance comparison diagram of two circuits of the classic six-tube storage unit in the BSIMIMG process library shown in Figure 1 and the read-write separation storage unit based on the FinFET device of the present invention when the input frequency is 1 GHz under the BSIMIMG standard process .
表3table 3
从表3中可以得出：本发明的基于FinFET器件的读写分离存储单元与和图1所示的BSIMIMG工艺库中经典六管存储单元相比，延时降低了7.4％，平均总功耗降低了2.6％，功耗延时积降低了9.8％。From Table 3, it can be drawn that the read-write separation storage unit based on the FinFET device of the present invention is compared with the classic six-tube storage unit in the BSIMIMG process library shown in Figure 1, the delay is reduced by 7.4%, and the average total power consumption 2.6% reduction and 9.8% reduction in power delay product.
表4为在BSIMIMG标准工艺下，输入频率为2G Hz时，本发明的基于FinFET器件的读写分离存储单元和图1所示的BSIMIMG工艺库中经典六管存储单元两种电路的性能比较图。Table 4 is a performance comparison diagram of two circuits of the classic six-tube memory unit in the BSIMIMG process library shown in Figure 1 and the read-write separation memory unit based on the FinFET device of the present invention when the input frequency is 2GHz under the BSIMIMG standard process .
表4Table 4
从表4中可以得出：本发明的基于FinFET器件的读写分离存储单元与和图1所示的BSIMIMG工艺库中经典六管存储单元相比，延时降低了7.4％，平均总功耗降低了3.3％，功耗延时积降低了10.5％。From Table 4, it can be drawn that the read-write separation storage unit based on the FinFET device of the present invention is compared with the classic six-tube storage unit in the BSIMIMG process library shown in Figure 1, the delay is reduced by 7.4%, and the average total power consumption 3.3% reduction and 10.5% reduction in power delay product.
由上述的比较数据可见，在不影响电路性能的前提下，本发明的基于FinFET器件的读写分离存储单元和图1所示的BSIMIMG工艺库中经典六管存储单元相比较，延时得到优化，运行速度得到了提高；电路的功耗和功耗延时积也得到了优化。It can be seen from the above comparison data that, under the premise of not affecting the circuit performance, compared with the classic six-tube storage unit in the BSIMIMG process library shown in Figure 1, the delay is optimized. , the operating speed has been improved; the power consumption and power consumption delay product of the circuit have also been optimized.
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| CN107393584B (en) * | 2017-06-19 | 2019-09-10 | 宁波大学 | A kind of single-ended reading storage unit of full swing based on FinFET |
| CN107369469B (en) * | 2017-06-19 | 2020-04-17 | 宁波大学 | Five-tube storage unit based on FinFET device |
| CN108461104A (en) * | 2018-02-02 | 2018-08-28 | 宁波大学 | A kind of single-ended read-write memory cell based on FinFET |
| CN108461104B (en) * | 2018-02-02 | 2020-04-17 | 宁波大学 | Single-ended read-write storage unit based on FinFET |
| CN108511014A (en) * | 2018-02-07 | 2018-09-07 | 宁波大学 | A kind of storage unit based on FinFET |
| CN108447515A (en) * | 2018-02-12 | 2018-08-24 | 宁波大学 | A FinFET-based read-write separation storage unit |
| CN110767251A (en) * | 2019-10-16 | 2020-02-07 | 安徽大学 | A 11T TFET SRAM cell circuit structure with low power consumption and high write margin |
| CN110767251B (en) * | 2019-10-16 | 2021-09-14 | 安徽大学 | 11T TFET SRAM unit circuit structure with low power consumption and high write margin |
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