CN106448725A - Read/write splitting memory cell based on FinFET (fin field-effect transistor) devices - Google Patents
Read/write splitting memory cell based on FinFET (fin field-effect transistor) devices Download PDFInfo
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- CN106448725A CN106448725A CN201610836865.0A CN201610836865A CN106448725A CN 106448725 A CN106448725 A CN 106448725A CN 201610836865 A CN201610836865 A CN 201610836865A CN 106448725 A CN106448725 A CN 106448725A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
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Abstract
The invention discloses a read/write splitting memory cell based on FinFET (fin field-effect transistor) devices. The read/write splitting memory cell is characterized by comprising a first FinFET, a second FinFET, a third FinFET, a fourth FinFET, a fifth FinFET, a sixth FinFET and a seventh FinFET, wherein the first FinFET and the second FinFET are P-type FinFETs; the third FinFET, the fourth FinFET, the fifth FinFET, the sixth FinFET and the seventh FinFET are N-type FinFETs; the number of fins of each of the first FinFET and the second FinFET is 2; the number of fins of each of the third FinFET, the fourth FinFET, the fifth FinFET, the sixth FinFET and the seventh FinFET is 1. The read/write splitting memory cell has the advantages that a circuit structure is simple; the functions of the memory cell are achieved by adopting a smaller number of transistors; read operation and write operation are split, so read and write do not interfere with each other; the delay, the power consumption and the power-delay product are smaller.
Description
Technical field
The present invention relates to a kind of memory element, especially relates to a kind of read and write abruption storage based on FinFET single
Unit.
Background technology
As process enters nanoscale, power consumption becomes the problem that IC designer must not be not concerned with.In big portion
Point digital display circuit in memorizer power consumption occupy way circuit power consumption ratio increasing.Static RAM
(SRAM, Static Random Access Memory), is an important ingredient in memory, thus designs low
SRAM has important Research Significance.Static RAM is mainly by storage array and other peripheral circuit structures
Become, and storage array is made up of memory element, memory element is the core of static RAM, memory element is directly determined
Determine the performance of static RAM.
Time delay, power consumption and power-consumption design are main three factors for embodying memory element performance, optimize these three factors
The performance of memory element can be optimized so as to the performance of static RAM total system is improved, wherein, power consumption time delay
Product is power consumption and the product of time delay, and unit is that joule, therefore power-consumption design is the measurement of energy, can be used as a derailing switch
The tolerance of part performance.In the case that power-consumption design is basically unchanged, area is also a key factor for restricting circuit performance.
FinFET pipe (fin field-effect transistor, Fin Field-Effect Transistor) is a kind of new complementary
Metal-oxide-semiconductor (MOS) (CMOS) transistor, with low in energy consumption, the little advantage of area.In view of this, designing one kind is not affecting circuit performance
In the case of, all less read and write abruption storages based on FinFET of circuit area, time delay, power consumption and power-consumption design are single
Unit is significant.
Content of the invention
The technical problem to be solved is to provide one kind in the case of circuit performance is not affected, circuit area,
Time delay, power consumption and power-consumption design all less read and write abruption memory element based on FinFET.
The present invention solves the technical scheme that adopted of above-mentioned technical problem：A kind of read and write abruption based on FinFET
Memory element, including FinFET pipe, the 2nd FinFET pipe, the 3rd FinFET pipe, the 4th FinFET pipe, the 5th FinFET
Pipe, the 6th FinFET pipe and the 7th FinFET pipe, described FinFET pipe and the 2nd described FinFET pipe are p-type
FinFET is managed, described 3rd FinFET pipe, described the 4th FinFET pipe, described the 5th FinFET pipe, the described the 6th
FinFET pipe and the 7th described FinFET pipe are N-type FinFET pipe, and a described FinFET is managed and described second
The quantity of the fin of FinFET pipe is 2, described the 3rd FinFET pipe, described the 4th FinFET pipe, the described the 5th
The quantity of the fin of FinFET pipe, described the 6th FinFET pipe and the 7th described FinFET pipe is 1；Described first
The source electrode of the source electrode of FinFET pipe and the 2nd described FinFET pipe all accesses power supply, the drain electrode of a described FinFET pipe,
The front gate, the backgate of the 2nd described FinFET pipe of the 2nd described FinFET pipe, the drain electrode of the 3rd described FinFET pipe, institute
The drain electrode of the front gate of the 4th FinFET pipe that states and the 5th described FinFET pipe connects and its connection end is that described read-write divides
From the outfan of memory element, the front gate of a described FinFET pipe, the backgate of a described FinFET pipe, described
The drain electrode of two FinFET pipes, the front gate of the 3rd described FinFET pipe, the drain electrode of the 4th described FinFET pipe, the described the 6th
The front gate of the drain electrode of FinFET pipe and the 7th described FinFET pipe connects and its connection end is that described read and write abruption storage is single
The reversed-phase output of unit；The source electrode of the 3rd described FinFET pipe, the backgate of the 3rd described FinFET pipe, the described the 4th
The source grounding of the backgate of FinFET pipe, the source electrode of the 4th described FinFET pipe and the 7th described FinFET pipe；Described
The front gate of the 5th FinFET pipe, the backgate of the 5th described FinFET pipe, the backgate of the 6th described FinFET pipe and described
The front gate connection of the 6th FinFET pipe and its connecting line be described read and write abruption memory element write word line；Described the 5th
The source electrode of FinFET pipe is the write bit line of described read and write abruption memory element；The source electrode of the 6th described FinFET pipe is described
Read and write abruption memory element write bit line Reverse Turning Control end；The drain electrode of the 7th described FinFET pipe is described read and write abruption
The sense bit line of memory element；The backgate of the 7th described FinFET pipe is the readout word line of described read and write abruption memory element.
Described FinFET pipe, described the 2nd FinFET pipe, described the 3rd FinFET pipe, the described the 4th
FinFET pipe, described 5th FinFET pipe and the 6th described FinFET pipe are Low threshold FinFET pipe, and the described 7th
FinFET pipe is managed for high threshold FinFET.
Described FinFET pipe, described the 2nd FinFET pipe, described the 3rd FinFET pipe, the described the 4th
The equal threshold voltage of FinFET pipe, described 5th FinFET pipe and described the 6th FinFET pipe is 0.1v, and described the
The threshold voltage of seven FinFET pipes is 0.6v.
Compared with prior art, it is an advantage of the current invention that by a FinFET manage, the 2nd FinFET pipe, the 3rd
FinFET pipe, the 4th FinFET pipe, the 5th FinFET pipe, the 6th FinFET pipe and the 7th FinFET manage this seven FinFET pipe structures
The read and write abruption memory element based on FinFET, FinFET pipe and the 2nd FinFET pipe is become to be p-type FinFET pipe,
3rd FinFET pipe, the 4th FinFET pipe, the 5th FinFET pipe, the 6th FinFET pipe and the 7th FinFET pipe are N-type
FinFET manage, a FinFET pipe and the 2nd FinFET pipe fin quantity be 2, the 3rd FinFET pipe, the 4th FinFET pipe,
The quantity of the fin of the 5th FinFET pipe, the 6th FinFET pipe and the 7th FinFET pipe is 1；The source electrode of the first FinFET pipe and
The source electrode of two FinFET pipes all accesses power supply, the drain electrode of a FinFET pipe, the front gate of the 2nd FinFET pipe, the 2nd FinFET pipe
Backgate, the drain electrode, the front gate of the 4th FinFET pipe and the 5th FinFET pipe of the 3rd FinFET pipe drain electrode connection and its connection
Hold the outfan for read and write abruption memory element, the front gate of a FinFET pipe, the backgate of a FinFET pipe, the 2nd FinFET
The drain electrode of pipe, the front gate of the 3rd FinFET pipe, the drain electrode of the 4th FinFET pipe, the drain electrode of the 6th FinFET pipe and the 7th FinFET
The front gate of pipe connects and its connection end is the reversed-phase output of read and write abruption memory element；The source electrode of the 3rd FinFET pipe, the 3rd
The backgate of FinFET pipe, the backgate of the 4th FinFET pipe, the source electrode of the 4th FinFET pipe and the source electrode of the 7th FinFET pipe all connect
Ground；Before the front gate, the backgate of the 5th FinFET pipe, the backgate of the 6th FinFET pipe of the 5th FinFET pipe and the 6th FinFET pipe
Grid connect and its connecting line is the write word line of read and write abruption memory element；The source electrode of the 5th FinFET pipe is single for read and write abruption storage
The write bit line of unit；The source electrode of the 6th FinFET pipe is the write bit line Reverse Turning Control end of read and write abruption memory element；7th FinFET
The drain electrode of pipe is the sense bit line of read and write abruption memory element；The backgate of the 7th FinFET pipe is the reading word of read and write abruption memory element
Line；The read and write abruption memory element read-write operation based on FinFET of the present invention is separated, and write word line WRWL is high level, the
Five FinFET pipe and the conducting of the 6th FinFET pipe, write bit line WRBL carries out read operation, write bit line WRBL and write bit line Reverse Turning Control
EndBetween form potential difference, when sense bit line RDWL is high level, the 7th FinFET pipe is used for read operation as point bank tube,
Read operation completes to carry out write operation by write operation control, will not destroy memory cell data, have more so as to memory element
Optimizing space and noise margin being write for improving, the backgate of the FinFET pipe for including in which is connected to high voltage/low-voltage, or is connected in
Same grid, can adjust the performance of each transistor, and the noise so as to improve memory element holds, the reading based on FinFET of the present invention
Write discrete memory location and there is correct work-based logic, and its circuit structure is simple, reality is come using the transistor of negligible amounts
Existing functional memory cell, read operation and write operation separate, and read-write does not interfere with each other, and time delay, power consumption and power-consumption design are all less；
When a FinFET pipe, the 2nd FinFET pipe, the 3rd FinFET pipe, the 4th FinFET pipe, the 5th FinFET pipe and
6th FinFET pipe is Low threshold FinFET pipe, when the 7th FinFET pipe is for high threshold FinFET pipe.First FinFET pipe, the
Two FinFET pipe, the 5th FinFET pipe and the 6th FinFET pipe are Low threshold FinFET pipe and are common gate connection pattern, protect
Card circuit speed.3rd FinFET pipe and the 4th FinFET pipe backgate ground connection, reduce circuit power consumption.7th FinFET pipe is high threshold
Value FinFET pipe ensures that circuit function is correct and power consumption is relatively low.
When a FinFET pipe, the 2nd FinFET pipe, the 3rd FinFET pipe, the 4th FinFET pipe, the 5th FinFET pipe and
The equal threshold voltage of 6th FinFET pipe is 0.1v, and when the threshold voltage of the 7th FinFET pipe is 0.6v, threshold voltage is
During 0.1v, the FinFET pipe speed of service is fast；When threshold voltage is 0.6v, FinFET pipe power consumption is relatively low.
Description of the drawings
Fig. 1 is the circuit diagram of classical memory element in BSIMIMG technology library；
Fig. 2 is the circuit diagram of the read and write abruption memory element based on FinFET of the present invention；
Fig. 3 is that under normal voltage (1v), the read and write abruption memory element based on FinFET of the present invention is in BSIMIMG
Simulation waveform under standard technology；
Fig. 4 is that under superthreshold threshold voltage (0.8v), the present invention is existed based on the read and write abruption memory element of FinFET
Simulation waveform under BSIMIMG standard technology.
Specific embodiment
Below in conjunction with accompanying drawing embodiment, the read and write abruption memory element based on FinFET of the present invention is made further
Describe in detail.
Embodiment one：As shown in Fig. 2 a kind of read and write abruption memory element based on FinFET, including first
FinFET pipe M1, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5, the 6th
FinFET pipe M6 and the 7th FinFET pipe M7, a FinFET pipe M1 and the 2nd FinFET pipe M2 are p-type FinFET and manage, and the 3rd
FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5, the 6th FinFET pipe M6 and the 7th FinFET pipe M7 are N
Type FinFET is managed, and the quantity of the fin of a FinFET pipe M1 and the 2nd FinFET pipe M2 is 2, the 3rd FinFET pipe M3, the 4th
FinFET pipe M4, the 5th FinFET pipe M5, the quantity of the fin of the 6th FinFET pipe M6 and the 7th FinFET pipe M7 are 1；First
The source electrode of the source electrode of FinFET pipe M1 and the 2nd FinFET pipe M2 all accesses power supply, the drain electrode of a FinFET pipe M1, second
The front gate of FinFET pipe M2, the backgate of the 2nd FinFET pipe M2, the drain electrode of the 3rd FinFET pipe M3, before the 4th FinFET pipe M4
The drain electrode of grid and the 5th FinFET pipe M5 connects and its connection end is the outfan of read and write abruption memory element, and a FinFET is managed
The front gate of M1, the backgate of a FinFET pipe M1, the drain electrode of the 2nd FinFET pipe M2, the front gate of the 3rd FinFET pipe M3, the 4th
The front gate of the drain electrode of FinFET pipe M4, the drain electrode of the 6th FinFET pipe M6 and the 7th FinFET pipe M7 connects and its connection end is for reading
Write the reversed-phase output of discrete memory location；The source electrode of the 3rd FinFET pipe M3, the backgate of the 3rd FinFET pipe M3, the 4th
The source grounding of the backgate of FinFET pipe M4, the source electrode of the 4th FinFET pipe M4 and the 7th FinFET pipe M7；5th FinFET
The front gate of pipe M5, the front gate of the backgate, the backgate of the 6th FinFET pipe M6 and the 6th FinFET pipe M6 of the 5th FinFET pipe M5 connect
Connect and its connecting line is the write word line WRWL of read and write abruption memory element；The source electrode of the 5th FinFET pipe M5 is stored for read and write abruption
The write bit line WRBL of unit；The source electrode of the 6th FinFET pipe M6 is the write bit line Reverse Turning Control end of read and write abruption memory elementThe drain electrode of the 7th FinFET pipe M7 is the sense bit line RDBL of read and write abruption memory element；The back of the body of the 7th FinFET pipe M7
Grid are the readout word line RDWL of read and write abruption memory element.
Embodiment two：As shown in Fig. 2 a kind of read and write abruption memory element based on FinFET, including first
FinFET pipe M1, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5, the 6th
FinFET pipe M6 and the 7th FinFET pipe M7, a FinFET pipe M1 and the 2nd FinFET pipe M2 are p-type FinFET and manage, and the 3rd
FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5, the 6th FinFET pipe M6 and the 7th FinFET pipe M7 are N
Type FinFET is managed, and the quantity of the fin of a FinFET pipe M1 and the 2nd FinFET pipe M2 is 2, the 3rd FinFET pipe M3, the 4th
FinFET pipe M4, the 5th FinFET pipe M5, the quantity of the fin of the 6th FinFET pipe M6 and the 7th FinFET pipe M7 are 1；First
The source electrode of the source electrode of FinFET pipe M1 and the 2nd FinFET pipe M2 all accesses power supply, the drain electrode of a FinFET pipe M1, second
The front gate of FinFET pipe M2, the backgate of the 2nd FinFET pipe M2, the drain electrode of the 3rd FinFET pipe M3, before the 4th FinFET pipe M4
The drain electrode of grid and the 5th FinFET pipe M5 connects and its connection end is the outfan of read and write abruption memory element, and a FinFET is managed
The front gate of M1, the backgate of a FinFET pipe M1, the drain electrode of the 2nd FinFET pipe M2, the front gate of the 3rd FinFET pipe M3, the 4th
The front gate of the drain electrode of FinFET pipe M4, the drain electrode of the 6th FinFET pipe M6 and the 7th FinFET pipe M7 connects and its connection end is for reading
Write the reversed-phase output of discrete memory location；The source electrode of the 3rd FinFET pipe M3, the backgate of the 3rd FinFET pipe M3, the 4th
The source grounding of the backgate of FinFET pipe M4, the source electrode of the 4th FinFET pipe M4 and the 7th FinFET pipe M7；5th FinFET
The front gate of pipe M5, the front gate of the backgate, the backgate of the 6th FinFET pipe M6 and the 6th FinFET pipe M6 of the 5th FinFET pipe M5 connect
Connect and its connecting line is the write word line WRWL of read and write abruption memory element；The source electrode of the 5th FinFET pipe M5 is stored for read and write abruption
The write bit line WRBL of unit；The source electrode of the 6th FinFET pipe M6 is the write bit line Reverse Turning Control end of read and write abruption memory elementThe drain electrode of the 7th FinFET pipe M7 is the sense bit line RDBL of read and write abruption memory element；The back of the body of the 7th FinFET pipe M7
Grid are the readout word line RDWL of read and write abruption memory element.
In the present embodiment, a FinFET pipe M1, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 4th FinFET pipe
M4, the 5th FinFET pipe M5 and the 6th FinFET pipe M6 are Low threshold FinFET pipe, and the 7th FinFET pipe M7 is high threshold
FinFET is managed.
Embodiment three：As shown in Fig. 2 a kind of read and write abruption memory element based on FinFET, including first
FinFET pipe M1, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5, the 6th
FinFET pipe M6 and the 7th FinFET pipe M7, a FinFET pipe M1 and the 2nd FinFET pipe M2 are p-type FinFET and manage, and the 3rd
FinFET pipe M3, the 4th FinFET pipe M4, the 5th FinFET pipe M5, the 6th FinFET pipe M6 and the 7th FinFET pipe M7 are N
Type FinFET is managed, and the quantity of the fin of a FinFET pipe M1 and the 2nd FinFET pipe M2 is 2, the 3rd FinFET pipe M3, the 4th
FinFET pipe M4, the 5th FinFET pipe M5, the quantity of the fin of the 6th FinFET pipe M6 and the 7th FinFET pipe M7 are 1；First
The source electrode of the source electrode of FinFET pipe M1 and the 2nd FinFET pipe M2 all accesses power supply, the drain electrode of a FinFET pipe M1, second
The front gate of FinFET pipe M2, the backgate of the 2nd FinFET pipe M2, the drain electrode of the 3rd FinFET pipe M3, before the 4th FinFET pipe M4
The drain electrode of grid and the 5th FinFET pipe M5 connects and its connection end is the outfan of read and write abruption memory element, and a FinFET is managed
The front gate of M1, the backgate of a FinFET pipe M1, the drain electrode of the 2nd FinFET pipe M2, the front gate of the 3rd FinFET pipe M3, the 4th
The front gate of the drain electrode of FinFET pipe M4, the drain electrode of the 6th FinFET pipe M6 and the 7th FinFET pipe M7 connects and its connection end is for reading
Write the reversed-phase output of discrete memory location；The source electrode of the 3rd FinFET pipe M3, the backgate of the 3rd FinFET pipe M3, the 4th
The source grounding of the backgate of FinFET pipe M4, the source electrode of the 4th FinFET pipe M4 and the 7th FinFET pipe M7；5th FinFET
The front gate of pipe M5, the front gate of the backgate, the backgate of the 6th FinFET pipe M6 and the 6th FinFET pipe M6 of the 5th FinFET pipe M5 connect
Connect and its connecting line is the write word line WRWL of read and write abruption memory element；The source electrode of the 5th FinFET pipe M5 is stored for read and write abruption
The write bit line WRBL of unit；The source electrode of the 6th FinFET pipe M6 is the write bit line Reverse Turning Control end of read and write abruption memory elementThe drain electrode of the 7th FinFET pipe M7 is the sense bit line RDBL of read and write abruption memory element；The back of the body of the 7th FinFET pipe M7
Grid are the readout word line RDWL of read and write abruption memory element.
In the present embodiment, a FinFET pipe M1, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 4th FinFET pipe
M4, the 5th FinFET pipe M5 and the 6th FinFET pipe M6 are Low threshold FinFET pipe, and the 7th FinFET pipe M7 is high threshold
FinFET is managed.
In the present embodiment, a FinFET pipe M1, the 2nd FinFET pipe M2, the 3rd FinFET pipe M3, the 4th FinFET pipe
The equal threshold voltage of M4, the 5th FinFET pipe M5 and the 6th FinFET pipe M6 is the threshold value electricity of 0.1v, the 7th FinFET pipe M7
Press as 0.6v.
In order to verify the excellent benefit of the read and write abruption memory element based on FinFET of the present invention, mark in BSIMIMG
Under quasi- technique, under conditions of the incoming frequency of circuit is 400MHz, 800MHz, 1GHz, 2G, using circuit simulation tools HSPICE
In the BSIMIMG technology library shown in the read and write abruption memory element based on FinFET and Fig. 1 to the present invention, classical six manage
The performance of memory element both circuits carries out simulation comparison, and wherein, the corresponding supply voltage of BSIMIMG technology library is 1V.Mark
Under quasi- voltage (1v), the read and write abruption memory element based on FinFET of the present invention is emulated based on BSIMIMG standard technology
Oscillogram is as shown in Figure 3；Under superthreshold threshold voltage (0.8v), the read and write abruption memory element base based on FinFET of the present invention
As shown in Figure 4 in BSIMIMG standard technology simulation waveform.Analysis Fig. 3 and Fig. 4 understand, the present invention based on FinFET
Read and write abruption memory element there is correct work-based logic.
Table 1 is under BSIMIMG standard technology, when incoming frequency is 400MHz, the present invention based on FinFET
The Performance comparision of classical six transistor memory units, two kinds of circuits in BSIMIMG technology library shown in read and write abruption memory element and Fig. 1
Figure.
Table 1
As can be drawn from Table 1：The read and write abruption memory element based on FinFET of the present invention with and Fig. 1 shown in
In BSIMIMG technology library, classical six transistor memory unit is compared, and time delay reduces 7.4%, and average total power consumption reduces 1.7%, work(
Consumption time delay product reduces 8.8%.
Table 2 is under BSIMIMG standard technology, when incoming frequency is 400MHz, the present invention based on FinFET
The Performance comparision of classical six transistor memory units, two kinds of circuits in BSIMIMG technology library shown in read and write abruption memory element and Fig. 1
Figure.
Table 2
As can be drawn from Table 2：The read and write abruption memory element based on FinFET of the present invention with and Fig. 1 shown in
In BSIMIMG technology library, classical six transistor memory unit is compared, and time delay reduces 7.4%, and average total power consumption reduces 2.4%, work(
Consumption time delay product reduces 9.5%.
Table 3 is the reading based on FinFET of the present invention under BSIMIMG standard technology, when incoming frequency is 1G Hz
Write the Performance comparision figure of classical six transistor memory units, two kinds of circuits in discrete memory location and the BSIMIMG technology library shown in Fig. 1.
Table 3
As can be drawn from Table 3：The read and write abruption memory element based on FinFET of the present invention with and Fig. 1 shown in
In BSIMIMG technology library, classical six transistor memory unit is compared, and time delay reduces 7.4%, and average total power consumption reduces 2.6%, work(
Consumption time delay product reduces 9.8%.
Table 4 is the reading based on FinFET of the present invention under BSIMIMG standard technology, when incoming frequency is 2G Hz
Write the Performance comparision figure of classical six transistor memory units, two kinds of circuits in discrete memory location and the BSIMIMG technology library shown in Fig. 1.
Table 4
As can be drawn from Table 4：The read and write abruption memory element based on FinFET of the present invention with and Fig. 1 shown in
In BSIMIMG technology library, classical six transistor memory unit is compared, and time delay reduces 7.4%, and average total power consumption reduces 3.3%, work(
Consumption time delay product reduces 10.5%.
From above-mentioned comparison data, on the premise of circuit performance is not affected, the present invention based on FinFET
Read and write abruption memory element compare with classical six transistor memory unit in the BSIMIMG technology library shown in Fig. 1, time delay obtains excellent
Change, the speed of service is improved；The power consumption of circuit and power-consumption design are also optimized.
Claims (3)
1. a kind of read and write abruption memory element based on FinFET, it is characterised in that including FinFET pipe, second
FinFET pipe, the 3rd FinFET pipe, the 4th FinFET pipe, the 5th FinFET pipe, the 6th FinFET pipe and the 7th FinFET pipe, institute
The FinFET pipe that states and the 2nd described FinFET pipe are p-type FinFET pipe, described 3rd FinFET pipe, described
4th FinFET pipe, described the 5th FinFET pipe, described the 6th FinFET pipe and the 7th described FinFET pipe are N-type
FinFET is managed, and the quantity of the fin of described FinFET pipe and the 2nd described FinFET pipe is 2, and the described 3rd
FinFET pipe, described the 4th FinFET pipe, described the 5th FinFET pipe, described the 6th FinFET pipe and the described the 7th
The quantity of the fin of FinFET pipe is 1；
The source electrode of the source electrode of a described FinFET pipe and the 2nd described FinFET pipe all accesses power supply, and described first
The drain electrode of FinFET pipe, the front gate of the 2nd described FinFET pipe, the backgate of the 2nd described FinFET pipe, the described the 3rd
The drain electrode connection of the drain electrode of FinFET pipe, the front gate of the 4th described FinFET pipe and the 5th described FinFET pipe and its connection
Hold the outfan for described read and write abruption memory element, the front gate of a described FinFET pipe, a described FinFET
The backgate of pipe, the drain electrode of the 2nd described FinFET pipe, the front gate of the 3rd described FinFET pipe, described the 4th FinFET pipe
The front gate connection of drain electrode, the drain electrode of the 6th described FinFET pipe and the 7th described FinFET pipe and its connection end for described
Read and write abruption memory element reversed-phase output；The source electrode of the 3rd described FinFET pipe, the 3rd described FinFET pipe
Backgate, the backgate of the 4th described FinFET pipe, the source electrode of the 4th described FinFET pipe and the 7th described FinFET pipe
Source grounding；The front gate, the backgate of the 5th described FinFET pipe of the 5th described FinFET pipe, the 6th described FinFET
The front gate of the backgate of pipe and the 6th described FinFET pipe connects and its connecting line is writing for described read and write abruption memory element
Wordline；The source electrode of the 5th described FinFET pipe is the write bit line of described read and write abruption memory element；Described the 6th
The source electrode of FinFET pipe is the write bit line Reverse Turning Control end of described read and write abruption memory element；The 7th described FinFET pipe
The sense bit line for draining as described read and write abruption memory element；The backgate of the 7th described FinFET pipe is described read and write abruption
The readout word line of memory element.
2. a kind of read and write abruption memory element based on FinFET according to claim 1, it is characterised in that described
FinFET pipe, described 2nd FinFET pipe, described the 3rd FinFET pipe, described the 4th FinFET pipe, described
The 5th FinFET pipe and the 6th described FinFET pipe be Low threshold FinFET pipe, described 7th FinFET pipe be
Value FinFET is managed.
3. a kind of read and write abruption memory element based on FinFET according to claim 1, it is characterised in that described
FinFET pipe, described 2nd FinFET pipe, described the 3rd FinFET pipe, described the 4th FinFET pipe, described
The 5th FinFET pipe and the equal threshold voltage of described 6th FinFET pipe be 0.1v, the threshold of described the 7th FinFET pipe
Threshold voltage is 0.6v.
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