CN108461104B - Single-ended read-write storage unit based on FinFET - Google Patents

Single-ended read-write storage unit based on FinFET Download PDF

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CN108461104B
CN108461104B CN201810104334.1A CN201810104334A CN108461104B CN 108461104 B CN108461104 B CN 108461104B CN 201810104334 A CN201810104334 A CN 201810104334A CN 108461104 B CN108461104 B CN 108461104B
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finfet
tube
finfet tube
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word line
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CN108461104A (en
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胡建平
杨会山
徐萧萧
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Ningbo University
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Ningbo University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Abstract

The invention discloses a single-ended read-write storage unit based on FinFETs, which comprises a first FinFET tube, a second FinFET tube, a third FinFET tube, a fourth FinFET tube, a fifth FinFET tube, a sixth FinFET tube, a seventh FinFET tube, a bit line, a word line, a write-up word line, a write-down word line and a virtual ground line, wherein the first FinFET tube and the second FinFET tube are both P-type FinFET tubes, and the third FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube are all N-type FinFET tubes; the advantage is on the basis of guaranteeing read operation stability, can obtain higher write noise margin, and the storage value result is stable, and the circuit function is stable, and leaks the consumption less, and the time delay is also less simultaneously, does benefit to the fast and stable access data.

Description

Single-ended read-write storage unit based on FinFET
Technical Field
The invention relates to a single-ended read-write memory cell, in particular to a FinFET-based single-ended read-write memory cell.
Background
As process dimensions enter the nanometer scale, power consumption becomes a concern for integrated circuit designers. The power consumption of the memory accounts for an increasing proportion of the total circuit power consumption in most digital systems. Static Random Access Memory (SRAM) is an important component in a Memory, and thus designing an SRAM with high stability and low power consumption has important research significance. The SRAM is mainly composed of a memory array and other peripheral circuits, wherein the memory array is composed of memory cells, the memory cells are the core of the SRAM, and the performance of the memory cells directly determines the performance of the SRAM. As transistor dimensions continue to shrink, the space for the common CMOS transistor size reduction is greatly reduced due to short channel effects and current manufacturing process limitations. When the size of a common CMOS transistor is reduced to below 20nm, the leakage current of the device is increased sharply, and larger circuit leakage power consumption is caused. Moreover, the short channel effect of the circuit becomes more obvious, the device becomes quite unstable, and the improvement of the circuit performance is greatly limited. A FinFET (Fin-Field-Effect Transistor) is a new complementary metal-oxide-semiconductor (CMOS) Transistor, which is a new type of 3D Transistor, and the channel of the FinFET is either zero-doped or low-doped, and is surrounded by three sides of the gate. The special three-dimensional structure enhances the control strength of the gate to the channel, greatly inhibits the short channel effect and inhibits the leakage current of the device. The FinFET has the advantages of low power consumption and small area, and gradually becomes one of excellent devices which take over the common CMOS devices and continue the Moore's law.
The conventional memory cell using FinFET design is the typical memory cell in the bsiimg process library. A circuit diagram of a typical memory cell in the bsiimg process library is shown in fig. 1. The memory cell is composed of six FinFET tubes (M1, M2, M3, M4, M5 and M6), wherein the FinFET tube M1 and the FinFET tube M3 form one inverter, and the FinFET tube M2 and the FinFET tube M4 form the other inverter. The pull-up network formed by the FinFET tube M1 and the FinFET tube M2 in the storage unit can improve the reverse threshold voltage of the inverter formed by the FinFET tube M1 and the FinFET tube M3 and the inverter formed by the FinFET tube M2 and the FinFET tube M4, data are not easily damaged in the read operation, the read stability is better, but in the write operation (writing '1' and '0'), the FinFET tube M4 and the FinFET tube M6 divide the write voltage, so that the written data value is smaller, the noise margin is smaller, the stored value written into the output end Q and the inverted output end Qb is unstable, and the circuit function is very unstable; and, two leakage current paths are formed when the memory cell is in a holding state in the pull-down network formed by the FinFET M3 and the FinFET M4, so the leakage current is large, the leakage power consumption is large, the time delay is large, and the data access is not favorable for rapid and stable.
Therefore, the FinFET-based single-ended read-write storage unit which is high in write noise tolerance, stable in stored value result, stable in circuit function, small in leakage power consumption and small in time delay on the basis of ensuring the stability of read operation is of great significance.
Disclosure of Invention
The invention aims to solve the technical problem of providing a single-ended read-write storage unit based on FinFET, which can obtain higher write noise margin, has stable storage value result, stable circuit function, smaller leakage power consumption and smaller time delay on the basis of ensuring the stability of read operation and is beneficial to quickly and stably accessing data.
The technical scheme adopted by the invention for solving the technical problems is as follows: a single-ended read-write memory cell based on FinFETs comprises a first FinFET tube, a second FinFET tube, a third FinFET tube, a fourth FinFET tube, a fifth FinFET tube, a sixth FinFET tube, a seventh FinFET tube, a bit line, a word line, a write word line, and a virtual ground line, wherein the first FinFET tube and the second FinFET tube are both P-type FinFET tubes, the third FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube, and the seventh FinFET tube are both N-type FinFET tubes, the first FinFET tube and the third FinFET tube are respectively high-threshold tubes, the second FinFET tube, the fourth FinFET tube, the fifth tube, the sixth FinFET tube, and the seventh FinFET tube are respectively low-threshold tubes, the number of fins of the first FinFET tube is 1, the number of the second FinFET tube is 1, the number of the third FinFET tube is 1, and the number of the fourth FinFET tubes is 1, the number of the fifth FinFET fins is 1, the number of the sixth FinFET fins is 1, and the number of the seventh FinFET fins is 1; the back gate of the first FinFET tube is connected with the write-up word line, the source of the first FinFET tube, the source of the second FinFET tube and the back gate of the second FinFET tube are all connected with a power supply, the drain of the first FinFET tube, the front gate of the second FinFET tube, the drain of the third FinFET tube, the front gate of the fourth FinFET tube, the drain of the sixth FinFET tube, the front gate of the seventh FinFET tube and the back gate of the seventh FinFET tube are connected and the connection end thereof is the output end of the single-ended read-write memory unit, the front gate of the first FinFET tube, the drain of the second FinFET tube, the front gate of the third FinFET tube and the drain of the fourth FinFET tube are connected and the connection end thereof is the inverted output end of the single-ended read-write memory unit, the back gate of the third FinFET tube is connected with the write-down word line, the source of the third FinFET tube, the front gate of the second FinFET tube, the front gate, The source of the fourth FinFET tube and the back gate of the fourth FinFET tube are connected to the ground, the drain of the fifth FinFET tube, the source of the sixth FinFET tube and the drain of the seventh FinFET tube are connected, the source of the fifth FinFET tube and the bit line are connected, the front gate of the fifth FinFET tube, the back gate of the fifth FinFET tube and the word line are connected, the front gate of the sixth FinFET tube, the back gate of the sixth FinFET tube and the write word line are connected, and the source of the seventh FinFET tube and the virtual ground line are connected.
The threshold voltages of the first FinFET tube and the third FinFET tube are both 0.6V, and the threshold voltages of the second FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube are all 0.3V.
Compared with the prior art, the invention has the advantages that a single-ended read-write storage unit is constructed by the first FinFET tube, the second FinFET tube, the third FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube, the seventh FinFET tube, the bit line, the word line, the write-up word line, the write-down word line and the virtual ground line, the single-ended read-write storage unit has a power control function, the first FinFET tube, the second FinFET tube, the third FinFET tube and the fourth FinFET tube form two phase inverters which are connected in a cross mode, the fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube form a read-write access buffer, wherein the first FinFET tube and the third FinFET tube are power control tubes, the single-ended bit line BL is connected with an output end (namely a storage point) Q through the read-write access buffer; the write word line WWL is only active for write operations; the upper write word line WLPU and the lower write word line WLPD are control signals and are in an off state only during a write operation, the virtual ground line VVSS is activated only during a read operation, the fifth FinFET is turned on when the word line WL is high, the VVSS is charged to the virtual ground signal VSS connected thereto, the sixth FinFET is turned off when the write word line WWL is high, the read operation starts, whether the precharged bit line BL is discharged or held is determined by the stored value of the output terminal Q, the seventh FinFET is turned on when the Q point stores "1", the BL is discharged to VSS through the fifth FinFET and the seventh FinFET, conversely, the seventh FinFET is turned off when the Q point stores "0", the BL is kept at the precharged high level, the read operation ends when the fluctuation of the bit line voltage is captured, the current during the read operation does not flow through the storage point Q because the storage point Q is separated from the bit line BL, which avoids read interference, during writing operation, WLPU is charged to VDD, WLPD is charged to VSS, the first FinFET and the third FinFET are cut off and the path from the power supply (VDD, VSS) to the storage point Q is blocked, meanwhile WL and WWL are charged to high level, the storage point Q is driven by the voltage of WL only, so the write interference caused by the power supply is eliminated, thereby the writing capability is greatly improved, because the fifth FinFET and the sixth FinFET are both NMOS, the phenomenon of threshold voltage drop can occur, the writing operation of '1' can be more difficult than the writing operation of '0', the voltage on WL and WWL can be increased during the writing operation, thereby the writing operation delay is reduced, the single-end read-write storage unit of the invention can obtain high-reliability read-write operation by using the read-write access buffer and the power control tube, simultaneously, the bit line crossing is used to avoid soft errors, the redundant charges on the bit lines when the virtual ground signal Vss of the virtual ground line is not selected are released, therefore, on the basis of ensuring the stability of the reading operation, higher write noise tolerance can be obtained, the stored value result is stable, the circuit function is stable, the leakage power consumption is smaller, the time delay is smaller, and the data can be accessed quickly and stably.
Drawings
FIG. 1 is a circuit diagram of a typical memory cell in a prior art BSIMIMG process library;
FIG. 2 is a circuit diagram of a FinFET-based single-ended read-write memory cell of the present invention;
fig. 3 is a simulation waveform diagram of the FinFET-based single-ended read-write memory cell under the bsiimg standard process under the conditions of the standard voltage (1v) and the frequency 1G.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The first embodiment is as follows: as shown in fig. 2, a FinFET-based single-ended read-write memory cell includes a first FinFET tube B1, a second FinFET tube B2, a third FinFET tube B3, a fourth FinFET tube B4, a fifth FinFET tube B5, a sixth FinFET tube B6, a seventh FinFET tube B7, a bit line BL, a word line WL, a write word line WWL, a write word line WLPU, a write down word line WLPD, and a virtual ground line VVSS, where the first FinFET tube B1 and the second FinFET tube B2 are both P-type FinFET tubes, the third FinFET tube B3, the fourth FinFET tube B4, the fifth FinFET tube B5, the sixth FinFET tube B6, and the seventh FinFET tube B7 are all N-type FinFET tubes, the first FinFET tube B1 and the third FinFET tube B3 are each high-threshold-value FinFET tubes, the second FinFET tube B2, the fourth FinFET tube B4, the fifth FinFET tube B5, the sixth FinFET tube B6, and the seventh FinFET tube B1 are each a number of high-threshold tubes, the number of the fourth FinFET tube B1 is equal to the number of the fourth FinFET tube B1, the number of the fifth FinFET tube B1, the fifth FinFET tube B1 is equal to the number of the fourth FinFET tube 1, the number of fins of the sixth FinFET B6 is 1, and the number of fins of the seventh FinFET B7 is 1; the back gate of the first FinFET B1 is connected to the upper write word line WLPU, the source of the first FinFET B1, the source of the second FinFET B2, and the back gate of the second FinFET B2 are all connected to the power supply VDD, the drain of the first FinFET B1, the front gate of the second FinFET B2, the drain of the third FinFET B3, the front gate of the fourth FinFET B4, the drain of the sixth FinFET B6, the front gate of the seventh FinFET B7, and the back gate of the seventh FinFET B7 are connected to the output Q of the single-ended read-write memory cell, the front gate of the first FinFET B1, the drain of the second FinFET B2, the front gate of the third FinFET B3, and the drain of the fourth FinFET B4 are connected to the inverted output Qb of the read-write memory cell, the write gate of the third FinFET B3 is connected to the lower write word line pd, the source of the third FinFET B3, the source of the third FinFET B58b 3, the source of the fourth FinFET B4, and the drain of the fifth FinFET B4624 are connected to the ground GND terminal of the fifth FinFET B4624, the source of the fifth FinFET B5 is connected to the bit line BL, the front gate of the fifth FinFET B5, the back gate of the fifth FinFET B5 are connected to the word line WL, the front gate of the sixth FinFET B6, the back gate of the sixth FinFET B6 are connected to the write word line WWL, and the source of the seventh FinFET B7 is connected to the virtual ground line VVSS.
Example two: as shown in fig. 2, a FinFET-based single-ended read-write memory cell includes a first FinFET tube B1, a second FinFET tube B2, a third FinFET tube B3, a fourth FinFET tube B4, a fifth FinFET tube B5, a sixth FinFET tube B6, a seventh FinFET tube B7, a bit line BL, a word line WL, a write word line WWL, a write word line WLPU, a write down word line WLPD, and a virtual ground line VVSS, where the first FinFET tube B1 and the second FinFET tube B2 are both P-type FinFET tubes, the third FinFET tube B3, the fourth FinFET tube B4, the fifth FinFET tube B5, the sixth FinFET tube B6, and the seventh FinFET tube B7 are all N-type FinFET tubes, the first FinFET tube B1 and the third FinFET tube B3 are each high-threshold-value FinFET tubes, the second FinFET tube B2, the fourth FinFET tube B4, the fifth FinFET tube B5, the sixth FinFET tube B6, and the seventh FinFET tube B1 are each a number of high-threshold tubes, the number of the fourth FinFET tube B1 is equal to the number of the fourth FinFET tube B1, the number of the fifth FinFET tube B1, the fifth FinFET tube B1 is equal to the number of the fourth FinFET tube 1, the number of fins of the sixth FinFET B6 is 1, and the number of fins of the seventh FinFET B7 is 1; the back gate of the first FinFET B1 is connected to the upper write word line WLPU, the source of the first FinFET B1, the source of the second FinFET B2, and the back gate of the second FinFET B2 are all connected to the power supply VDD, the drain of the first FinFET B1, the front gate of the second FinFET B2, the drain of the third FinFET B3, the front gate of the fourth FinFET B4, the drain of the sixth FinFET B6, the front gate of the seventh FinFET B7, and the back gate of the seventh FinFET B7 are connected to the output Q of the single-ended read-write memory cell, the front gate of the first FinFET B1, the drain of the second FinFET B2, the front gate of the third FinFET B3, and the drain of the fourth FinFET B4 are connected to the inverted output Qb of the read-write memory cell, the write gate of the third FinFET B3 is connected to the lower write word line pd, the source of the third FinFET B3, the source of the third FinFET B58b 3, the source of the fourth FinFET B4, and the drain of the fifth FinFET B4624 are connected to the ground GND terminal of the fifth FinFET B4624, the source of the fifth FinFET B5 is connected to the bit line BL, the front gate of the fifth FinFET B5, the back gate of the fifth FinFET B5 are connected to the word line WL, the front gate of the sixth FinFET B6, the back gate of the sixth FinFET B6 are connected to the write word line WWL, and the source of the seventh FinFET B7 is connected to the virtual ground line VVSS.
In this embodiment, the threshold voltages of the first FinFET tube B1 and the third FinFET tube B3 are both 0.6V, and the threshold voltages of the second FinFET tube B2, the fourth FinFET tube B4, the fifth FinFET tube B5, the sixth FinFET tube B6, and the seventh FinFET tube B7 are all 0.3V.
In order to verify the superiority of the single-ended read-write memory cell based on the FinFET, a circuit simulation tool HSPICE is respectively used for carrying out simulation comparison on the performances of the single-ended read-write memory cell based on the FinFET and the performances of the two circuits of an classical memory cell in a BSIMG process library shown in figure 1 under the conditions that the input frequency of the circuit is 1GHz and the power supply voltage is 1V and 0.7V under the BSIMG standard process, wherein the standard power supply voltage corresponding to the BSIMG process library is 1V, and the tolerance noise of the read operation and the write operation of the two circuits is compared at the same time. Under the standard voltage (1v), the simulation waveform diagram of the FinFET-based single-ended read-write memory cell under the bsiimg standard process is shown in fig. 3. As can be seen from fig. 3, the FinFET-based single-ended read-write memory cell of the present invention has correct operation logic.
Table 1 shows performance comparison data of the single-ended read-write memory cell based on the FinFET and the typical memory cell in the bsiimg process library shown in fig. 1, when the power supply voltage is 1V and the input frequency is 1GHz in the bsiimg standard process.
TABLE 1
Type of circuit Number of transistors Time delay (ps) Total power consumption (μ W) Power consumption time delay product (fJ)
The invention 7 10.46 43.70 0.457
Classic memory cell 6 18.25 57.24 1.045
From table 1, it can be derived: compared with the typical memory cell in the BSIMIMIMG process library shown in FIG. 1, the single-ended read-write memory cell based on the FinFET has the advantages that the delay is reduced by 42.68%, the average total power consumption is reduced by 23.65%, and the power consumption delay product is reduced by 56.27%.
Table 2 shows performance comparison data of the single-ended read-write memory cell based on the FinFET of the present invention and the typical memory cell in the bsiimg process library shown in fig. 1, when the power supply voltage is 0.7V and the input frequency is 1GHz in the bsiimg standard process.
TABLE 2
Type of circuit Number of transistors Time delay (ps) Total power consumption (μ W) Power consumption time delay product (fJ)
The invention 7 21.50 27.35 0.588
Classic memory cell 6 30.56 39.13 1.196
From table 2, it can be derived: compared with the typical memory cell in the BSIMIMIMG process library shown in figure 1, the single-ended read-write memory cell based on the FinFET has the advantages that the delay is reduced by 29.65%, the average total power consumption is reduced by 30.10%, and the power consumption delay product is reduced by 50.84%.
Table 3 shows the comparison data of the read/write noise margins of the single-ended read/write memory cell based on FinFET and the typical memory cell in the BSIMIMG library of FIG. 1, when the power supply voltage is 0.7V and the input frequency is 1GHz in the BSIMIMG standard process
TABLE 3
Figure GDA0002295172000000071
From table 3, it can be derived: compared with the typical memory cell in the BSIMIMG process library shown in FIG. 1, the FinFET-based single-ended read-write memory cell of the invention has 313.04% of read noise tolerance and 60.45% of write noise tolerance.
As can be seen from the above comparison data, compared with the typical storage unit in the bsiimg process library shown in fig. 1, the FinFET-based single-ended read-write storage unit of the present invention has a large noise margin during write operation, stable stored value results written to the output terminal Q and the inverted output terminal Qb, stable circuit function, optimized power consumption and power consumption delay product, and improved operation speed, while ensuring the stability of read operation.

Claims (1)

1. A single-ended read-write memory cell based on FinFETs comprises a first FinFET tube, a second FinFET tube, a third FinFET tube, a fourth FinFET tube, a fifth FinFET tube, a sixth FinFET tube, a seventh FinFET tube, a bit line, a word line, a write word line and a virtual ground line, wherein the first FinFET tube and the second FinFET tube are P-type FinFET tubes, the third FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube are N-type FinFET tubes, the first FinFET tube and the third FinFET tube are high-threshold tubes, the second FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube are low-threshold tubes, the number of fins of the first FinFET tube is 1, the number of the second FinFET tube is 1, and the number of the third FinFET tube is 1, the number of the fourth FinFET fins is 1, the number of the fifth FinFET fins is 1, the number of the sixth FinFET fins is 1, and the number of the seventh FinFET fins is 1;
the back gate of the first FinFET tube is connected with the write-up word line, the source of the first FinFET tube, the source of the second FinFET tube and the back gate of the second FinFET tube are all connected with a power supply, the drain of the first FinFET tube, the front gate of the second FinFET tube, the drain of the third FinFET tube, the front gate of the fourth FinFET tube, the drain of the sixth FinFET tube, the front gate of the seventh FinFET tube and the back gate of the seventh FinFET tube are connected and the connection end thereof is the output end of the single-ended read-write memory unit, the front gate of the first FinFET tube, the drain of the second FinFET tube, the front gate of the third FinFET tube and the drain of the fourth FinFET tube are connected and the connection end thereof is the inverted output end of the single-ended read-write memory unit, the back gate of the third FinFET tube is connected with the write-down word line, the source of the third FinFET tube, the front gate of the second FinFET tube, the front gate, The source of the fourth FinFET tube and the back gate of the fourth FinFET tube are connected to the ground, the drain of the fifth FinFET tube, the source of the sixth FinFET tube and the drain of the seventh FinFET tube are connected, the source of the fifth FinFET tube and the bit line are connected, the front gate of the fifth FinFET tube, the back gate of the fifth FinFET tube and the word line are connected, the front gate of the sixth FinFET tube, the back gate of the sixth FinFET tube and the write word line are connected, and the source of the seventh FinFET tube and the virtual ground line are connected; the threshold voltages of the first FinFET tube and the third FinFET tube are both 0.6V, and the threshold voltages of the second FinFET tube, the fourth FinFET tube, the fifth FinFET tube, the sixth FinFET tube and the seventh FinFET tube are all 0.3V.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100253408B1 (en) * 1998-02-04 2000-05-01 김영환 Sram cell for low power consumption
CN103886887A (en) * 2014-03-31 2014-06-25 西安华芯半导体有限公司 Dual-port static random access memory with single-port memory cells
US9490008B1 (en) * 2014-08-12 2016-11-08 Skan Technologies Corporation 9T, 8T, and 7T Bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write
CN106448725A (en) * 2016-09-21 2017-02-22 宁波大学 Read/write splitting memory cell based on FinFET (fin field-effect transistor) devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100253408B1 (en) * 1998-02-04 2000-05-01 김영환 Sram cell for low power consumption
CN103886887A (en) * 2014-03-31 2014-06-25 西安华芯半导体有限公司 Dual-port static random access memory with single-port memory cells
US9490008B1 (en) * 2014-08-12 2016-11-08 Skan Technologies Corporation 9T, 8T, and 7T Bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write
CN106448725A (en) * 2016-09-21 2017-02-22 宁波大学 Read/write splitting memory cell based on FinFET (fin field-effect transistor) devices

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