CN108461104A - A kind of single-ended read-write memory cell based on FinFET - Google Patents
A kind of single-ended read-write memory cell based on FinFET Download PDFInfo
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- CN108461104A CN108461104A CN201810104334.1A CN201810104334A CN108461104A CN 108461104 A CN108461104 A CN 108461104A CN 201810104334 A CN201810104334 A CN 201810104334A CN 108461104 A CN108461104 A CN 108461104A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
The invention discloses a kind of single-ended read-write memory cell based on FinFET, including the first FinFET pipes, the 2nd FinFET pipes, the 3rd FinFET pipes, the 4th FinFET pipes, the 5th FinFET pipes, the 6th FinFET pipes, the 7th FinFET pipes, bit line, wordline, write word line writes wordline, writes wordline and virtual earth line, first FinFET is managed and the 2nd FinFET pipes are p-type FinFET pipes, and the 3rd FinFET pipes, the 4th FinFET pipes, the 5th FinFET pipes, the 6th FinFET pipes and the 7th FinFET pipes are N-type FinFET pipes；Advantage be on the basis of ensureing read operation stability, can obtain it is higher write noise margin, storage value result is stablized, and circuit function is stablized, and it is smaller to leak power consumption, while it is also smaller to be delayed, and is conducive to fast and stable and accesses data.
Description
Technical field
The present invention relates to a kind of single-ended read-write memory cells, are stored more particularly, to a kind of single-ended read-write based on FinFET
Unit.
Background technology
As process enters nanoscale, power consumption becomes the problem of IC designer must not be not concerned with.In big portion
Point digital display circuit in memory power consumption occupy way circuit power consumption ratio it is increasing.Static RAM
(SRAM, Static Random Access Memory), is an important component part in memory, thus is designed high
Stability low-power consumption SRAM has important research significance.Static RAM is mainly by storage array and other peripheries
Circuit is constituted, and storage array is made of storage unit, and storage unit is the core of static RAM, storage unit
Performance directly determine the performance of static RAM.With the continuous diminution of transistor size, by short-channel effect
It is extremely reduced with the space of the limitation of present production process, common CMOS transistor size reduction.When common CMOS transistor
Size reduction to 20nm or less when, the leakage current of device can be increased drastically, and larger circuit is caused to leak power consumption.Also, circuit
Short-channel effect becomes readily apparent from, and device becomes rather unstable, significantly limits the raising of circuit performance.FinFET is managed
(fin field-effect transistor, Fin Field-Effect Transistor) is a kind of new Complementary MOS (CMOS)
Transistor is a kind of novel 3D transistors, and the raceway grooves of FinFET pipes is using zero doping or low-doped, and raceway groove is by three bread of grid
It encloses.This special three-dimensional structure, enhances control dynamics of the grid to raceway groove, greatly inhibits short-channel effect, suppression
The leakage current of device is made.FinFET pipe have it is low in energy consumption, the small advantage of area is increasingly becoming and takes over conventional CMOS devices, prolongs
One of the improved device of continuous Moore's Law.
It is traditional use the storage unit of FinFET design for BSIMIMG technology libraries in classical storage unit.BSIMIMG works
The circuit diagram of classical storage unit is as shown in Figure 1 in skill library.The storage unit managed by six FinFET (M1, M2, M3, M4, M5 and
M6 it) forms, wherein FinFET pipes M1 and FinFET pipe M3 constitutes a phase inverter, and FinFET pipe M2 and FinFET pipes M4 constitutes another
One phase inverter.The upper pull-up network being made of FinFET pipe M1 and FinFET pipes M2 in the storage unit can make FinFET pipes M1
With the reversed threshold voltage of the FinFET pipes M3 phase inverters constituted and FinFET pipe M2 and FinFET pipes the M4 phase inverter constituted
It improves, in read operation, data are not easy to be destroyed, and read stability is more preferable, but in write operation (write-in " 1 " and " 0 "),
FinFET pipe M4 and FinFET pipes M6 can divide write-in voltage so that the data value of write-in is smaller, thus leads to noise
Tolerance is smaller, so that being written to the storage value unstable result at output end Q and reversed-phase output Qb, circuit function is very unstable
It is fixed；Also, the pulldown network being made of FinFET pipe M3 and FINFET pipes M4 has two when storage unit is in hold mode
The path of leakage current, so leakage current is larger, it is larger so as to cause leakage power consumption, while it is also larger to be delayed, this is unfavorable for quickly
Stablize access data.
In view of this, design one kind writing noise margin height on the basis of ensureing read operation stability, and storage value result is stablized,
Circuit function is stablized, and leakage power consumption is smaller, while it is also smaller to be delayed, and is conducive to the list based on FinFET of fast and stable access data
End read-write memory cell is of great significance.
Invention content
Technical problem to be solved by the invention is to provide one kind on the basis of ensureing read operation stability, can obtain
Higher to write noise margin, storage value result is stablized, and circuit function is stablized, and leakage power consumption is smaller, while it is also smaller to be delayed, and is conducive to
Fast and stable accesses the single-ended read-write memory cell based on FinFET of data.
Technical solution is used by the present invention solves above-mentioned technical problem：A kind of single-ended read-write storage based on FinFET
Unit, including the first FinFET pipes, the 2nd FinFET pipes, the 3rd FinFET pipes, the 4th FinFET pipes, the 5th FinFET pipes, the
Six FinFET pipes, the 7th FinFET pipes, bit line, wordline, write word line write wordline, write wordline and virtual earth line, and described first
FinFET is managed and the 2nd FinFET pipes are p-type FinFET pipes, the 3rd FinFET is managed, the 4th FinFET is managed,
5th FinFET pipes, the 6th FinFET pipes and the 7th FinFET pipes is N-type FinFET pipes, described
The first FinFET pipes and described 3rd FinFET pipes be respectively high threshold FinFET pipes, the 2nd FinFET pipes, institute
The 4th FinFET pipes, the 5th FinFET pipes, the 6th FinFET pipes and the 7th FinFET pipes point stated
Not Wei Low threshold FinFET pipe, the quantity of the first FinFET pipe fins is 1, and the quantity of the 2nd FinFET pipe fins is
1, the quantity of the 3rd FinFET pipe fins is 1, and the quantity of the 4th FinFET pipe fins is the 1, the described the 5th
The quantity of FinFET pipe fins is 1, and the quantity of the 6th FinFET pipe fins is 1, the quantity of the 7th FinFET pipe fins
It is 1；The backgate of the first FinFET pipes is connected with the upper write word line, the source electrode of the first FinFET pipes, institute
The source electrode for the 2nd FinFET pipes stated and the backgate of the 2nd FinFET pipes access power supply, the first FinFET pipes
Drain, the draining of the front gate of the 2nd FinFET pipes, the 3rd FinFET pipes, the 4th FinFET pipes
Front gate, the draining of the 6th FinFET pipes, the front gate of the 7th FinFET pipes and the 7th FinFET pipes
Back-gate connection and the output end that its connecting pin is the single-ended read-write memory cell, the front gate of the first FinFET pipes,
The drain electrode of the draining of the 2nd FinFET pipes, the front gate of the 3rd FinFET pipes and the 4th FinFET pipes connects
It connects and reversed-phase output that its connecting pin is the single-ended read-write memory cell, the backgate of the 3rd FinFET pipes and institute
That states writes wordline connection, the source electrode of the 3rd FinFET pipes, the source electrode of the 4th FinFET pipes and described the
The backgate of four FinFET pipes accesses the earth, the draining of the 5th FinFET pipes, the source electrode of the 6th FinFET pipes
It is connected with the drain electrode of the 7th FinFET pipes, the source electrode of the 5th FinFET pipes is connected with the bit line, described
The front gate of the 5th FinFET pipes, the backgate of the 5th FinFET pipes connected with the wordline, the described the 6th
The front gate of FinFET pipes, the backgate of the 6th FinFET pipes are connected with the write word line, the 7th FinFET pipes
Source electrode connected with the virtual earth line.
The threshold voltage of the first FinFET pipes and the 3rd FinFET pipes is 0.6V, and described second
FinFET pipes, the 4th FinFET pipes, the 5th FinFET pipes, the 6th FinFET pipes and the described the 7th
The threshold voltage of FinFET pipes is 0.3V.
Compared with the prior art, the advantages of the present invention are as follows pass through the first FinFET pipes, the 2nd FinFET pipes, third
FinFET pipes, the 4th FinFET pipes, the 5th FinFET pipes, the 6th FinFET pipes, the 7th FinFET pipes, bit line, wordline, write
Line writes wordline, writes wordline and the single-ended read-write memory cell of virtual earth line structure, and the single-ended read-write memory cell is with power control work(
Can, the first FinFET pipes, the 2nd FinFET pipes, the 3rd FinFET pipes constitute two with the 4th FinFET pipes and intersect the reverse phase being connected
Device, the 5th FinFET pipes, the 6th FinFET pipes and the 7th FinFET pipes constitute a read/write access buffer, wherein first
FinFET is managed and the 3rd FinFET pipes are power control pipe, and single end bit line BL passes through read/write access buffer and output end (storing a little)
Q is connected, during wordline WL read-writes effectively；Write word line WWL is only effective in write operation；It writes wordline WLPU and writes wordline
WLPD signals in order to control, are only off state during write operation, and virtual earth line VVSS is only activated during read operation, is reading
When operation, when wordline WL is high level, the 5th FinFET of conducting pipes, VVSS are charged to the virtual earth signal VSS of its access, write
Wordline WWL is that high level turns off the 6th FinFET pipes, and read operation starts, by the position of precharge from the point of view of the storage value of output end Q
Whether the ends line BL can discharge or keep, and when Q points store " 1 ", the 7th FinFET pipe pipes are connected, then BL can pass through the 5th
FinFET is managed discharges into VSS with the 7th FinFET pipes, and opposite the 7th FinFET pipes when Q points store " 0 " end, then BL
The high level that can keep precharge, when capturing the fluctuation of bit-line voltage read operation terminate, due to storage point Q and bit line BL minutes
From, so electric current when read operation does not flow through storage point Q, this avoids interference is read, in write operation, WLPU is charged to VDD,
WLPD is charged to VSS, and the first FinFET pipes and the cut-off of the 3rd FinFET pipes are from power supply (VDD, VSS) to the path quilt of storage point Q
It blocks, at the same time WL and WWL is charged to high level, and storage point Q is only driven by the voltage of WL, so being made by power supply
At interference of writing be eliminated, greatly improve to write capability, since the 5th FinFET pipes and the 6th FinFET pipes are NMOS, meeting
There is the phenomenon that threshold voltage decreasing, write-in " 1 " operation can be caused more difficult than write-in " 0 ", can be promoted during write operation
Voltage on WL and WWL, to reduce write operation delay, single-ended read-write memory cell of the invention uses read/write access buffer
The read-write operation that high reliability can be obtained with power control pipe is both to go to avoid soft error using bit line intersection, utilizes virtual earth line
Excess charge when the Vss releases of virtual earth signal are not selected on bit line is ensureing read operation stabilization as a result, to reduce energy consumption
Property on the basis of, can obtain it is higher write noise margin, storage value result is stablized, and circuit function is stablized, and it is smaller to leak power consumption,
Delay is also smaller simultaneously, is conducive to fast and stable and accesses data.
Description of the drawings
Fig. 1 is the circuit diagram of classical storage unit in existing BSIMIMG technology libraries；
Fig. 2 is the circuit diagram of the single-ended read-write memory cell based on FinFET of the present invention；
Fig. 3 is normal voltage (1v), and under the conditions of frequency 1G, the single-ended read-write memory cell of the invention based on FinFET exists
Simulation waveform under BSIMIMG standard technologies.
Specific implementation mode
Below in conjunction with attached drawing embodiment, present invention is further described in detail.
Embodiment one：As shown in Fig. 2, a kind of single-ended read-write memory cell based on FinFET, including the first FinFET pipes
B1, the 2nd FinFET pipes B2, the 3rd FinFET pipes B3, the 4th FinFET pipes B4, the 5th FinFET pipes B5, the 6th FinFET pipes
B6, the 7th FinFET pipes B7, bit line BL, wordline WL, write word line WWL, write wordline WLPU, write wordline WLPD and virtual earth line
VVSS, the first FinFET pipes B1 and the 2nd FinFET pipes B2 are p-type FinFET pipes, the 3rd FinFET pipes B3, the 4th FinFET
Pipe B4, the 5th FinFET pipes B5, the 6th FinFET pipes B6 and the 7th FinFET pipes B7 are N-type FinFET pipes, the first FinFET
Pipe B1 and the 3rd FinFET pipes B3 is respectively high threshold FinFET pipes, the 2nd FinFET pipes B2, the 4th FinFET pipes B4, the 5th
FinFET pipes B5, the 6th FinFET pipes B6 and the 7th FinFET pipes B7 are respectively Low threshold FinFET pipes, the first FinFET pipes B1
The quantity of fin is 1, and the quantity of the 2nd FinFET pipe B2 fins is 1, and the quantity of the 3rd FinFET pipe B3 fins is 1, the 4th FinFET pipes
The quantity of B4 fins is 1, and the quantity of the 5th FinFET pipe B5 fins is 1, and the quantity of the 6th FinFET pipe B6 fins is 1, the 7th FinFET
The quantity of pipe B7 fins is 1；The backgate of first FinFET pipes B1 is connected with upper write word line WLPU, the source electrode of the first FinFET pipes B1,
The source electrode of 2nd FinFET pipes B2 and the backgate of the 2nd FinFET pipes B2 access power vd D, the drain electrode of the first FinFET pipes B1,
The front gate of 2nd FinFET pipes B2, the drain electrode of the 3rd FinFET pipes B3, the front gate of the 4th FinFET pipes B4, the 6th FinFET pipes B6
Drain electrode, the front gate of the 7th FinFET pipes B7 and the back-gate connection of the 7th FinFET pipes B7 and its connecting pin be single-ended read-write storage
The output end Q of unit, the front gate of the first FinFET pipes B1, the drain electrode of the 2nd FinFET pipes B2, the 3rd FinFET pipes B3 front gate
Drain electrode connection and its connecting pin with the 4th FinFET pipes B4 are the reversed-phase output Qb of single-ended read-write memory cell, third
The backgate of FinFET pipes B3 is connected with wordline WLPD is write, the source electrode of the 3rd FinFET pipes B3, the source electrode of the 4th FinFET pipes B4
The earth GND, the drain electrode of the 5th FinFET pipes B5, the source electrode of the 6th FinFET pipes B6 are accessed with the backgate of the 4th FinFET pipes B4
It is connected with the drain electrode of the 7th FinFET pipes B7, the source electrode of the 5th FinFET pipes B5 is connected with bit line BL, the 5th FinFET pipes B5's
Front gate, the backgate of the 5th FinFET pipes B5 are connected with wordline WL, the front gate of the 6th FinFET pipes B6, the back of the body of the 6th FinFET pipes B6
Grid are connected with write word line WWL, and the source electrode of the 7th FinFET pipes B7 is connected with virtual earth line VVSS.
Embodiment two：As shown in Fig. 2, a kind of single-ended read-write memory cell based on FinFET, including the first FinFET pipes
B1, the 2nd FinFET pipes B2, the 3rd FinFET pipes B3, the 4th FinFET pipes B4, the 5th FinFET pipes B5, the 6th FinFET pipes
B6, the 7th FinFET pipes B7, bit line BL, wordline WL, write word line WWL, write wordline WLPU, write wordline WLPD and virtual earth line
VVSS, the first FinFET pipes B1 and the 2nd FinFET pipes B2 are p-type FinFET pipes, the 3rd FinFET pipes B3, the 4th FinFET
Pipe B4, the 5th FinFET pipes B5, the 6th FinFET pipes B6 and the 7th FinFET pipes B7 are N-type FinFET pipes, the first FinFET
Pipe B1 and the 3rd FinFET pipes B3 is respectively high threshold FinFET pipes, the 2nd FinFET pipes B2, the 4th FinFET pipes B4, the 5th
FinFET pipes B5, the 6th FinFET pipes B6 and the 7th FinFET pipes B7 are respectively Low threshold FinFET pipes, the first FinFET pipes B1
The quantity of fin is 1, and the quantity of the 2nd FinFET pipe B2 fins is 1, and the quantity of the 3rd FinFET pipe B3 fins is 1, the 4th FinFET pipes
The quantity of B4 fins is 1, and the quantity of the 5th FinFET pipe B5 fins is 1, and the quantity of the 6th FinFET pipe B6 fins is 1, the 7th FinFET
The quantity of pipe B7 fins is 1；The backgate of first FinFET pipes B1 is connected with upper write word line WLPU, the source electrode of the first FinFET pipes B1,
The source electrode of 2nd FinFET pipes B2 and the backgate of the 2nd FinFET pipes B2 access power vd D, the drain electrode of the first FinFET pipes B1,
The front gate of 2nd FinFET pipes B2, the drain electrode of the 3rd FinFET pipes B3, the front gate of the 4th FinFET pipes B4, the 6th FinFET pipes B6
Drain electrode, the front gate of the 7th FinFET pipes B7 and the back-gate connection of the 7th FinFET pipes B7 and its connecting pin be single-ended read-write storage
The output end Q of unit, the front gate of the first FinFET pipes B1, the drain electrode of the 2nd FinFET pipes B2, the 3rd FinFET pipes B3 front gate
Drain electrode connection and its connecting pin with the 4th FinFET pipes B4 are the reversed-phase output Qb of single-ended read-write memory cell, third
The backgate of FinFET pipes B3 is connected with wordline WLPD is write, the source electrode of the 3rd FinFET pipes B3, the source electrode of the 4th FinFET pipes B4
The earth GND, the drain electrode of the 5th FinFET pipes B5, the source electrode of the 6th FinFET pipes B6 are accessed with the backgate of the 4th FinFET pipes B4
It is connected with the drain electrode of the 7th FinFET pipes B7, the source electrode of the 5th FinFET pipes B5 is connected with bit line BL, the 5th FinFET pipes B5's
Front gate, the backgate of the 5th FinFET pipes B5 are connected with wordline WL, the front gate of the 6th FinFET pipes B6, the back of the body of the 6th FinFET pipes B6
Grid are connected with write word line WWL, and the source electrode of the 7th FinFET pipes B7 is connected with virtual earth line VVSS.
In the present embodiment, the threshold voltage of the first FinFET pipes B1 and the 3rd FinFET pipes B3 are 0.6V, and second
The threshold value of FinFET pipes B2, the 4th FinFET pipes B4, the 5th FinFET pipes B5, the 6th FinFET pipes B6 and the 7th FinFET pipes B7
Voltage is 0.3V.
In order to verify the excellent benefit of the single-ended read-write memory cell based on FinFET of the invention, in BSIMIMG standard works
Under skill, under conditions of the input frequency of circuit is 1GHz, circuit simulation tools are used under the conditions of supply voltage 1V and 0.7V respectively
HSPICE deposits classics in the single-ended read-write memory cell based on FinFET of the present invention and BSIMIMG technology libraries shown in FIG. 1
The performance of both circuits of storage unit carries out simulation comparison, wherein and the corresponding standard mains voltage of BSIMIMG technology libraries is 1V,
Two kinds of circuit read operations and write operation noise margin are compared simultaneously.Under normal voltage (1v), the list of the invention based on FinFET
Hold read-write memory cell simulation waveform under BSIMIMG standard technologies as shown in Figure 3.Analysis chart 3 it is found that the present invention based on
The single-ended read-write memory cell of FinFET has correct work-based logic.
Table 1 be under BSIMIMG standard technologies, supply voltage 1V, input frequency be 1GHz when, it is of the invention based on
The performance of two kinds of circuits of classical storage unit in the single-ended read-write memory cell of FinFET and BSIMIMG technology libraries shown in FIG. 1
Compare data.
Table 1
| Circuit types | Transistor size | It is delayed (ps) | Total power consumption (μ W) | Power-consumption design (fJ) |
| The present invention | 7 | 10.46 | 43.70 | 0.457 |
| Classical storage unit | 6 | 18.25 | 57.24 | 1.045 |
As can be drawn from Table 1：The single-ended read-write memory cell based on FinFET of the present invention with and it is shown in FIG. 1
Classical storage unit is compared in BSIMIMG technology libraries, and delay reduces 42.68%, and average total power consumption reduces 23.65%, work(
Consumption delay product reduces 56.27%.
Table 2 be under BSIMIMG standard technologies, supply voltage 0.7V, input frequency be 1GHz when, it is of the invention based on
The performance of two kinds of circuits of classical storage unit in the single-ended read-write memory cell of FinFET and BSIMIMG technology libraries shown in FIG. 1
Compare data.
Table 2
As can be drawn from Table 2：The single-ended read-write memory cell based on FinFET of the present invention with and it is shown in FIG. 1
Classical storage unit is compared in BSIMIMG technology libraries, and delay reduces 29.65%, and average total power consumption reduces 30.10%, work(
Consumption delay product reduces 50.84%.
Table 3 be under BSIMIMG standard technologies, supply voltage 0.7V, input frequency be 1GHz when, it is of the invention based on
The reading behaviour of two kinds of circuits of classical storage unit in the single-ended read-write memory cell of FinFET and BSIMIMG technology libraries shown in FIG. 1
Work/write operation noise margin compares data
Table 3
As can be drawn from Table 3：The single-ended read-write memory cell based on FinFET of the present invention with and it is shown in FIG. 1
Classical storage unit is compared in BSIMIMG technology libraries, and read noise tolerance increases 313.04%, writes noise margin and increases
60.45%.
By above-mentioned comparison data as it can be seen that the single-ended read-write memory cell based on FinFET of the present invention and shown in FIG. 1
Classical storage unit compares in BSIMIMG technology libraries, on the basis of ensureing read operation stability, noise margin when write operation
It is larger, it is written to the storage value result at output end Q and reversed-phase output Qb and stablizes, circuit function is stablized, and the work(of circuit
Consumption and power-consumption design are also optimized, and the speed of service is improved.
Claims (2)
1. a kind of single-ended read-write memory cell based on FinFET, it is characterised in that including the first FinFET pipes, the 2nd FinFET
Pipe, the 3rd FinFET pipes, the 4th FinFET pipes, the 5th FinFET pipes, the 6th FinFET pipes, the 7th FinFET pipes, bit line, word
Line, write word line write wordline, write wordline and virtual earth line, and the first FinFET pipes and the 2nd FinFET pipes are p-type
FinFET is managed, the 3rd FinFET pipes, the 4th FinFET pipes, the 5th FinFET pipes, the described the 6th
FinFET is managed and the 7th FinFET pipes are N-type FinFET pipes, the first FinFET pipes and the third
FinFET pipes are respectively high threshold FinFET pipes, the 2nd FinFET pipes, the 4th FinFET pipes, the described the 5th
FinFET pipes, the 6th FinFET pipes and the 7th FinFET pipes are respectively Low threshold FinFET pipe, and described the
The quantity of one FinFET pipe fins is 1, and the quantity of the 2nd FinFET pipe fins is 1, the number of the 3rd FinFET pipe fins
Amount is 1, and the quantity of the 4th FinFET pipe fins is 1, and the quantity of the 5th FinFET pipe fins is the 1, the described the 6th
The quantity of FinFET pipe fins is 1, and the quantity of the 7th FinFET pipe fins is 1；
The backgate of the first FinFET pipes is connected with the upper write word line, the source electrode of the first FinFET pipes, institute
The source electrode for the 2nd FinFET pipes stated and the backgate of the 2nd FinFET pipes access power supply, the first FinFET pipes
Drain, the draining of the front gate of the 2nd FinFET pipes, the 3rd FinFET pipes, the 4th FinFET pipes
Front gate, the draining of the 6th FinFET pipes, the front gate of the 7th FinFET pipes and the 7th FinFET pipes
Back-gate connection and the output end that its connecting pin is the single-ended read-write memory cell, the front gate of the first FinFET pipes,
The drain electrode of the draining of the 2nd FinFET pipes, the front gate of the 3rd FinFET pipes and the 4th FinFET pipes connects
It connects and reversed-phase output that its connecting pin is the single-ended read-write memory cell, the backgate of the 3rd FinFET pipes and institute
That states writes wordline connection, the source electrode of the 3rd FinFET pipes, the source electrode of the 4th FinFET pipes and described the
The backgate of four FinFET pipes accesses the earth, the draining of the 5th FinFET pipes, the source electrode of the 6th FinFET pipes
It is connected with the drain electrode of the 7th FinFET pipes, the source electrode of the 5th FinFET pipes is connected with the bit line, described
The front gate of the 5th FinFET pipes, the backgate of the 5th FinFET pipes connected with the wordline, the described the 6th
The front gate of FinFET pipes, the backgate of the 6th FinFET pipes are connected with the write word line, the 7th FinFET pipes
Source electrode connected with the virtual earth line.
2. a kind of single-ended read-write memory cell based on FinFET according to claim 1, it is characterised in that described
One FinFET is managed and the threshold voltages of the 3rd FinFET pipes is 0.6V, the 2nd FinFET pipes, described the
The threshold value electricity of four FinFET pipes, the 5th FinFET pipes, the 6th FinFET pipes and the 7th FinFET pipes
Pressure is 0.3V.
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| CN103886887A (en) * | 2014-03-31 | 2014-06-25 | 西安华芯半导体有限公司 | Dual-port static random access memory with single-port memory cells |
| US9490008B1 (en) * | 2014-08-12 | 2016-11-08 | Skan Technologies Corporation | 9T, 8T, and 7T Bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write |
| CN106448725A (en) * | 2016-09-21 | 2017-02-22 | 宁波大学 | Read/write splitting memory cell based on FinFET (fin field-effect transistor) devices |
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