CN102385916B - Dual-port static random access memory (SRAM) unit 6T structure with reading-writing separation function - Google Patents
Dual-port static random access memory (SRAM) unit 6T structure with reading-writing separation function Download PDFInfo
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Abstract
The invention discloses a dual-port static random access memory (SRAM) unit 6T structure with a reading-writing separation function. The dual-port SRAM unit 6T structure with a reading-writing separation function is characterized in that a latch circuit comprises a first inverter and a second inverter coupled to the first inverter. The first inverter and the second inverter are connected between a unit voltage source and a unit ground wire. The first inverter comprises a first pull-up transistor and a first pull-down transistor. The second inverter comprises a second pull-up transistor and a second pull-down transistor. Sources of the first pull-up transistor and the second pull-up transistor are connected to the unit voltage source. A grid of the first pull-up transistor is connected to an output end of the second inverter. A grid of the first pull-up transistor is connected to an output end of the first inverter. Sources of the first pull-down transistor and the second pull-down transistor are connected to the unit ground wire. A grid of the first pull-down transistor is connected to the output end of the second inverter. A grid of the first pull-down transistor is connected to the output end of the first inverter. A drain electrode of the first pull-up transistor is connected to a drain electrode of the first pull-down transistor so that a first memory point is formed. A drain electrode of the second pull-up transistor is connected to a drain electrode of the second pull-down transistor so that a second memory point is formed. A transmission transistor is connected respectively to the first memory point, a first bit line and a first word line. A reading transistor is connected respectively to the second memory point, a second bit line and a second word line. The dual-port SRAM unit 6T structure with a reading-writing separation function improves static noise margin (SNM), reduces electric leakage and increases reading currents.
Description
Technical field
The present invention relates to the in-line memory technical field of SIC (semiconductor integrated circuit), be specifically related to a kind of dual-port sram cell 6T structure that read-write separates that has.
Background technology
Static RAM (SRAM) is embedded in nearly all large scale integrated circuit (VLSI), and has played critical effect in requiring high speed, high integration, low-power consumption, low-voltage, low cost, short-period application.Embedded SRAM is compared other memory embedded semiconductors such as dynamic RAM (DRAM) can provide access speed faster, thus in high-end applications in occupation of dominant position.
At first, sram cell can be divided into peripheral circuit and cell array two large divisions on the whole.Wherein peripheral circuit comprises the basic modules such as overall imput output circuit, timing sequence generating circuit, column decode circuitry, column selection circuit, sensitive amplifier circuit; Cell array is formed according to the row and column proper alignment by the SRAM storage unit.The sram cell design is important ingredient in whole SRAM design.Along with dwindling of process, the area of unit significantly dwindles, and operating rate improves, but technique rises and falls and process deviation has proposed challenge on impact and the leakage current of noise margin (SNM) to Unit Design.
The matter of utmost importance of sram cell design is structural design.Traditional sram cell structure is 6 pipes (6T), has afterwards the people to propose 4 pipes, 7 pipes, 8 pipe (8T) and 9 pipe units for different problems.4 pipe units adopt two resistance to substitute the load pipe in six pipe units, and purpose is to reduce area.But failing to be convened for lack of a quorum, Static Electro significantly increases, and because not mating of two resistance can the noise decrease tolerance limit.Read and write operation that 8 pipe units have adopted two other transistor isolation, improved the noise margin of read operation.This partition method provides a class effectively to improve the method for designing of read operation noise margin.According to this thinking, the proposition of the different structure unit such as 7 pipes, 9 pipes and 10 pipes is successively arranged.But the area that 8 pipes, 9 pipes and 10 pipes increase is larger, does not meet highdensity requirement, the electric leakage that the increase of metal-oxide-semiconductor has increased unit simultaneously.The area that 7 pipe units increase is less, but temporary transient floating sky can appear in internal node when read operation, is not full static structure.
How not increasing area, not reducing on the basis of read current to increase the SNM of sram cell and reducing electric leakage becomes sram cell and designs a difficult problem urgently to be resolved hurrily.
Summary of the invention
In order to overcome the shortcoming of above-mentioned prior art, the object of the present invention is to provide a kind of dual-port sram cell 6T structure that read-write separates that has, realize in sram cell improving SNM, reduce electric leakage, increase the purpose of read current.
To achieve these goals, the technical scheme that the present invention proposes is:
A kind of dual-port sram cell 6T structure with read-write separation, its 6T unit 300 comprises that latch cicuit, the first transmission transistor 360 and first read transistor 365, latch cicuit is formed by the first phase inverter 380 intercoupled and the second phase inverter 390, and the first phase inverter 380 and the second phase inverter 390 are connected between cell voltage 310 and ground, unit 315;
The first phase inverter 380 comprises a PMOS the 350 and the one NMOS pull-down transistor 370 that pulls up transistor, the second phase inverter 390 comprises the 2nd PMOS the 355 and the 2nd NMOS pull-down transistor 375 that pulls up transistor, the one PMOS pulls up transistor 350, the 2nd PMOS 355 source electrode orders units voltages 310 that pull up transistor, grid connects the output of another phase inverter, the one NMOS pull-down transistor 370, the 2nd NMOS pull-down transistor 375 source electrode order unit ground 315, grid connects the output of another phase inverter, the one PMOS 350 drain electrodes that pull up transistor are connected with the drain electrode of a NMOS pull-down transistor 370, form the first memory node 340 of 6T structure, the 2nd PMOS 355 drain electrodes that pull up transistor are connected with the drain electrode of the 2nd NMOS pull-down transistor 375, form the second memory node 345 of 6T structure, the first memory node 340 and the second memory node 345 are used for storing a pair of contrary data, the source electrode of the first transmission transistor 360 is connected respectively the first memory node 340 and the first bit line 330 with drain electrode, its grid connects the first word line 320, the first source electrode of reading transistor 365 is connected respectively the second word line 325 and the second bit line 335 with drain electrode, its grid connects the second memory node 345,
The first phase inverter 380, the second phase inverter 390 and the first transmission transistor 360 form and latch transmission circuit 305.
Described the first bit line 330 is for writing bit line, and the first word line 320 is for writing the word line.
Described the second bit line 335 is readout bit line, and the second word line 325 is sense word line.
Described the first transmission transistor 360 is nmos pass transistor.
Described first reads transistor 365 for nmos pass transistor.
A described PMOS who latchs in transmission circuit 305 pull up transistor the 355, the one NMOS pull-down transistor 370, the 2nd NMOS pull-down transistor 375, the first transmission transistor 360 of the 350, the 2nd PMOS that pull up transistor used the high threshold device models, to reduce electric leakage.Because the device threshold under different process is not identical.The high threshold model here, refer to the high threshold device in the high, medium and low threshold value device that technique provides.
The present invention separates the read operation of unit and write operation, significantly improves the SNM of unit; Latch the application of high threshold technology in transmission circuit, reduced the unit electric leakage; The first threshold value and size of reading transistor 365 can not affect cell S NM simultaneously, is conducive to obtain larger read current.Compare with traditional 6T unit, do not increase transistorized number, therefore can not bring area cost, realization improves SNM, reduces to leak electricity, increase the purpose of read current.
The accompanying drawing explanation
Accompanying drawing is circuit diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in detail.
With reference to accompanying drawing, a kind of dual-port sram cell 6T structure with read-write separation, its 6T unit 300 comprises that latch cicuit, the first transmission transistor 360 and first read transistor 365, latch cicuit is formed by the first phase inverter 380 intercoupled and the second phase inverter 390, and the first phase inverter 380 and the second phase inverter 390 are connected between cell voltage 310 and ground, unit 315;
The first phase inverter 380 comprises a PMOS the 350 and the one NMOS pull-down transistor 370 that pulls up transistor, the second phase inverter 390 comprises the 2nd PMOS the 355 and the 2nd NMOS pull-down transistor 375 that pulls up transistor, the one PMOS pulls up transistor 350, the 2nd PMOS 355 source electrode orders units voltages 310 that pull up transistor, grid connects the output of another phase inverter, the one NMOS pull-down transistor 370, the 2nd NMOS pull-down transistor 375 source electrode order unit ground 315, grid connects the output of another phase inverter, the one PMOS 350 drain electrodes that pull up transistor are connected with the drain electrode of a NMOS pull-down transistor 370, form the first memory node 340 of 6T structure, the 2nd PMOS 355 drain electrodes that pull up transistor are connected with the drain electrode of the 2nd NMOS pull-down transistor 375, form the second memory node 345 of 6T structure, the first memory node 340 and the second memory node 345 are used for storing a pair of contrary data, the source electrode of the first transmission transistor 360 is connected respectively the first memory node 340 and the first bit line 330 with drain electrode, its grid connects the first word line 320, the first source electrode of reading transistor 365 is connected respectively the second word line 325 and the second bit line 335 with drain electrode, its grid connects the second memory node 345,
The first phase inverter 380, the second phase inverter 390 and the first transmission transistor 360 form latchs transmission circuit 305.
Described the first bit line 330 is for writing bit line, and the first word line 320 is for writing the word line.
Described the second bit line 335 is readout bit line, and the second word line 325 is sense word line.
Described the first transmission transistor 360 is nmos pass transistor.
Described first reads transistor 365 for nmos pass transistor.
A described PMOS who latchs in transmission circuit 305 pull up transistor the 355, the one NMOS pull-down transistor 370, the 2nd NMOS pull-down transistor 375, the first transmission transistor 360 of the 350, the 2nd PMOS that pull up transistor used the high threshold device models, to reduce electric leakage.
Principle of work of the present invention is:
The definition supply voltage is VDD, is also high level ' 1 '; Power supply ground is VSS, is also low level ' 0 '; Writing boosting voltage is VDDL; Writing the bit line pre-charge pressure is VWBL_pre.In 6T cell operation process of the present invention, each port signal of unit is controlled as follows:
At first, when 6T sram cell of the present invention keeps data, cell voltage 310 is VDD, and ground, unit 315 meets VSS; The first word line 320 remains ' 0 ', and the first transmission transistor 360 is in off state; The first bit line 330 is charged to VWBL_pre in advance; The second word line 325 and the second bit line 335 all remain ' 1 ', and first reads transistor 365 in off state.
Then, when 6T sram cell of the present invention starts write operation, data are delivered on the first bit line 330, and cell voltage 310 is down to VDDL; Then the first word line 320, after cell voltage 310 reduces, is changed to ' 1 ', the first transmission transistor 360 is opened, to the unit data writing.When write operation finishes, first the first word line 320 is reduced to ' 0 ', then cell voltage is increased to VDD and preliminary filling writes bit line to VWBL_pre.
Finally, when 6T sram cell of the present invention carries out read operation, the second word line 325 is reduced to ' 0 '.Now, if what the second memory node 345 was deposited is ' 1 ', first reads transistor 365 opens, and the second 335 of bit lines are read transistor 365 and the drop-down tube discharge of driver be connected with the second word line by first, read the data contrary with the second memory node 345; If what the second memory node 345 was deposited is ' 0 ', first reads transistor 365 turn-offs, and the second bit line 335 does not change, and still reads the data contrary with the second memory node 345.
Claims (4)
1. one kind has the dual-port sram cell 6T structure that read-write separates, it is characterized in that: its 6T unit (300) comprises that latch cicuit, the first transmission transistor (360) and first read transistor (365), latch cicuit is formed by the first phase inverter (380) intercoupled and the second phase inverter (390), and the first phase inverter (380) and the second phase inverter (390) are connected between cell voltage (310) and ground, unit (315);
The first phase inverter (380) comprises that a PMOS pulls up transistor (350) and a NMOS pull-down transistor (370), the second phase inverter (390) comprises that the 2nd PMOS pulls up transistor (355) and the 2nd NMOS pull-down transistor (375), the one PMOS pull up transistor (350), the 2nd PMOS (355) the source electrode order unit voltage (310) that pulls up transistor, grid connects the output of another phase inverter, the one NMOS pull-down transistor (370), the 2nd NMOS pull-down transistor (375) source electrode order unit ground (315), grid connects the output of another phase inverter, the one PMOS pull up transistor (350) drain electrode with the drain electrode of a NMOS pull-down transistor (370), be connected, form
first memory node (340) of structure, the 2nd PMOS pull up transistor (355) drain electrode with the drain electrode of the 2nd NMOS pull-down transistor (375), be connected, formation
second memory node (345) of structure, the first memory node (340) and the second memory node (345) are used for storing a pair of contrary data, the source electrode of the first transmission transistor (360) is connected respectively the first memory node (340) and the first bit line (330) with drain electrode, its grid connects the first word line (320), the first source electrode of reading transistor (365) is connected respectively the second word line (325) and the second bit line (335) with drain electrode, and its grid connects the second memory node (345),
The first phase inverter (380), the second phase inverter (390) and the first transmission transistor (360) form and latch transmission circuit (305);
Described the first bit line (330) is for writing bit line, and the first word line (320) is for writing the word line;
Described the second bit line (335) is readout bit line, and the second word line (325) is sense word line.
2. a kind of dual-port sram cell 6T structure that read-write separates that has according to claim 1, it is characterized in that: described the first transmission transistor (360) is nmos pass transistor.
3. a kind of dual-port sram cell 6T structure that read-write separates that has according to claim 1 is characterized in that: described first to read transistor (365) be nmos pass transistor.
4. a kind of dual-port sram cell 6T structure that read-write separates that has according to claim 1 is characterized in that: a described PMOS who latchs in transmission circuit (305) pulls up transistor (350), the 2nd PMOS pulls up transistor (355), a NMOS pull-down transistor (370), the 2nd NMOS pull-down transistor (375), the first transmission transistor (360) are used the high threshold device model.
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| US8995178B1 (en) * | 2013-10-31 | 2015-03-31 | Freescale Semiconductor, Inc. | SRAM with embedded ROM |
| CN104637532B (en) * | 2013-11-07 | 2017-11-10 | 中芯国际集成电路制造(上海)有限公司 | SRAM memory cell arrays, SRAM memories and its control method |
| CN104751878B (en) * | 2013-12-30 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | The dual-port SRAM structures and its unit of read and write abruption |
| CN105097017A (en) * | 2014-05-20 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | SRAM (static random access memory) storage unit, SRAM memory and control method therefor |
| CN106445831A (en) * | 2015-08-11 | 2017-02-22 | 深圳市中兴微电子技术有限公司 | Storage unit and processing system |
| CN110875071B (en) * | 2018-08-31 | 2022-05-10 | 华为技术有限公司 | SRAM unit and related device |
| CN112309461B (en) * | 2019-07-24 | 2024-03-19 | 中芯国际集成电路制造(上海)有限公司 | SRAM (static random Access memory) storage structure, memory and control method |
| CN112309460B (en) * | 2020-11-20 | 2024-03-12 | 上海华力集成电路制造有限公司 | Dual-port SRAM with separated read and write |
| CN115512672B (en) * | 2022-10-25 | 2023-10-27 | 业成科技（成都）有限公司 | Scan driving circuit and operation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6061268A (en) * | 1999-10-27 | 2000-05-09 | Kuo; James B. | 0.7V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique |
| CN101840728A (en) * | 2010-05-28 | 2010-09-22 | 上海宏力半导体制造有限公司 | Dual-end static random access memory (SRMA) unit |
| CN101923892A (en) * | 2009-06-12 | 2010-12-22 | 台湾积体电路制造股份有限公司 | Stable SRAW cell |
-
2011
- 2011-09-21 CN CN201110282766XA patent/CN102385916B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6061268A (en) * | 1999-10-27 | 2000-05-09 | Kuo; James B. | 0.7V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique |
| CN101923892A (en) * | 2009-06-12 | 2010-12-22 | 台湾积体电路制造股份有限公司 | Stable SRAW cell |
| CN101840728A (en) * | 2010-05-28 | 2010-09-22 | 上海宏力半导体制造有限公司 | Dual-end static random access memory (SRMA) unit |
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