CN102385916A - Dual-port static random access memory (SRAM) unit 6T structure with reading-writing separation function - Google Patents

Dual-port static random access memory (SRAM) unit 6T structure with reading-writing separation function Download PDF

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CN102385916A
CN102385916A CN201110282766XA CN201110282766A CN102385916A CN 102385916 A CN102385916 A CN 102385916A CN 201110282766X A CN201110282766X A CN 201110282766XA CN 201110282766 A CN201110282766 A CN 201110282766A CN 102385916 A CN102385916 A CN 102385916A
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transistor
pull
phase inverter
inverter
unit
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CN102385916B (en
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曹华敏
刘鸣
陈虹
郑翔
王聪
王志华
高志强
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Shenzhen Graduate School Tsinghua University
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Tsinghua University
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Abstract

The invention discloses a dual-port static random access memory (SRAM) unit 6T structure with a reading-writing separation function. The dual-port SRAM unit 6T structure with a reading-writing separation function is characterized in that a latch circuit comprises a first inverter and a second inverter coupled to the first inverter. The first inverter and the second inverter are connected between a unit voltage source and a unit ground wire. The first inverter comprises a first pull-up transistor and a first pull-down transistor. The second inverter comprises a second pull-up transistor and a second pull-down transistor. Sources of the first pull-up transistor and the second pull-up transistor are connected to the unit voltage source. A grid of the first pull-up transistor is connected to an output end of the second inverter. A grid of the first pull-up transistor is connected to an output end of the first inverter. Sources of the first pull-down transistor and the second pull-down transistor are connected to the unit ground wire. A grid of the first pull-down transistor is connected to the output end of the second inverter. A grid of the first pull-down transistor is connected to the output end of the first inverter. A drain electrode of the first pull-up transistor is connected to a drain electrode of the first pull-down transistor so that a first memory point is formed. A drain electrode of the second pull-up transistor is connected to a drain electrode of the second pull-down transistor so that a second memory point is formed. A transmission transistor is connected respectively to the first memory point, a first bit line and a first word line. A reading transistor is connected respectively to the second memory point, a second bit line and a second word line. The dual-port SRAM unit 6T structure with a reading-writing separation function improves static noise margin (SNM), reduces electric leakage and increases reading currents.

Description

A kind of dual-port sram cell 6T structure with read-write separation
Technical field
The present invention relates to the in-line memory technical field of SIC (semiconductor integrated circuit), be specifically related to a kind of dual-port sram cell 6T structure that read-write separates that has.
Background technology
Static RAM (SRAM) is embedded in nearly all large scale integrated circuit (VLSI), and in requiring high speed, high integration, low-power consumption, low-voltage, low cost, short-period application, has played critical effect.Embedded SRAM is compared dynamic RAM (DRAM) and is waited other memory embedded semiconductors that access speed faster can be provided, thus in high-end applications in occupation of dominant position.
At first, sram cell can be divided into peripheral circuit and cell array two large divisions on the whole.Wherein peripheral circuit comprises basic modules such as overall imput output circuit, timing sequence generating circuit, column decode circuitry, column selection circuit, sensitive amplifier circuit; Cell array is then formed according to the row and column proper alignment by the SRAM storage unit.The sram cell design is an important ingredient in the whole SRAM design.Along with dwindling of process, the area of unit significantly dwindles, and operating rate improves, but technology rises and falls and process deviation has proposed challenge to the influence and the leakage current of noise margin (SNM) to unit design.
The matter of utmost importance of sram cell design is a structural design.Traditional sram cell structure is 6 pipes (6T), and the someone is directed against different problems and has proposed 4 pipes, 7 pipes, 8 pipe (8T) and 9 pipe units afterwards.4 pipe units adopt two resistance to substitute the load pipe in six pipe units, and purpose is to reduce area.But quiescent current can significantly increase, and because not matching of two resistance can reduce noise margin.Read and write operation that 8 pipe units have adopted two other transistor isolation has improved the noise margin of read operation.This partition method provides one type of method for designing that effectively improves the read operation noise margin.According to this thinking, the proposition of different structure unit such as 7 pipes, 9 pipes and 10 pipes is arranged successively.But the area that 8 pipes, 9 pipes and 10 pipes increase is bigger, does not meet highdensity requirement, the electric leakage that the increase of metal-oxide-semiconductor has simultaneously increased the unit.The area that 7 pipe units increase is less, but internal node can temporary transient floating sky occur when read operation, be not full static structure.
How not increasing area, the SNM that does not reduce to increase on the basis of read current sram cell becomes the difficult problem that the sram cell design needs to be resolved hurrily with reducing to leak electricity.
Summary of the invention
In order to overcome the shortcoming of above-mentioned prior art, the object of the present invention is to provide a kind of dual-port sram cell 6T structure that read-write separates that has, realize the purpose that improves SNM in the sram cell, reduces to leak electricity, increase read current.
To achieve these goals, the technical scheme of the present invention's proposition is:
A kind of dual-port sram cell 6T structure with read-write separation; Its 6T unit 300 comprises that latch cicuit, first transmission transistor 360 and first read transistor 365; Latch cicuit is formed by first phase inverter 380 that intercouples and second phase inverter 390, and first phase inverter 380 and second phase inverter 390 are connected between cell voltage 310 and the ground, unit 315;
First phase inverter 380 comprises a PMOS the 350 and the one NMOS pull-down transistor 370 that pulls up transistor; Second phase inverter 390 comprises the 2nd PMOS the 355 and the 2nd NMOS pull-down transistor 375 that pulls up transistor; The one PMOS the 350, the 2nd PMOS 355 source electrode orders units voltage 310 that pulls up transistor that pulls up transistor, grid connects the output of another phase inverter, a NMOS pull-down transistor 370, the 2nd NMOS pull-down transistor 375 source electrode orders unit ground 315; Grid connects the output of another phase inverter; The one PMOS 350 drain electrodes that pull up transistor link to each other with the drain electrode of a NMOS pull-down transistor 370, and first memory node, 340, the two PMOS of formation 6T structure pull up transistor and 355 drain and link to each other with the drain electrode of the 2nd NMOS pull-down transistor 375; Form second memory node 345 of 6T structure; First memory node 340 and second memory node 345 are used for storing a pair of opposite data, and the source electrode of first transmission transistor 360 is connected first memory node 340 and first bit line 330 respectively with drain electrode, and its grid connects first word line 320; First read transistor 365 source electrode be connected second word line 325 and second bit line 335 respectively with drain electrode, its grid connects second memory node 345;
First phase inverter 380, second phase inverter 390 and first transmission transistor 360 form and latch transmission circuit 305.
Said first bit line 330 is for writing bit line, and first word line 320 is for writing word line.
Said second bit line 335 is a readout bit line, and second word line 325 is a sense word line.
Said first transmission transistor 360 is a nmos pass transistor.
Said first reads transistor 365 is nmos pass transistor.
A said PMOS who latchs in the transmission circuit 305 pull up transistor the 355, the one NMOS pull-down transistor 370, the 2nd NMOS pull-down transistor 375, first transmission transistor 360 of the 350, the 2nd PMOS that pull up transistor uses the high threshold device models, to reduce electric leakage.Because the device threshold under the different process is inequality.The high threshold model here refers to the high threshold device in the high, medium and low threshold value device that technology provides.
The present invention separates the read operation of unit and write operation, significantly improves the SNM of unit; Latch high threshold The Application of Technology in the transmission circuit, reduced the unit electric leakage; Threshold value and size that while first is read transistor 365 can not influence cell S NM, help obtaining bigger read current.Compare with traditional 6T unit, do not increase transistorized number, therefore can not bring area cost, realize the purpose that improves SNM, reduces to leak electricity, increase read current.
Description of drawings
Accompanying drawing is a circuit diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention is done detailed description.
With reference to accompanying drawing; A kind of dual-port sram cell 6T structure with read-write separation; Its 6T unit 300 comprises that latch cicuit, first transmission transistor 360 and first read transistor 365; Latch cicuit is formed by first phase inverter 380 that intercouples and second phase inverter 390, and first phase inverter 380 and second phase inverter 390 are connected between cell voltage 310 and the ground, unit 315;
First phase inverter 380 comprises a PMOS the 350 and the one NMOS pull-down transistor 370 that pulls up transistor; Second phase inverter 390 comprises the 2nd PMOS the 355 and the 2nd NMOS pull-down transistor 375 that pulls up transistor; The one PMOS the 350, the 2nd PMOS 355 source electrode orders units voltage 310 that pulls up transistor that pulls up transistor, grid connects the output of another phase inverter, a NMOS pull-down transistor 370, the 2nd NMOS pull-down transistor 375 source electrode orders unit ground 315; Grid connects the output of another phase inverter; The one PMOS 350 drain electrodes that pull up transistor link to each other with the drain electrode of a NMOS pull-down transistor 370, and first memory node, 340, the two PMOS of formation 6T structure pull up transistor and 355 drain and link to each other with the drain electrode of the 2nd NMOS pull-down transistor 375; Form second memory node 345 of 6T structure; First memory node 340 and second memory node 345 are used for storing a pair of opposite data, and the source electrode of first transmission transistor 360 is connected first memory node 340 and first bit line 330 respectively with drain electrode, and its grid connects first word line 320; First read transistor 365 source electrode be connected second word line 325 and second bit line 335 respectively with drain electrode, its grid connects second memory node 345;
First phase inverter 380, second phase inverter 390 and first transmission transistor 360 form latchs transmission circuit 305.
Said first bit line 330 is for writing bit line, and first word line 320 is for writing word line.
Said second bit line 335 is a readout bit line, and second word line 325 is a sense word line.
Said first transmission transistor 360 is a nmos pass transistor.
Said first reads transistor 365 is nmos pass transistor.
A said PMOS who latchs in the transmission circuit 305 pull up transistor the 355, the one NMOS pull-down transistor 370, the 2nd NMOS pull-down transistor 375, first transmission transistor 360 of the 350, the 2nd PMOS that pull up transistor uses the high threshold device models, to reduce electric leakage.
Principle of work of the present invention is:
The definition supply voltage is VDD, also is high level ' 1 '; Power supply ground is VSS, also is low level ' 0 '; Writing boosting voltage is VDDL; Write the bit-line pre-charge pressure and be VWBL_pre.In 6T cell operation process of the present invention, each port signal of unit is controlled as follows:
At first, when 6T sram cell of the present invention kept data, cell voltage 310 was VDD, and ground, unit 315 meets VSS; First word line 320 remains ' 0 ', and first transmission transistor 360 is in off state; First bit line, 330 preliminary fillings are to VWBL_pre; Second word line 325 and second bit line 335 all remain ' 1 ', and first reads transistor 365 is in off state.
Then, when 6T sram cell of the present invention began write operation, data were delivered on first bit line 330, and cell voltage 310 is reduced to VDDL; First word line 320 is changed to ' 1 ' after cell voltage 310 reduces then, and first transmission transistor 360 is opened, and the unit is write data.When write operation finishes, earlier first word line 320 is reduced to ' 0 ', again cell voltage is increased to VDD and preliminary filling writes bit line to VWBL_pre.
At last, when 6T sram cell of the present invention carries out read operation, second word line 325 is reduced to ' 0 '.At this moment; If what second memory node 345 was deposited is ' 1 '; First reads transistor 365 opens, and 335 of second bit lines are read transistor 365 and the drop-down tube discharge of driver that links to each other with second word line through first, reads the data opposite with second memory node 345; If what second memory node 345 was deposited is ' 0 ', first reads transistor 365 turn-offs, and second bit line 335 does not change, and still reads the data opposite with second memory node 345.

Claims (6)

1. one kind has the dual-port sram cell 6T structure that read-write separates; It is characterized in that: its 6T unit (300) comprises that latch cicuit, first transmission transistor (360) and first read transistor (365); Latch cicuit is formed by first phase inverter (380) that intercouples and second phase inverter (390), and first phase inverter (380) and second phase inverter (390) are connected between cell voltage (310) and ground, unit (315);
First phase inverter (380) comprises that a PMOS pulls up transistor (350) and a NMOS pull-down transistor (370); Second phase inverter (390) comprises that the 2nd PMOS pulls up transistor (355) and the 2nd NMOS pull-down transistor (375); (355) source electrode order that the one PMOS pulls up transistor (350), the 2nd PMOS pulls up transistor unit voltage (310); Grid connects the output of another phase inverter; The one NMOS pull-down transistor (370), the 2nd NMOS pull-down transistor (375) source electrode order unit ground (315), grid connects the output of another phase inverter, and a PMOS (350) drain electrode that pulls up transistor links to each other with the drain electrode of a NMOS pull-down transistor (370); Form first memory node (340) of 6T structure; The 2nd PMOS (355) drain electrode that pulls up transistor links to each other with the drain electrode of the 2nd NMOS pull-down transistor (375), second memory node (345) of formation 6T structure, and first memory node (340) and second memory node (345) are used for storing a pair of opposite data; The source electrode of first transmission transistor (360) is connected first memory node (340) and first bit line (330) respectively with drain electrode; Its grid connects first word line (320), first read transistor (365) source electrode be connected second word line (325) and second bit line (335) respectively with drain electrode, its grid connects second memory node (345);
First phase inverter (380), second phase inverter (390) and first transmission transistor (360) form latchs transmission circuit (305).
2. a kind of dual-port sram cell 6T structure that read-write separates that has according to claim 1, it is characterized in that: said first bit line (330) is for writing bit line, and first word line (320) is for writing word line.
3. a kind of dual-port sram cell 6T structure that read-write separates that has according to claim 1, it is characterized in that: said second bit line (335) is a readout bit line, and second word line (325) is a sense word line.
4. a kind of dual-port sram cell 6T structure that read-write separates that has according to claim 1, it is characterized in that: said first transmission transistor (360) is a nmos pass transistor.
5. a kind of dual-port sram cell 6T structure that read-write separates that has according to claim 1 is characterized in that: said first to read transistor (365) be nmos pass transistor.
6. a kind of dual-port sram cell 6T structure that read-write separates that has according to claim 1 is characterized in that: a said PMOS who latchs in the transmission circuit (305) pulls up transistor (350), the 2nd PMOS pulls up transistor (355), a NMOS pull-down transistor (370), the 2nd NMOS pull-down transistor (375), first transmission transistor (360) use the high threshold device model.
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CN104599707A (en) * 2013-10-31 2015-05-06 飞思卡尔半导体公司 SRAM with embedded ROM
CN104637532A (en) * 2013-11-07 2015-05-20 中芯国际集成电路制造(上海)有限公司 SRAM storage unit array, SRAM memory and control method thereof
CN104751878A (en) * 2013-12-30 2015-07-01 中芯国际集成电路制造(上海)有限公司 Read and write separating dual-port SRAM (static random access memory) structure and unit
CN105097017A (en) * 2014-05-20 2015-11-25 中芯国际集成电路制造(上海)有限公司 SRAM (static random access memory) storage unit, SRAM memory and control method therefor
WO2017024873A1 (en) * 2015-08-11 2017-02-16 深圳市中兴微电子技术有限公司 Memory unit and processing system
CN110875071A (en) * 2018-08-31 2020-03-10 华为技术有限公司 SRAM unit and related device
CN112309460A (en) * 2020-11-20 2021-02-02 上海华力集成电路制造有限公司 Read-write separated dual-port SRAM
CN112309461A (en) * 2019-07-24 2021-02-02 中芯国际集成电路制造(上海)有限公司 SRAM (static random Access memory) storage structure, memory and control method
CN115512672A (en) * 2022-10-25 2022-12-23 业成科技（成都）有限公司 Scan driving circuit and operating method thereof

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CN101840728A (en) * 2010-05-28 2010-09-22 上海宏力半导体制造有限公司 Dual-end static random access memory (SRMA) unit
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US6061268A (en) * 1999-10-27 2000-05-09 Kuo; James B. 0.7V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique
CN101923892A (en) * 2009-06-12 2010-12-22 台湾积体电路制造股份有限公司 Stable SRAW cell
CN101840728A (en) * 2010-05-28 2010-09-22 上海宏力半导体制造有限公司 Dual-end static random access memory (SRMA) unit

Cited By (17)

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Publication number Priority date Publication date Assignee Title
CN104599707A (en) * 2013-10-31 2015-05-06 飞思卡尔半导体公司 SRAM with embedded ROM
CN104599707B (en) * 2013-10-31 2019-03-29 恩智浦美国有限公司 SRAM with Embedded ROM
CN104637532A (en) * 2013-11-07 2015-05-20 中芯国际集成电路制造(上海)有限公司 SRAM storage unit array, SRAM memory and control method thereof
CN104637532B (en) * 2013-11-07 2017-11-10 中芯国际集成电路制造(上海)有限公司 SRAM memory cell arrays, SRAM memories and its control method
CN104751878A (en) * 2013-12-30 2015-07-01 中芯国际集成电路制造(上海)有限公司 Read and write separating dual-port SRAM (static random access memory) structure and unit
CN104751878B (en) * 2013-12-30 2018-03-09 中芯国际集成电路制造(上海)有限公司 The dual-port SRAM structures and its unit of read and write abruption
CN105097017A (en) * 2014-05-20 2015-11-25 中芯国际集成电路制造(上海)有限公司 SRAM (static random access memory) storage unit, SRAM memory and control method therefor
WO2017024873A1 (en) * 2015-08-11 2017-02-16 深圳市中兴微电子技术有限公司 Memory unit and processing system
CN110875071A (en) * 2018-08-31 2020-03-10 华为技术有限公司 SRAM unit and related device
CN110875071B (en) * 2018-08-31 2022-05-10 华为技术有限公司 SRAM unit and related device
US11456030B2 (en) 2018-08-31 2022-09-27 Huawei Technologies Co., Ltd. Static random access memory SRAM unit and related apparatus
CN112309461A (en) * 2019-07-24 2021-02-02 中芯国际集成电路制造(上海)有限公司 SRAM (static random Access memory) storage structure, memory and control method
CN112309461B (en) * 2019-07-24 2024-03-19 中芯国际集成电路制造(上海)有限公司 SRAM (static random Access memory) storage structure, memory and control method
CN112309460A (en) * 2020-11-20 2021-02-02 上海华力集成电路制造有限公司 Read-write separated dual-port SRAM
CN112309460B (en) * 2020-11-20 2024-03-12 上海华力集成电路制造有限公司 Dual-port SRAM with separated read and write
CN115512672A (en) * 2022-10-25 2022-12-23 业成科技（成都）有限公司 Scan driving circuit and operating method thereof
CN115512672B (en) * 2022-10-25 2023-10-27 业成科技（成都）有限公司 Scan driving circuit and operation method thereof

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