CN103871461B - A kind of be applicable to SRAM write duplicate circuit - Google Patents
A kind of be applicable to SRAM write duplicate circuit Download PDFInfo
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Abstract
The present invention provide a kind of be applicable to SRAM write duplicate circuit, by replicating wordline load, replicating bit-line load, duplication bit line selector and replicate write driver, write copied cells, state machine, line decoder, storage array, control circuit and Pre-decoder, bit line selector and sense amplifier and input/output circuitry composition.Load in wordline when replicating wordline load simulation normal write operation, the load on bit line when replicating the bit-line load normal write operation of simulation, replicate bit line selector and simulate bit line selector during normal write operation and write driver with duplication write driver, writing the memory element being written over when copied cells simulates normal write operation, state machine provides the State Transferring between starting and terminating for normal write operation.This circuit is normally write " 0 " by simulation and is operated, and provides accurate self-timing for SRAM write operation under different process voltage temperature.Compared with prior art wordline pulse width during write operation declines 20%.
Description
[technical field]
The present invention relates to SRAM design field, particularly to a kind of be applicable to SRAM write duplication electricity
Road.
[background technology]
SRAM is as the important memory element in integrated circuit, due to its high-performance, high reliability, low-power consumption etc.
Advantage is widely used in high-performance calculation device system (CPU), SOC(system on a chip) (SOC), and handheld device etc. calculates field.
Along with the continuous evolution of Technology, constantly reducing of dimensions of semiconductor devices, the local and process deviation of the overall situation, to integrated
The performance of circuit, the impact that reliability causes is increasing.In order to overcome this impact, some are to process voltage temperature (PVT)
On insensitive sheet, adaptive technique has obtained studying widely and applying in recent years.By increasing duplicate circuit on sheet, follow the tracks of
PVT environmental change is to whole chip performance, the impact of reliability, and feeds back to control system, adjusts some crucial ginseng in circuit
Number, the state that the Performance And Reliability that makes chip operation can reach under current PVT environment is optimal.
Reading duplicate circuit is exactly that such a is applied in SRAM, is used for following the tracks of under different PVT environment, static with
Wordline pulse width during machine memory read operation is to provide enough bitline discharge time, it is ensured that the voltage difference on bit line, permissible
A kind of technology that is reliable by sense amplifier, that quickly amplify.For SRAM, read access generally needs than write access
The more time.Therefore, in traditional SRAM design, read duplicate circuit and be also used to produce required for write operation
Wordline pulse width.For the application that those read access times are the most crucial, such design is rational.But for those
The application that the write access time is the most crucial or the most crucial, such design obviously means that surdimensionnement (over-design),
The performance that can not reach whole system is optimal.
Therefore, it is designed to SRAM under accurate tracking difference PVT environment be reliably rapidly completed required for write access
Wordline pulse width write duplicate circuit, be significantly.
[summary of the invention]
It is an object of the invention to propose a kind of be applicable to SRAM write duplicate circuit, this circuit is normally write by simulation
During operation, memory element is write " 0 " operation, provides essence for SRAM write operation under different process voltage temperature
True self-timing.
To achieve these goals, the present invention adopts the following technical scheme that
A kind of be applicable to SRAM write duplicate circuit, including replicating wordline load, replicating bit-line load, replicate position
Line selector with replicate write driver, write copied cells, state machine, line decoder, storage array, control circuit and Pre-decoder,
Bit line selector and sense amplifier and imput output circuit；
Replicate wordline load by replicating wordline connection status machine, writing copied cells and replicate bit line selector and replicate write driver；
Replicate bit-line load and write copied cells by replicating bit line connection, and replicate bit line selector and replicate write driver；
Write copied cells by writing complete marking signal line connection status machine；
State machine is enabled by wordline and connects line decoder, and state machine connects control circuit and Pre-decoder also by local clock；
Line decoder connects storage array by a plurality of wordline and replicates bit-line load；
Storage array loads also by multiple bit lines Connection-copy wordline, bit line selector and sense amplifier and imput output circuit.
The present invention is further improved by: described duplication bit line selector with replicate write driver, when simulating normal write operation
Bit line selector and write driver.
The present invention is further improved by: described in write copied cells, the memory element being written over when simulating normal write operation.
The present invention is further improved by: described state machine, provides State Transferring between starting for normal write operation and terminate.
The present invention is further improved by: when write operation starts, and duplication bit line is replicated bit line selector and writes driving with duplication
Device rushes in advance to pre-charge level VDD；According to the address of input, write enable and clock, control circuit produce this with Pre-decoder
Ground clock；In the rising edge of local clock, state machine set, replicate wordline and wordline enables effectively；Replicate wordline along replicating wordline
Load, is connected to write copied cells and replicate bit line selector and replicate write driver；Replicate bit line selector and replicate write driver
Bit line discharges will be replicated to low level；Replicate bit line and be rewritten as " 0 " by being stored in advance in " 1 " value write in copied cells；Write
Become marking signal effective, feed back to state machine, by resets, replicate wordline and enable invalidating signal with wordline；Wordline enables letter
Number pulse width equal to replicating the pulse width of wordline, line decoder enables signal according to wordline to carry out level wordline signal cutting
Take, produce pulse word-line signal required during normal write operation；Wherein replicate bit-line load to be used for simulating in regular array connecting
Receive the load on bit line, replicate wordline load and be used for simulating the load being connected in regular array in wordline；When replicating, wordline is invalid
Time, write the value in copied cells and will be reset to " 1 ", replicate bit line simultaneously and also will be rushed in advance to pre-punching electricity level VDD.
The present invention is further improved by: write copied cells by NMOS transmission gate, reset PMOS transistor and phase inverter
Composition；The grid end of reset PMOS transistor connects VSS；The grid Connection-copy wordline of NMOS transmission gate, source electrode connects multiple
Bit line processed, drain electrode connects memory node；The source electrode of reset PMOS transistor meets VDD, and grid connects VSS, and drain electrode connects storage
Node and the input of phase inverter, the outfan connection of phase inverter writes complete marking signal line.
The present invention is further improved by: replicate bit line selector with replicate write driver include replicate precharge PMOS,
Replicate bit line selector NMOS tube and replicate write driver NMOS tube；Replicate the grid termination VDD of write driver NMOS tube,
Source meets VSS, and drain electrode connects and replicates write bit line and replicate the source electrode of bit line selector NMOS tube；Replicate wordline Connection-copy bit line
The grid of selector NMOS tube, the source electrode replicating precharge PMOS connects VDD, replicates the grid of precharge PMOS
Pole Connection-copy wordline, replicates the drain electrode Connection-copy bit line of bit line selector NMOS tube and replicates the leakage of precharge PMOS
Pole.
The present invention is further improved by: state machine is made up of with door and buffer phase inverter, the first nor gate, the second nor gate；
Local clock connects the input of phase inverter, and the outfan of phase inverter connects an input of the first nor gate, the first nor gate
Outfan is connected to an input of the second nor gate, and another input connection of the second nor gate writes complete marking signal line,
The outfan of the second nor gate connect the first nor gate another input and with an input of door, with another input of door
End connects local clock；Being connected the input of buffer with the outfan of door and replicate wordline, the outfan of buffer connects wordline to be made
Can signal.
Relative to prior art, when the invention have the advantages that this circuit by simulating normal write operation, memory element is write " 0 "
Operation, provides accurate self-timing for SRAM write operation under different process voltage temperature.Read with traditional use
The design that duplicate circuit controls as self-timing is compared, and wordline pulse width during the design write operation declines 20%.
[accompanying drawing explanation]
Fig. 1 is a typical data path schematic diagram of SRAM.
Fig. 2 is the SRAM schematic diagram implemented according to the present invention.
Fig. 3 is for writing copied cells circuit design principle figure.
Fig. 4 is for replicating bit line selector and replicating write driver circuit design principle figure.
Fig. 5 is state machine circuit design principle figure.
[detailed description of the invention]
Below in conjunction with the accompanying drawings embodiments of the present invention are described further.
Referring to shown in Fig. 1, Fig. 1 is a typical data path example of SRAM.This typical data path includes
Pre-charge circuit, memory element, bit line selector, sense amplifier and write driver.
Pre-charge circuit is by PMOS transistor 12, and 13,15 are constituted.Phase inverter 16 that memory element is coupled by pair of cross,
17 and the NMOS transfer tube 19,20 that is respectively connected with memory node 22,23 constitute.Bit line selector is by a pair NMOS
Transistor 24,27 and a pair pmos transistor 25,26 are constituted.Sense amplifier 36 in sense amplifier such as Fig. 1.Write driving
Device is made up of phase inverter 38 and a pair tristate inverter 35,37.
When the holding pattern of static memory, the wordline 14 of memory element is invalid (high level is effective), and bit line 18 is anti-with bit line
21 are maintained at pre-punching electricity level VDD.Owing to now NMOS transfer tube 19,20 is closed, end to end phase inverter 16,17
Forming positive feedback, be stored in memory node 22, the data of 23 keep stable.
When the read operation of SRAM, bit line 18 and bit line anti-21 are rushed electricity in advance and are arrived pre-charge level VDD, in advance
Charging signals 11 invalid (Low level effective).Wordline 14 is opened, and bit line 18 and bit line anti-21 are according to memory node 22,23
Value electric discharge.The one end storing " 0 " in memory element to corresponding bit line discharges, can make the bit-line levels of this side less than precharge
Level VDD, then at two bit lines 18, establishes voltage difference between 21.Sense bit line selects signal 28 effectively, and bit line selects
PMOS transistor 25 in device, 26 open, and the voltage on anti-to bit line 18 and bit line 21 is delivered separately to sense amplifier 36
Input, sense bit line 30 and sense bit line anti-33.When the voltage difference on sense bit line 30 with sense bit line anti-33 reaches sense amplifier
36 detected sensitive electrical pressure differential deltap V time, sense amplifier enable signal 39 effective (high level is effective), sense amplifier work
Make, sense bit line 30 and the small signal difference reading line anti-33 are amplified to full swing signal, output to output data terminal 41.
When the write operation of SRAM, bit line 18 and bit line anti-21 are rushed electricity in advance and are arrived pre-charge level VDD, in advance
Charging signals 11 is invalid.Writing enable 34 effective (high level is effective), input data 40 are by reverser 38 and tristate inverter
Data and the counter of data are respectively transmitted on write bit line 31 and write bit line anti-32 by 35,37.Write bit line selects signal 29 effectively,
Nmos pass transistor 24 in bit line selector, 27 open, by anti-to write bit line 31 and write bit line 32 respectively with bit line 18 and 21 phase
Even.The bit line being attached thereto is discharged to by pre-charge level VDD by write bit line 31 anti-with write bit line 32 for low level one end
Low level.Effectively, NMOS transfer tube 19,20 is opened for wordline 14, by memory node 22,23 respectively with bit line 18, bit line
Anti-21 are connected.If memory node 22, the level of 23 respectively anti-with bit line 18 and bit line 21 level identical, then store joint
The level of point 22,23 does not changes.Otherwise, bit line 18 and bit line anti-21 will rewrite memory node 22, the level of 23.
Referring to shown in Fig. 2, Fig. 2 is the SRAM example implemented according to the present invention.This SRAM
Including replicating wordline load 105, duplication bit-line load 103, replicating bit line selector and replicate write driver 108, write duplication list
Unit 106, state machine 109, line decoder 101, storage array 102, control circuit and Pre-decoder 104, bit line selector
Form with sense amplifier and input/output circuitry 107.
When write operation starts, duplication bit line 132 is replicated bit line selector and rushes in advance to pre-charge level with replicating write driver 108
VDD.According to the address of input, write enable and clock 110, control circuit and Pre-decoder 104 produce local clock 144.
Effectively (high level has to enable 158 in the rising edge of local clock 144, state machine 109 set, duplication wordline 134 and wordline
Effect).Replicate wordline 134 and load 105 along replicating wordline, be connected to write copied cells 106 and replicate bit line selector write with duplication
Driver 108.Replicate bit line selector, with replicating write driver 108, duplication bit line 132 is discharged to low level.Replicate bit line
132 are rewritten as " 0 " by being stored in advance in " 1 " value write in copied cells 106.Write complete marking signal 136 effectively (high electricity
Flat effective), feed back to state machine 109, state machine 109 is resetted, replicate wordline 134 and wordline enable signal 158 is invalid.
The pulse width of wordline enable signal 158 i.e. replicates the pulse width of wordline 134, is i.e. by writing copied cells 106 according to currently
Produced by the process voltage temperature of circuit, during normal write operation, wordline 122 can be reliable, is rapidly completed memory element write access
Required pulse width.Line decoder 101 enables signal 158 according to wordline and intercepts level wordline signal, is just producing
Often required during write operation pulse word-line signal 122.Wherein replicate bit-line load 103 and be used for simulating connection in regular array
Load on bit line, replicates wordline load 105 and is used for simulating the load being connected in regular array in wordline.When replicating wordline
134 invalid time, write the value in copied cells 106 and will be reset to " 1 ", replicate bit line 132 simultaneously and also will be rushed in advance to pre-punching
Electricity level VDD.
Referring to shown in Fig. 3, Fig. 3 is the circuit design principle figure writing copied cells 106.This writes copied cells 106 by NMOS
Transmission gate 131, reset PMOS transistor 135 and phase inverter 137 form.Grid due to reset PMOS transistor 135
Terminating on VSS, PMOS 135 turns on all the time.The grid Connection-copy wordline 134 of NMOS transmission gate 131, source
Pole Connection-copy bit line 132, drain electrode connects memory node 133；The source electrode of reset PMOS transistor 135 connects VDD, grid
Connecting VSS, drain electrode connects memory node 133 and the input of phase inverter 137, and the outfan connection of phase inverter 137 writes complete mark
Will holding wire 136.
When keeping pattern, replicating wordline 134 invalid (high level is effective), NMOS transfer tube 131 turns off.Owing to resetting
The source of PMOS 135 is connected on VDD, and stable " 1 " value is stored on memory node 133.Write complete marking signal
136 for deposit the anti-phase of memory node 133, the most invalid.
When write operation, replicating wordline 134 effective (high level is effective), NMOS transfer tube 131 is opened.Replicate bit line 132
It is discharged to low level with replicating write driver 108 by replicating bit line selector shown in Fig. 2.NMOS transfer tube 131 will replicate
In " 0 " value write memory node 133 on bit line 132, write complete marking signal 136 effective.
Owing to reset PMOS 135 is always on, can compete when writing the operation of " 0 ".Solution is by multiple
The size of position PMOS 135 takes and pull-up PMOS of phase inverter in normal memory cell (such as phase inverter 16,17 in Fig. 1)
Pipe equivalently-sized, the size of NMOS transfer tube 131 more than transfer tube in normal memory cell (such as NMOS transmission in Fig. 1
Pipe 19,20) size, to guarantee correct to write " 0 " operation；The size of the middle pull-down NMOS of phase inverter 137 is more than just
The size of pull-down NMOS pipe in phase inverter (such as phase inverter 16,17 in Fig. 1) in normal memory element, to meet phase inverter 137
Load request.
Referring to Fig. 4, Fig. 4 is to replicate bit line selector and the circuit design principle figure replicating write driver 108.This circuit includes
Replicate precharge PMOS 141 (PMOS 12,13 in pre-charge circuit in simulation drawing 1), replicate bit line selector NMOS
Pipe 142 (NMOS tube 24,27 in write bit line selector in simulation drawing 1) and duplication write driver NMOS tube 144 (simulation
Phase inverter 35,37 in write driver in Fig. 1).Replicating the grid termination VDD of write driver NMOS tube 144, source meets VSS,
Drain electrode connects duplication write bit line 143, therefore replicates write driver NMOS tube 144 and opens all the time, and replicates write bit line 143 all the time
For low level.Replicate wordline 134 and connect the grid of NMOS tube 142 and the grid level of PMOS 141, PMOS 141
Source electrode connect VDD, the drain Connection-copy bit line 132 of PMOS 141 and the drain electrode of NMOS tube 142, NMOS
The source electrode Connection-copy write bit line 143 of pipe 142.
When keeping pattern, replicate wordline 134 invalid (high level is effective), replicate bit line selector NMOS tube 142 and close,
Precharge PMOS 141 is opened.Replicate bit line 132 to be rushed in advance to pre-charge level VDD.
When write operation, replicating wordline 134 effective (high level is effective), precharge PMOS 141 is closed, and replicates bit line choosing
Select device NMOS tube 142 to open, write duplication bit line 143 and duplication bit line 132 is discharged to low level.
Referring to Fig. 5, Fig. 5 is state machine 109 circuit design principle figure.This state machine by phase inverter 151, nor gate 152,
153, with door 156, buffer 157 forms.Wherein local clock 144 connects the input of phase inverter 151, phase inverter 151
Outfan connect an input of nor gate 152, the output 154 of nor gate 152 be connected to nor gate 153 one is defeated
Entering end, another input connection of nor gate 153 writes complete marking signal 136, and the output 155 of nor gate 153 is connected to
Another input of nor gate 152 and an input with door 156, be connected this locality with another input of door 156
Clock 144, two nor gates so connected constitute a simple R S-trigger.It is connected buffer with the outfan of door 156
The input of 157 and duplication wordline 134, the outfan of buffer 157 connects wordline and enables signal 158.
When keeping pattern, local clock 144 is low level, writes complete marking signal 136 for low level.RS-trigger defeated
Going out 155 is high level, and RS-trigger is in SM set mode.Owing to local clock 144 is low level, the output of RS-trigger
155 with local clock through with door 156 phase with after, replicate wordline 134 be low level, wordline enable signal 158 be low level.
When write operation, local clock 144 is high level, and RS-trigger is in SM set mode.Owing to local clock 144 is high
Level, the output 155 of RS-trigger and local clock through with door 156 phase with after, replicating wordline 134 is high level, word
It is high level that line enables signal 158.Replicate wordline 134 effectively to make as in Fig. 2, duplication r/w cell 106 occurs duplication to write " 0 "
Operation.At the end of " 0 " operation is write in duplication, write complete marking signal 136 and become high level.RS-trigger output 155 change
For low level, RS-trigger enters reset state.The output 155 of RS-trigger and local clock through with door 156 phase with after,
Replicating wordline 134 and become low level, wordline enables signal 158 and becomes low level.
Claims (7)
1. one kind be applicable to SRAM write duplicate circuit, it is characterised in that include replicating wordline load, replicating position
Linear load, replicate bit line selector with replicate write driver, write copied cells, state machine, line decoder, storage array, control
Circuit and Pre-decoder, bit line selector and sense amplifier and imput output circuit；
Replicate wordline load by replicating wordline (DWL) connection status machine, writing copied cells and replicate bit line selector and duplication
Write driver；
Replicate bit-line load and write copied cells by replicating bit line (DBL) connection, and replicate bit line selector and replicate write driver；
Write copied cells by writing complete marking signal line (WR_DONE) connection status machine；
State machine enables (WL_EN) by wordline and connects line decoder, and state machine connects also by local clock (LCLK)
Control circuit and Pre-decoder；
Line decoder connects storage array by a plurality of wordline (WL) and replicates bit-line load；
Storage array loads also by multiple bit lines (BL) Connection-copy wordline, bit line selector and sense amplifier and input defeated
Go out circuit；
When write operation starts, duplication bit line is replicated bit line selector and rushes in advance to pre-charge level VDD with replicating write driver；
According to the address of input, write enable and clock, control circuit produce local clock with Pre-decoder；At the rising edge of local clock,
State machine set, replicates wordline and wordline enables effectively；Replicate wordline and load along replicating wordline, be connected to write copied cells and duplication
Bit line selector and duplication write driver；Replicate bit line selector and replicate write driver by duplication bit line discharges to low level；Replicate
Bit line is rewritten as " 0 " by being stored in advance in " 1 " value write in copied cells；Write complete marking signal effective, feed back to state machine,
By resets, replicate wordline and enable invalidating signal with wordline；Wordline enables the pulse width of signal equal to the pulse replicating wordline
Width, line decoder enables signal according to wordline and intercepts level wordline signal, produces pulse required during normal write operation
Word-line signal；Wherein replicate bit-line load and be used for simulating the load being connected in regular array on bit line, replicate wordline load and use
Simulate the load being connected in regular array in wordline；When replicating wordline and being invalid, writing the value in copied cells will be reset to
" 1 ", replicates bit line simultaneously and also will be rushed in advance to pre-punching electricity level VDD.
Be applicable to SRAM the most as claimed in claim 1 writes duplicate circuit, it is characterised in that described duplication position
Line selector with replicate write driver, bit line selector when simulating normal write operation and write driver.
Be applicable to SRAM the most as claimed in claim 1 writes duplicate circuit, it is characterised in that described in write duplication
Unit, the memory element being written over when simulating normal write operation.
Be applicable to SRAM the most as claimed in claim 1 writes duplicate circuit, it is characterised in that described state machine,
State Transferring is provided between starting for normal write operation and terminate.
Be applicable to SRAM the most as claimed in claim 1 writes duplicate circuit, it is characterised in that write copied cells
By NMOS transmission gate (131), reset PMOS transistor (135) and phase inverter (137) composition；Reset PMOS is brilliant
The grid end of body pipe (135) connects VSS；The grid Connection-copy wordline of NMOS transmission gate (131), source electrode Connection-copy position
Line, drain electrode connects memory node；The source electrode of reset PMOS transistor (135) meets VDD, and grid connects VSS, and drain electrode connects
Memory node (133) and the input of phase inverter (137), the outfan connection of phase inverter (137) writes complete marking signal line.
Be applicable to SRAM the most as claimed in claim 1 writes duplicate circuit, it is characterised in that replicate bit line choosing
Select device with replicate write driver include replicate precharge PMOS (141), replicate bit line selector NMOS tube (142) and
Replicate write driver NMOS tube (144)；Replicating the grid termination VDD of write driver NMOS tube (144), source meets VSS,
Drain electrode connects and replicates write bit line (143) and replicate the source electrode of bit line selector NMOS tube (142)；Replicate wordline (134) even
Connecing the grid replicating bit line selector NMOS tube (142), the source electrode replicating precharge PMOS (141) connects VDD,
Replicate grid Connection-copy wordline (134) of precharge PMOS (141)；Replicate bit line selector NMOS tube (142)
Drain electrode Connection-copy bit line (132) and replicate precharge PMOS (141) drain electrode.
Be applicable to SRAM the most as claimed in claim 1 writes duplicate circuit, it is characterised in that state machine is by instead
Phase device (151), the first nor gate (152), the second nor gate (153) and door (156) and buffer (157) composition；
Local clock connects the input of phase inverter (151), and the outfan of phase inverter (151) connects the one of the first nor gate (152)
Individual input, the outfan of the first nor gate (152) is connected to an input of the second nor gate (153), and second or non-
Another input of door (153) connects and writes complete marking signal line, the outfan of the second nor gate (153) connect first or
Another input of not gate (152) and an input with door (156), be connected with another input of door (156)
Local clock；It is connected the input of buffer (157) with the outfan of door (156) and replicates wordline, buffer (157)
Outfan connects wordline and enables signal.
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| CN201410126264.1A CN103871461B (en) | 2014-03-31 | 2014-03-31 | A kind of be applicable to SRAM write duplicate circuit |
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| CN201410126264.1A CN103871461B (en) | 2014-03-31 | 2014-03-31 | A kind of be applicable to SRAM write duplicate circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104575590B (en) * | 2015-01-13 | 2017-06-09 | 安徽大学 | A kind of both-end pipeline-type replicates bit line circuit |
| CN107767907B (en) * | 2017-10-30 | 2019-10-25 | 上海集成电路研发中心有限公司 | A kind of voltage-controlled magnetic anisotropy magnetic RAM and its judgment method |
| CN109979504B (en) * | 2019-03-29 | 2020-12-01 | 长江存储科技有限责任公司 | Control circuit of static random access memory |
| CN112652337B (en) * | 2019-10-10 | 2024-03-12 | 上海磁宇信息科技有限公司 | Line decoder for memory |
| CN111768807A (en) * | 2020-06-28 | 2020-10-13 | 上海磁宇信息科技有限公司 | Word line power supply control circuit for magnetic random memory cell |
| CN115547383B (en) * | 2022-12-01 | 2023-03-03 | 安徽大学 | Storage circuit and magnetic random access memory read key circuit |
| CN116206651B (en) * | 2023-05-05 | 2023-07-14 | 华中科技大学 | Wide-voltage-domain SRAM read-write time sequence control circuit and method |
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