CN205645282U - Static RAM of low -power consumption - Google Patents
Static RAM of low -power consumption Download PDFInfo
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- CN205645282U CN205645282U CN201620468006.6U CN201620468006U CN205645282U CN 205645282 U CN205645282 U CN 205645282U CN 201620468006 U CN201620468006 U CN 201620468006U CN 205645282 U CN205645282 U CN 205645282U
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Abstract
The utility model relates to a static RAM of low -power consumption, including the storage array, word line decoding and driver, bit line precharge and balanced device, the write driver, write control circuit and sensitive amplifier, it produces bit line precharge signal PRE to write control circuit, bit line equalizing signal EQ with write enable signal WE, bit line precharge includes NMOS transistor N0 with the balanced device, NMOS transistor N1 and NMOS transistor N2, bit line precharge signal PRE connects NMOS transistor N0 and NMOS transistor N1's bars end, bit line equalizing signal EQ connects NMOS transistor N2's bars end, bit line charging source is in advance all connected to NMOS transistor N0's source end and NMOS transistor N1's source end, write enable signal WE and connect the write driver. The utility model provides a current high technical problem of static RAM write operation energy consumption, the utility model discloses the bit line upset consumption that the write operation consumed each time is 0.5 CBL VCC2, compares the CBL VCC2 of traditional technique, has reduced 50%.
Description
Technical field
This utility model relates to SRAM design field, particularly to the static state of a kind of low-power consumption
Random access memory.
Background technology
SRAM is as the important memory element in integrated circuit, due to its high-performance, high
Reliability, the advantage such as low-power consumption is widely used in high-performance calculation device system (CPU), SOC(system on a chip)
(SOC), handheld device etc. calculate field.According to the estimation of ITRS ITRS, arrive
2016, Embedded SRAM area accounted for whole calculator system (CPU), and sheet is
The 90% of system (SOC) area.Its power consumption consumed accounts for whole calculator system (CPU), sheet on sheet
The 40% of upper system (SOC), wherein dynamic power consumption accounts for about 14%.For SRAM
Write operation, usual bit line needs full swing to operate, and has only to discharge compared to bit line during read operation the least
Voltage difference, sense amplifier small voltage difference for being amplified to full swing, write operation consume power consumption more
Greatly.
As it is shown in figure 1, the SRAM that Fig. 1 is traditional writes data-path circuit design principle figure.
This is write data path and includes the precharge of multiple 6 transistor memory units, bit line and equalizer and write driver.
Multiple 6 transistor memory unit shared bit line BL and the anti-BL_N of bit line.Assume that bit line BL and bit line are anti-
Load capacitance on BL_N is respectively CBL and CBL_N.
Multiple 6 transistor memory units connect bit line precharge with equal respectively by bit line BL and the anti-BL_N of bit line
Weighing apparatus and write driver；
Bit line precharge is Jun Heng by 2 precharge PMOS transistor P0, P1 and one with equalizer
PMOS transistor P2 forms.Bit line BL connects drain terminal and the source of transistor P2 of transistor P0.
The anti-BL_N of bit line connects drain terminal and the drain terminal of transistor P2 of transistor P1.Bit line precharge inverted signal
PRE_N connects the grid end of P0-P2.SRAM supply voltage VCC connection transistor P0,
The source of transistor P1.
In conjunction with Fig. 2, traditional SRAM writes the oscillogram of data path so that this circuit to be described
Operation principle.
When keeping pattern, write enable signal WE is low, and write driver is closed.The anti-letter of bit line precharge
Number PRE_N is low, bit line precharge and 3 PMOS transistor in equalizer all in conducting state,
Bit line BL and the anti-BL_N of bit line is charged to supply voltage VCC in advance.
All of word-line signal WL is low, and being in of the most all of 6 transistor memory units keeps data shape
State.
When write operation, first, bit line precharge inverted signal PRE_N is drawn high, in bit line precharge and equalizer
3 PMOS transistor (P0-P2) turn off, bit line BL and bit line anti-BL_N floating.Then, write
It is high for enabling signal WE, and write driver is opened, write driver will write the driving of data D to bit line BL with
The anti-BL_N of bit line.In bit line BL and the anti-BL_N of bit line wherein one be maintained at pre-charge level VCC,
Another is discharged into ground VSS from VCC, and this process, owing to not extracting electric current from power supply VCC, disappears
The energy of consumption is 0.Then, 6 selected transistor memory unit wordline WL are drawn high, and write driver is by driving
The data rewriting of storage in 6 transistor memory units that dynamic bit line BL and the anti-BL_N of bit line will choose.When selected
In 6 transistor memory units in the data rewriting of storage when completing, wordline WL drags down, 6 selected pipes
Storage keeps its data being written over.Then write enable signal drags down, write driver close, bit line BL and
Bit line anti-BL_N floating.Then, bit line precharge inverted signal PRE_N drags down, and bit line precharge is with equal
3 PMOS transistor conductings in weighing apparatus, are power supply electricity before in bit line BL and the anti-BL_N of bit line
One bit lines of pressure VCC is maintained at VCC, and the bit lines for ground VSS is charged to VCC before.
This process extracts electric current from power supply VCC, and the energy of consumption is CBL VCC VCC, i.e.
CBL·VCC2.After in sum, for write operation each time, drive position including write driver during write operation
Line BL and the anti-BL_N of bit line, and when write operation completes, bit line is pre-charged with equalizer bit line BL and position
The equilibrium of the anti-BL_N of line and precharge operation, for BL_N anti-to every pair of bit lines BL and bit line, its
The upset power consumption consumed is: the energy of consumption during write operation disappears when adding up line precharge with equalization operation
The energy of consumption, i.e. 0+CBL VCC2, for CBL VCC2。
Summary of the invention
The technical problem high in order to solve existing SRAM write operation energy consumption, this utility model
The SRAM of a kind of low-power consumption and the control method of write operation thereof are provided.
Technical solution of the present utility model:
A kind of SRAM of low-power consumption, including storage array, word line decoding and driver 104,
Bit line precharge and equalizer, write driver, write control circuit 102 and sense amplifier, it is special
Part is: described write control circuit 102 produces Bit line pre-charge signal PRE, bit line equalizing signal EQ
With write enable signal WE, the precharge of described bit line includes nmos pass transistor N0, NMOS with equalizer
Transistor N1 and nmos pass transistor N2.
Bit line pre-charge signal PRE connects the grid end of nmos pass transistor N0 and nmos pass transistor N1,
Bit line equalizing signal EQ connects the grid end of nmos pass transistor N2, and bit line BL connects NMOS crystal
The drain terminal of pipe N0 and the source of nmos pass transistor N2, the anti-BL_N of bit line connects nmos pass transistor
The drain terminal of N1 and the drain terminal of nmos pass transistor N2, the source of nmos pass transistor N0 and NMOS
The source of transistor N1 is all connected with bit line precharge power supply；
Write enable signal WE connects write driver.
Bit line pre-charge signal PRE, bit line equalizing signal EQ and write enable signal WE meet following bar
Part:
When Bit line pre-charge signal PRE and bit line equalizing signal EQ step-down, write operation begins preparing for；
When write enable signal WE uprises, write operation starts；
When write enable signal WE step-down, write operation terminates；
Uprise as balance stage when bit line equalizing signal EQ uprises Bit line pre-charge signal PRE；
It is pre-charging stage when Bit line pre-charge signal PRE is in high state.
Above-mentioned write control circuit include two input nand gate the 601, first phase inverter the 602, second phase inverters 603,
The input of 3rd phase inverter 604, delay unit 605, first liang inputs and door 607 with door 606 and second liang,
Clock signal after the input termination write enable signal WEX of described two input nand gates 601 and time delay
CLKD, the outfan of described two input nand gates inputs and door with the first phase inverter 602, first liang respectively
606 and second liang of input be connected with the input of door 607, the outfan of described first phase inverter 602 with
The input of the second phase inverter 603 connects, the outfan of the second phase inverter 603 respectively with the 3rd phase inverter
604 and first liang of input be connected with the input of door 606, the outfan of described second phase inverter 603 passes through
Delay unit 605 is connected with the input of door 607 with second liang of input, described 3rd phase inverter 604
Outfan output write enable signal WE, described first liang of input is Jun Heng with the outfan output bit-line of door 606
Signal EQ, described second liang of input and the outfan output bit-line precharging signal PRE of door.
Above-mentioned bit line precharge power supply is 1/2nd of SRAM supply voltage VCC.
The control method of the write operation of memorizer, comprises the following steps:
1) Bit line pre-charge signal PRE and bit line equalizing signal EQ drags down, bit line precharge and equalizer
Middle nmos pass transistor N0, nmos pass transistor N1 and nmos pass transistor N2 turn off, bit line BL
BL_N floating anti-with bit line；
2) write enable signal WE uprises, and write driver is opened, and write driver will be write data D and drive to position
Line BL and the anti-BL_N of bit line；
3) selected in storage array memory element wordline WL is drawn high, and write driver is by driving bit line
BL and the bit line anti-BL_N memory element to choosing carry out write operation；
4) when selected memory cell write-operation completes, wordline WL drags down, selected storage list
Unit keeps its data being written over；
5) write enable signal WE drags down, and write driver is closed, bit line BL and bit line anti-BL_N floating；
Then, bit line equalizing signal EQ draws high, bit line precharge and the nmos pass transistor N2 in equalizer
There is charge share in conducting, bit line BL and the anti-BL_N of bit line；
6) when bit line BL and bit line anti-BL_N charge share reach VCC/2, Bit line pre-charge signal
PRE draws high, bit line precharge and the nmos pass transistor N0 in equalizer and nmos pass transistor N1
Opening, bit line BL and the anti-BL_N of bit line is maintained at VCC/2.
This utility model have the advantage that:
1, the bit line upset power consumption that this utility model write operation each time is consumed is 0.5 CBL VCC2,
Compare the CBL VCC of traditional technology2, decrease 50%.
2, the precharge of this utility model bit line uses nmos pass transistor with equalizer.Due to same size
The performance of nmos pass transistor is that the mobility of PMOS is high 2 to 3 times, therefore for identical driving energy
Power, uses nmos pass transistor the size of transistor can be reduced to 1/2 to the 1/3 of PMOS transistor,
Such that it is able to saving area.
Accompanying drawing explanation
The SRAM that Fig. 1 is traditional writes data-path circuit design principle figure.
The SRAM that Fig. 2 is traditional writes the oscillogram of data path.
Fig. 3 is the SRAM schematic diagram implemented according to this utility model.
Fig. 4 is that SRAM of the present utility model writes data-path circuit design principle figure.
Fig. 5 is the oscillogram that SRAM of the present utility model writes data path.
Fig. 6 is write control circuit design principle figure.
Detailed description of the invention
Below in conjunction with the accompanying drawings embodiment of the present utility model is described further.
Referring to shown in Fig. 3, Fig. 3 is that the SRAM implemented according to this utility model shows
It is intended to.This SRAM includes control circuit and Pre-decoder 101, write control circuit 102, position
Line precharge and equalizer, write driver and sense amplifier 103, word line decoding and driver 104, deposit
Storage array 105.
Control circuit connects bit line with Pre-decoder 101 by a plurality of row control signal and is pre-charged with Jun Heng
Device, write driver and sense amplifier 103；
Control circuit and Pre-decoder 101 are also by writing enable after the clock CLKD after time delay and latch
WEX connects write control circuit 103；
Control circuit is connected word line decoding and driving with Pre-decoder 101 also by a plurality of row pre-decode YPD
Device 104；
Write control circuit 102, by Bit line pre-charge signal PRE, bit line equalizing signal EQ, writes enable letter
Number WE connects bit line precharge, equalizer, write driver and sense amplifier 103；
Word line decoding is connected storage array 105 with driver 104 by a plurality of wordline WL；
Storage array 105 connects bit line precharge, equalizer, write driver and spirit by multiple bit lines BL
Quick amplifier 103.
Referring to shown in Fig. 4, Fig. 4 is that SRAM of the present utility model writes data-path circuit
Design principle figure.This is write data path and includes multiple 6 transistor memory units, and bit line is pre-charged and equalizer,
Write driver.
Multiple 6 transistor memory unit shared bit line BL and the anti-BL_N of bit line.Assume that bit line BL and bit line are anti-
Load capacitance on BL_N is respectively CBL and CBL_N.
Multiple 6 transistor memory units connect bit line by bit line BL and the anti-BL_N of bit line and are pre-charged and equalizer
And write driver；
Bit line precharge is Jun Heng by 2 precharge nmos pass transistor N0, N1 and one with equalizer
Nmos pass transistor N2 forms.Bit line BL connects drain terminal and the source of N2 of N0.The anti-BL_N of bit line
Connect drain terminal and the drain terminal of N2 of N1.Bit line pre-charge signal PRE connects the grid end of N0, N1.Position
Line equalizing signal EQ connects the grid end of N2.Bit line precharge power supply VCC/2 connects the source of N0, N1.
In conjunction with Fig. 5, SRAM of the present utility model is write the oscillogram of data path and this is described
The operation principle of circuit.
When keeping pattern, write enable signal WE is low, and write driver is closed.Bit line pre-charge signal
PRE and bit line equalizing signal EQ is high, and in bit line precharge, equalizer, 2 precharge NMOS are brilliant
Body pipe N0, N1 and an equilibrium nmos pass transistor N2 are all in conducting state, bit line BL and bit line
Anti-BL_N is maintained at bit line precharge power supply VCC/2.
All of word-line signal WL is low, and the most all of 6 transistor memory units are in keeping data shape
State.
When write operation, first, Bit line pre-charge signal PRE and bit line equalizing signal EQ drags down, position
Line precharge is brilliant with in equalizer 2 precharge nmos pass transistor N0, a N1 and Jun Heng NMOS
Body pipe N2 turns off, bit line BL and bit line anti-BL_N floating.Then, write enable signal WE is high,
Write driver is opened, and write driver will be write data D and drive to the anti-BL_N of bit line BL and bit line.Bit line
In BL and the anti-BL_N of bit line wherein one be charged to SRAM supply voltage from VCC/2
VCC, the energy of this process consumption is CBL VCC/2 VCC, is 0.5 CBL VCC2；Another from
VCC/2 discharges into ground VSS, and this process extracts electric current owing to not being pre-charged power supply VCC/2 from bit line,
The energy consumed is 0.Then, 6 selected transistor memory unit wordline WL are drawn high, and write driver passes through
The data rewriting of storage in 6 transistor memory units that driving bit line BL and the anti-BL_N of bit line will choose.Work as quilt
When in 6 transistor memory units chosen, the data rewriting of storage completes, wordline WL drags down, selected 6
Pipe storage keeps its data being written over.Then write enable signal drags down, and write driver is closed, bit line BL
BL_N floating anti-with bit line.Then, bit line equalizing signal EQ draws high, in bit line precharge and equalizer
Equilibrium nmos pass transistor N2 conducting, there is charge share, wherein in bit line BL and the anti-BL_N of bit line
Originally be ground VSS bit-line levels begin to ramp up, be SRAM supply voltage VCC originally
Bit line begin to decline.Due to bit line BL and load capacitance CBL of the anti-BL_N of bit line and CBL_N phase
Deng, between bit line BL and the anti-BL_N of bit line, the final result of charge share is, bit line BL and bit line are anti-
It is (VCC+0) that BL_N arrives the level in the middle of SRAM supply voltage VCC and ground VSS
/ 2, i.e. VCC/2.This process, owing to not extracting electric current from bit line precharge power supply VCC/2, therefore disappears
The energy of consumption is 0.When bit line BL and bit line anti-BL_N charge share reach VCC/2, bit line preliminary filling
Signal of telecommunication PRE draws high, and bit line precharge is beaten with precharge nmos pass transistor N0, the N1 in equalizer
Opening, bit line BL and the anti-BL_N of bit line is maintained at VCC/2.In sum, for write operation each time,
Drive bit line BL and the anti-BL_N of bit line including write driver during write operation, and when write operation completes, bit line is pre-
Charging, the equilibrium of equalizer BL_N anti-to bit line BL and bit line and precharge operation, to every pair of bit lines
For BL and the anti-BL_N of bit line, its upset power consumption consumed is that the energy of consumption during write operation adds
The energy consumed when bit line precharge, equalization operation, i.e. 0.5 CBL VCC2+ 0, it is 0.5 CBL VCC2。
Referring to Fig. 6, Fig. 6 is write control circuit design principle figure.This control circuit is by two input nand gates
601, phase inverter 602-604, delay unit 605, two inputs form with door 606,607.
After write enable signal WEX after latch and time delay, clock CLKD is respectively two input nand gates 601
Two inputs.WEX_N connects the output of two input nand gates 601, connects the input of phase inverter 602,
Connect an input of two inputs and door 606,607.WEX_D connects the output of phase inverter 602 with anti-
The input of phase device 603.WEN_D1 connects the output of phase inverter 603, connects the input of phase inverter 604,
Connect another input of two inputs and door 606, connect the input of delay unit 605.WEN_D2 is even
Connect the output of delay unit 605, connect another input of two inputs and door 607.Write enable signal WE
Connect the output of phase inverter 604.Bit line equalizing signal EQ connects the output of two inputs and door 606.Bit line
Precharging signal PRE connects the output of two inputs and door 607.
Wherein delay unit 605 is made up of chain of inverters, its role is to when write operation completes, and postpones
The rising edge of Bit line pre-charge signal PRE, to provide time enough to open by bit line equalizing signal EQ
Fig. 4 neutrality line equalizer line N2, makes bit line BL and bit line BL_N complete charge share, reaches VCC/2.
It is advantageous in that, when the rising edge of Bit line pre-charge signal PRE arrives, and bit line BL and the anti-BL_N of bit line
Being complete charge share, reach VCC/2, bit line preliminary filling fulgurite N0, N1 of opening are served only for position
Line BL and the anti-BL_N of bit line is maintained at VCC/2, takes out without from bit line precharge power supply VCC/2
Take any electric current, thus reach to save the purpose of bit line upset power consumption.
Claims (4)
1. a SRAM for low-power consumption, including storage array, word line decoding and driver
(104), bit line precharge and equalizer, write driver, write control circuit (102) and sensitive amplification
Device, it is characterised in that: described write control circuit (102) generation Bit line pre-charge signal PRE, bit line are equal
Weighing apparatus signal EQ and write enable signal WE, the precharge of described bit line includes nmos pass transistor with equalizer
N0, nmos pass transistor N1 and nmos pass transistor N2,
Bit line pre-charge signal PRE connects the grid end of nmos pass transistor N0 and nmos pass transistor N1,
Bit line equalizing signal EQ connects the grid end of nmos pass transistor N2, and bit line BL connects NMOS crystal
The drain terminal of pipe N0 and the source of nmos pass transistor N2, the anti-BL_N of bit line connects nmos pass transistor
The drain terminal of N1 and the drain terminal of nmos pass transistor N2, the source of nmos pass transistor N0 and NMOS
The source of transistor N1 is all connected with bit line precharge power supply；
Write enable signal WE connects write driver.
The SRAM of low-power consumption the most according to claim 1, it is characterised in that: bit line
Precharging signal PRE, bit line equalizing signal EQ and write enable signal WE meet following condition:
When Bit line pre-charge signal PRE and bit line equalizing signal EQ step-down, write operation begins preparing for；
When write enable signal WE uprises, write operation starts；
When write enable signal WE step-down, write operation terminates；
Uprise as balance stage when bit line equalizing signal EQ uprises Bit line pre-charge signal PRE；
It is pre-charging stage when Bit line pre-charge signal PRE is in high state.
The SRAM of low-power consumption the most according to claim 1 and 2, it is characterised in that:
Described write control circuit includes two input nand gates (601), the first phase inverter (602), the second phase inverter
(603), the 3rd phase inverter (604), delay unit (605), first liang input with door (606) and
Second liang of input and door (607), the input termination write enable signal of described two input nand gates (601)
Clock signal clk D after WEX and time delay, the outfan of described two input nand gates is anti-phase with first respectively
Device (602), first liang of input connect with door (606) and second liang of input inputted with door (607)
Connecing, the outfan of described first phase inverter (602) and the input of the second phase inverter (603) connect,
The outfan of the second phase inverter (603) inputs and door (606) with the 3rd phase inverter (604) and first liang respectively
Input connect, the outfan of described second phase inverter (603) is through delay unit (605) and the
Two liang of inputs are connected with the input of door (607), the outfan output of described 3rd phase inverter (604)
Write enable signal WE, described first liang of input and the outfan output bit-line equalizing signal EQ of door (606),
Described second liang of input and the outfan output bit-line precharging signal PRE of door.
The SRAM of low-power consumption the most according to claim 3, it is characterised in that: described
Bit line precharge power supply is 1/2nd of SRAM supply voltage VCC.
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| CN201620468006.6U CN205645282U (en) | 2016-05-20 | 2016-05-20 | Static RAM of low -power consumption |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105895148A (en) * | 2016-05-20 | 2016-08-24 | 西安紫光国芯半导体有限公司 | Low-power consumption static random access memory and control method of writing operation of low-power consumption static random access memory |
| CN112992203A (en) * | 2021-03-24 | 2021-06-18 | 长鑫存储技术有限公司 | Sense amplifier, memory and control method |
| US12033690B2 (en) | 2021-03-24 | 2024-07-09 | Changxin Memory Technologies, Inc. | Sense amplifier, memory and control method |
-
2016
- 2016-05-20 CN CN201620468006.6U patent/CN205645282U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105895148A (en) * | 2016-05-20 | 2016-08-24 | 西安紫光国芯半导体有限公司 | Low-power consumption static random access memory and control method of writing operation of low-power consumption static random access memory |
| CN105895148B (en) * | 2016-05-20 | 2018-11-09 | 西安紫光国芯半导体有限公司 | A kind of Static RAM of low-power consumption and its control method of write operation |
| CN112992203A (en) * | 2021-03-24 | 2021-06-18 | 长鑫存储技术有限公司 | Sense amplifier, memory and control method |
| CN112992203B (en) * | 2021-03-24 | 2022-05-17 | 长鑫存储技术有限公司 | Sense amplifier, memory and control method |
| US12033690B2 (en) | 2021-03-24 | 2024-07-09 | Changxin Memory Technologies, Inc. | Sense amplifier, memory and control method |
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