CN203799670U - Write copy circuit applicable to static RAM (random access memory) - Google Patents
Write copy circuit applicable to static RAM (random access memory) Download PDFInfo
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- CN203799670U CN203799670U CN201420152049.4U CN201420152049U CN203799670U CN 203799670 U CN203799670 U CN 203799670U CN 201420152049 U CN201420152049 U CN 201420152049U CN 203799670 U CN203799670 U CN 203799670U
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Abstract
The utility model provides a write copy circuit applicable to a static RAM (random access memory). The write copy circuit applicable to the static RAM consists of a copy word line load, a copy bit line load, a copy bit line selector, a copy write actuator, a write copy unit, a state machine, a row decoder, a memory array, a control circuit and a pre-decoder, a bit line selector, a sense amplifier as well as an input/output circuit. The copy word line load simulates the load on a word line in normal write operation; the copy bit line load simulates the load on a bit line during normal write operation; the copy bit line selector and the copy write actuator simulate the bit line selector and the write driver in normal operation; the write copy unit simulates the rewritten memory unit in normal write operation; the state machine provides state conversion between beginning and ending for the normal write operation. The circuit provides accurate self-timing for write operation of the static RAM under different technology voltage temperatures by simulating the normal write '0' operation. Compared with the prior art, the word line pulse width in write operation decreases by 20%.
Description
[technical field]
The utility model relates to static RAM design field, particularly a kind of duplicate circuit of writing that is applicable to static RAM.
[background technology]
Static RAM is as the important memory element in integrated circuit, due to its high-performance, and high reliability, the advantages such as low-power consumption are widely used in high-performance calculation device system (CPU), SOC (system on a chip) (SOC), the calculating fields such as handheld device.
Along with the continuous evolution of technology, constantly the dwindling of dimensions of semiconductor devices, local and overall process deviation, to the performance of integrated circuit, the impact that reliability causes is increasing.In order to overcome this impact, some have obtained research widely and application in recent years to insensitive upper adaptive technique of process voltage temperature (PVT).By increase duplicate circuit on sheet, follow the tracks of PVT environmental change to whole chip performance, the impact of reliability, and feed back to control system, some key parameter in Circuit tuning, makes the state of Performance And Reliability the best that chip operation can reach under current PVT environment.
Reading duplicate circuit is exactly that such one is applied in static RAM, be used for following the tracks of under different PVT environment, wordline pulse width when static RAM read operation, so that the enough bit line discharges time to be provided, guarantee the voltage difference on bit line, can be reliable by sense amplifier, a kind of technology of amplifying fast.For static RAM, read access needs the more time than write access conventionally.Therefore,, in traditional static RAM design, read duplicate circuit and be also used to produce the needed wordline pulse width of write operation.For the more crucial application of those read access times, such design is rational.But for the same crucial or more crucial application of those write access times, such design obviously means surdimensionnement (over-design), can not reach performance the best of whole system.
Therefore, under can the accurate tracking different PVT environment of design, static RAM reliably completes the duplicate circuit of writing of the needed wordline pulse width of write access fast, is very significant.
[utility model content]
The purpose of this utility model is to propose a kind of duplicate circuit of writing that is applicable to static RAM, this circuit when simulating normal write operation to storage unit write " 0 " operation, for the write operation of static RAM under different process voltage temperature provides accurate self-timing.
To achieve these goals, the utility model adopts following technical scheme:
A kind of duplicate circuit of writing that is applicable to static RAM, comprise copy word linear load, copy bit-line load, copy bit line selector switch and copy write driver, write copied cells, state machine, line decoder, storage array, control circuit and pre-decode device, bit line selector switch and sense amplifier and imput output circuit;
Copy word linear load by copying word line connect state machine, writing copied cells and copy bit line selector switch and copy write driver;
Copy bit-line load and write copied cells by copying bit line connection, and copy bit line selector switch and copy write driver;
Write copied cells by having write marking signal line connect state machine;
State machine connects line decoder by word line enable, and state machine also connects control circuit and pre-decode device by local clock;
Line decoder is connected storage array and is copied bit-line load by many word lines;
Storage array is also by multiple bit lines Connection-copy word linear load, bit line selector switch and sense amplifier and imput output circuit.
The utility model further improves and is: described in copy bit line selector switch and copy write driver, bit line selector switch and write driver while simulating normal write operation.
The utility model further improves and is: described in write copied cells, the storage unit of being rewritten while simulating normal write operation.
The utility model further improves and is: described state machine, and for normal write operation provides state conversion between starting and finishing.
The utility model further improves and is: in the time that write operation starts, copy bit line and be replicated bit line selector switch and copy write driver and rush in advance to pre-charge level VDD; According to the address of input, write and enable and clock, produce local clock by control circuit and pre-decode device; At the rising edge of local clock, state machine set, copies word line and word line enable effective; Copy word line along copying word linear load, be connected to and write copied cells and copy bit line selector switch and copy write driver; Copy bit line selector switch and copy write driver and will copy bit line discharges to low level; Copy bit line and be rewritten as " 0 " by pre-stored in " 1 " value of writing in copied cells; Write marking signal effective, fed back to state machine, state machine has been resetted, copied word line and word line enable invalidating signal; The pulse width of word line enable signal equals to copy the pulse width of word line, and line decoder intercepts level word-line signal according to word line enable signal, needed pulse word-line signal while producing normal write operation; Wherein copy bit-line load and be used for simulating in regular array and be connected to the load on bit line, copy word linear load and be used for simulating and in regular array, be connected to the load on word line; When copying word line when invalid, the value of writing in copied cells will be reset to " 1 ", and copy bit line also will be by pre-punching to rushing in advance level VDD simultaneously.
The utility model further improves and is: write copied cells by NMOS transmission gate, reset PMOS transistor and phase inverter composition; The transistorized grid end of reset PMOS connects VSS; The grid Connection-copy word line of NMOS transmission gate, source electrode Connection-copy bit line, drain electrode connects memory node; The transistorized source electrode of reset PMOS meets VDD, and grid connects VSS, and drain electrode connects the input end of memory node and phase inverter, and the output terminal of phase inverter connects has write marking signal line.
The utility model further improves and is: copy bit line selector switch and copy write driver and comprise and copy precharge PMOS pipe, copy bit line selector switch NMOS pipe and copy write driver NMOS pipe; The grid termination VDD that copies write driver NMOS pipe, source meets VSS, and drain electrode connects and copies write bit line; Copy the grid of word line Connection-copy bit line selector switch NMOS pipe, the source electrode that copies precharge PMOS pipe connects VDD, copy the grid Connection-copy bit line and the drain electrode that copies bit line selector switch NMOS pipe of precharge PMOS pipe, copy the source electrode Connection-copy word line of bit line selector switch NMOS pipe.
The utility model further improves and is: state machine is made up of with door and impact damper phase inverter, the first rejection gate, the second rejection gate; Local clock connects the input end of phase inverter, the input end of phase inverter connects an input end of the first rejection gate, the output terminal of the first rejection gate is connected to an input end of the second rejection gate, another input end of the second rejection gate connects has write marking signal line, the output terminal of the second rejection gate connects input end of rejection gate and an input end with door, is connected local clock with another input end of door; Be connected the input end of impact damper with the output terminal of door and copy word line, the output terminal connective word line enable signal of impact damper.
With respect to prior art, the utlity model has following advantage: this circuit when simulating normal write operation to storage unit write " 0 " operation, for the write operation of static RAM under different process voltage temperature provides accurate self-timing.Read duplicate circuit as compared with the design of self-timing control with traditional use, wordline pulse width when the design's write operation declines 20%.
[brief description of the drawings]
Fig. 1 is a typical data path schematic diagram of static RAM.
Fig. 2 is a static RAM schematic diagram of implementing according to the utility model.
Fig. 3 is for writing copied cells circuit design principle figure.
Fig. 4 is for copying bit line selector switch and copying write driver circuit design principle figure.
Fig. 5 is state machine circuit design concept figure.
[embodiment]
Below in conjunction with accompanying drawing, embodiment of the present utility model is described further.
Refer to shown in Fig. 1 the typical data path example that Fig. 1 is static RAM.This typical data path comprises pre-charge circuit, storage unit, bit line selector switch, sense amplifier and write driver.
Pre-charge circuit is made up of PMOS transistor 12,13,15.The phase inverter 16,17 that storage unit is coupled by pair of cross and NMOS transfer tube 19,20 formations that are connected respectively with memory node 22,23.Bit line selector switch is made up of pair of NMOS transistors 24,27 and a pair pmos transistor 25,26.Sense amplifier is as sense amplifier in Fig. 1 36.Write driver is made up of phase inverter 38 and a pair of tristate inverter 35,37.
In the time of the Holdover mode of static memory, the word line 14 of storage unit invalid (high level is effective), bit line 18 remains on pre-punching level VDD with bit line anti-21.Because NMOS transfer tube 19,20 is now closed, end to end phase inverter 16,17 forms positive feedbacks, and the data that are stored in memory node 22,23 keep stable.
In the time of the read operation of static RAM, bit line 18 and bit line anti-21 arrived pre-charge level VDD, precharging signal 11 invalid (Low level effective) by pre-subpunch electricity.Word line 14 is opened, anti-21 electric discharges of the value according to memory node 22,23 of bit line 18 and bit line.In storage unit, one end of storage " 0 " can be to corresponding bit line discharges, makes the bit-line levels of this side lower than pre-charge level VDD, so set up voltage difference between two bit lines 18,21.Sense bit line selects signal 28 effective, and in bit line selector switch, PMOS transistor 25,26 is opened, and the voltage on bit line 18 and bit line anti-21 is passed to respectively to the input of sense amplifier 36, sense bit line 30 and sense bit line anti-33.In the time that sense bit line 30 reaches the poor Δ V of detected sense voltage of sense amplifier 36 with the voltage difference on sense bit line anti-33, sense amplifier enable signal 39 effective (high level is effective), sense amplifier work, by sense bit line 30 and the poor full swing signal that is amplified to of small signal of reading line anti-33, output to output data terminal 41.
In the time of the write operation of static RAM, bit line 18 and bit line anti-21 is by pre-subpunch electricity to pre-charge level VDD, and precharging signal 11 is invalid.Write and enable 34 effective (high level is effective), input data 40 are by reverser 38 and tristate inverter 35,37 being instead transferred to respectively on write bit line 31 and write bit line anti-32 data and data.Write bit line selects signal 29 effective, and in bit line selector switch, nmos pass transistor 24,27 is opened, and is connected respectively anti-to write bit line 31 and write bit line 32 with bit line 18 with 21.In write bit line 31 and write bit line anti-32, for low level one end, the bit line being attached thereto is discharged to low level by pre-charge level VDD.Word line 14 is effective, and NMOS transfer tube 19,20 is opened, by memory node 22,23 respectively with bit line 18, bit line anti-21 is connected.If the level of memory node 22,23 is identical with the level of bit line 18 and bit line anti-21 respectively, the level of memory node 22,23 does not change.Otherwise bit line 18 and bit line anti-21 will be rewritten the level of memory node 22,23.
Refer to shown in Fig. 2, Fig. 2 is a static RAM example of implementing according to the utility model.This static RAM comprise copy word linear load 105, copy bit-line load 103, copy bit line selector switch and copy write driver 108, write copied cells 106, state machine 109, line decoder 101, storage array 102, control circuit and pre-decode device 104, bit line selector switch and sense amplifier and input/output circuitry 107 form.
In the time that write operation starts, copy bit line 132 and be replicated bit line selector switch and copy write driver 108 and rush in advance to pre-charge level VDD.According to the address of input, write and enable and clock 110, produce local clock 144 by control circuit and pre-decode device 104.At the rising edge of local clock 144, state machine 109 set, copy word line 134 and word line enable 158 effective (high level is effective).Copy word line 134 along copying word linear load 105, be connected to and write copied cells 106 and copy bit line selector switch and copy write driver 108.Copy bit line selector switch and copy write driver 108 and will copy bit line 132 and be discharged to low level.Copy bit line 132 and be rewritten as " 0 " by pre-stored in " 1 " value of writing in copied cells 106.Write marking signal 136 effective (high level is effective), fed back to state machine 109, state machine 109 has been resetted, copied word line 134 invalid with word line enable signal 158.The pulse width of word line enable signal 158 copies the pulse width of word line 134, be that word line 122 can be reliable when writing the normal write operation that copied cells 106 produces according to the process voltage temperature of current circuit, complete fast the needed pulse width of storage unit write access.Line decoder 101 intercepts level word-line signal according to word line enable signal 158, needed pulse word-line signal 122 while producing normal write operation.Wherein copy bit-line load 103 and be used for simulating in regular array and be connected to the load on bit line, copy word linear load 105 and be used for simulating and in regular array, be connected to the load on word line.When copying word line 134 when invalid, the value of writing in copied cells 106 will be reset to " 1 ", and copy bit line 132 also will be by pre-punching to rushing in advance level VDD simultaneously.
Refer to shown in Fig. 3, Fig. 3 is the circuit design principle figure that writes copied cells 106.This writes copied cells 106 by NMOS transmission gate 131, and reset PMOS transistor 135 and phase inverter 137 form.Because the grid of reset PMOS transistor 135 terminate at VSS above, PMOS manages 135 conductings all the time.The grid Connection-copy word line 134 of NMOS transmission gate 131, source electrode Connection-copy bit line 132, drain electrode connects memory node 133; The source electrode of reset PMOS transistor 135 meets VDD, and grid connects VSS, and drain electrode connects the input end of memory node 133 and phase inverter 137, and the output terminal of phase inverter 137 connects has write marking signal line 136.
In the time of Holdover mode, copy word line 134 invalid (high level is effective), NMOS transfer tube 131 turn-offs.Because the source of reset PMOS pipe 135 is connected on VDD above, stable " 1 " value is stored on memory node 133.Write marking signal 136 for to deposit the anti-phase of memory node 133, now invalid.
In the time of write operation, copy word line 134 effective (high level is effective), NMOS transfer tube 131 is opened.Copying bit line 132 is copied bit line selector switch and copies write driver 108 and be discharged to low level shown in Fig. 2.NMOS transfer tube 131 writes " 0 " value copying on bit line 132 in memory node 133, has write marking signal 136 effective.
Because reset PMOS pipe 135 is opened all the time, in the time writing the operation of " 0 ", can compete.Solution be by the size of reset PMOS pipe 135 get with normal memory cell in phase inverter (as phase inverter in Fig. 1 16,17) on, draw the measure-alike of PMOS pipe, the size of NMOS transfer tube 131 is greater than transfer tube in normal memory cell (as NMOS transfer tube 19 in Fig. 1,20) size, to guarantee correct writing " 0 " operation; The size of the middle pull-down NMOS of phase inverter 137 is greater than the size of pull-down NMOS pipe in phase inverter in normal memory cell (as phase inverter in Fig. 1 16,17), to meet the load request of phase inverter 137.
Refer to Fig. 4, Fig. 4 copies bit line selector switch and the circuit design principle figure that copies write driver 108.This circuit comprises copying and in precharge PMOS pipe 141(simulation drawing 1, rushes in advance PMOS pipe 12 in circuit, 13), copy in bit line selector switch NMOS pipe 142(simulation drawing 1 NMOS pipe 24 in write bit line selector switch, 27) and copy in write driver NMOS pipe 144(simulation drawing 1 phase inverter 35,37 in write driver).The grid termination VDD that copies write driver NMOS pipe 144, source meets VSS, and drain electrode connects and copies write bit line 143, therefore copies write driver NMOS pipe 144 and opens all the time, and copy write bit line 143 and be always low level.Copy the grid that word line 134 connects NMOS pipe 142, the source electrode of PMOS pipe 141 connects VDD, the drain electrode of the grid Connection-copy bit line 132 of PMOS pipe 141 and NMOS pipe 142, the source electrode Connection-copy word line 134 of NMOS pipe 142.
In the time of Holdover mode, copy word line 134 invalid (high level is effective), copy bit line selector switch NMOS pipe 142 and close, precharge PMOS pipe 141 is opened.Copying bit line 132 is rushed in advance to pre-charge level VDD.
In the time of write operation, copy word line 134 effective (high level is effective), precharge PMOS pipe 141 is closed, and copies bit line selector switch NMOS pipe 142 and opens, and writes to copy bit line 143 and will copy bit line 132 and be discharged to low level.
Refer to Fig. 5, Fig. 5 is state machine 109 circuit design principle figure.This state machine is by phase inverter 151, rejection gate 152,153, and with door 156, impact damper 157 forms.Wherein local clock 144 connects the input end of phase inverter 151, the input end of phase inverter 151 connects an input end of rejection gate 152, the output 154 of rejection gate 152 is connected to an input end of rejection gate 153, another input end of rejection gate 153 connects has write marking signal 136, the output 155 of rejection gate 153 has been connected to input end of rejection gate 154 and an input end with door 156, be connected local clock 144 with another input end of door 156, two rejection gates that so connect have formed a simple R S-trigger.Be connected the input end of impact damper 157 with the output terminal of door 156 and copy word line 134, the output terminal connective word line enable signal 158 of impact damper 157.
In the time of Holdover mode, local clock 144 is low level, has write marking signal 136 for low level.The output 155 of RS-trigger is high level, and RS-trigger is in SM set mode.Because local clock 144 is low level, the output 155 of RS-trigger and local clock through with door 156 with after, copy word line 134 for low level, word line enable signal 158 is low level.
In the time of write operation, local clock 144 is high level, and RS-trigger is in SM set mode.Because local clock 144 is high level, the output 155 of RS-trigger and local clock through with door 156 with after, copy word line 134 for high level, word line enable signal 158 is high level.Copy word line 134 effectively make as in Fig. 2, copy r/w cell 106 copy write " 0 " operation.Write " 0 " EO during when copying, write marking signal 136 and become high level.RS-trigger output 155 becomes low level, and RS-trigger enters reset mode.The output 155 of RS-trigger and local clock through with door 156 with after, copy word line 134 and become low level, word line enable signal 158 becomes low level.
Claims (7)
1. one kind is applicable to the duplicate circuit of writing of static RAM, it is characterized in that, comprise copy word linear load, copy bit-line load, copy bit line selector switch and copy write driver, write copied cells, state machine, line decoder, storage array, control circuit and pre-decode device, bit line selector switch and sense amplifier and imput output circuit;
Copy word linear load by copying word line (DWL) connect state machine, writing copied cells and copy bit line selector switch and copy write driver;
Copy bit-line load and write copied cells by copying bit line (DBL) connection, and copy bit line selector switch and copy write driver;
Write copied cells by having write marking signal line (WR_DONE) connect state machine;
State machine connects line decoder by word line enable (WL_EN), and state machine also connects control circuit and pre-decode device by local clock (LCLK);
Line decoder is connected storage array and is copied bit-line load by many word lines (WL);
Storage array is also by multiple bit lines (BL) Connection-copy word linear load, bit line selector switch and sense amplifier and imput output circuit.
2. the duplicate circuit of writing that is applicable to static RAM as claimed in claim 1, is characterized in that, described in copy bit line selector switch and copy write driver, bit line selector switch and write driver while simulating normal write operation.
3. the duplicate circuit of writing that is applicable to static RAM as claimed in claim 1, is characterized in that, described in write copied cells, the storage unit of being rewritten while simulating normal write operation.
4. the duplicate circuit of writing that is applicable to static RAM as claimed in claim 1, is characterized in that, described state machine, for normal write operation provides state conversion between starting and finishing.
5. the duplicate circuit of writing that is applicable to static RAM as claimed in claim 1, is characterized in that, writes copied cells by NMOS transmission gate (131), reset PMOS transistor (135) and phase inverter (137) composition; The grid end of reset PMOS transistor (135) connects VSS; The grid Connection-copy word line of NMOS transmission gate (131), source electrode Connection-copy bit line, drain electrode connects memory node; The source electrode of reset PMOS transistor (135) meets VDD, and grid connects VSS, and drain electrode connects the input end of memory node (133) and phase inverter (137), and the output terminal of phase inverter (137) connects has write marking signal line.
6. the duplicate circuit of writing that is applicable to static RAM as claimed in claim 1, it is characterized in that, copy bit line selector switch and copy write driver and comprise and copy precharge PMOS pipe (141), copy bit line selector switch NMOS pipe (142) and copy write driver NMOS and manage (144); The grid termination VDD that copies write driver NMOS pipe (144), source meets VSS, and drain electrode connects and copies write bit line; Copy the grid of word line Connection-copy bit line selector switch NMOS pipe (142), the source electrode that copies precharge PMOS pipe (141) connects VDD, copy the grid Connection-copy bit line of precharge PMOS pipe (141) and copy bit line selector switch NMOS the drain electrode of managing (142), copy the source electrode Connection-copy word line of bit line selector switch NMOS pipe (142).
7. the duplicate circuit of writing that is applicable to static RAM as claimed in claim 1, is characterized in that, state machine is made up of with door (156) and impact damper (157) phase inverter (151), the first rejection gate (152), the second rejection gate (153); Local clock connects the input end of phase inverter (151), the input end of phase inverter (151) connects an input end of the first rejection gate (152), the output terminal of the first rejection gate (152) is connected to an input end of the second rejection gate (153), another input end of the second rejection gate (153) connects has write marking signal line, the output terminal of the second rejection gate (153) connects input end of rejection gate (154) and an input end with door (156), is connected local clock with another input end of door (156); Be connected the input end of impact damper (157) with the output terminal of door (156) and copy word line, the output terminal connective word line enable signal of impact damper (157).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420152049.4U CN203799670U (en) | 2014-03-31 | 2014-03-31 | Write copy circuit applicable to static RAM (random access memory) |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420152049.4U CN203799670U (en) | 2014-03-31 | 2014-03-31 | Write copy circuit applicable to static RAM (random access memory) |
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| CN203799670U true CN203799670U (en) | 2014-08-27 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871461A (en) * | 2014-03-31 | 2014-06-18 | 西安华芯半导体有限公司 | Copy-on-write circuit suitable for static random access memory |
| CN105577150A (en) * | 2014-10-17 | 2016-05-11 | 円星科技股份有限公司 | Pulse wave width adjusting device |
| CN105679362A (en) * | 2016-03-31 | 2016-06-15 | 西安紫光国芯半导体有限公司 | Copy-on-write circuit applicable to static random access memory |
| CN105577150B (en) * | 2014-10-17 | 2018-08-31 | 円星科技股份有限公司 | Pulse bandwidth regulating device |
| CN112712834A (en) * | 2019-10-25 | 2021-04-27 | 长鑫存储技术(上海)有限公司 | Write operation circuit, semiconductor memory and write operation method |
-
2014
- 2014-03-31 CN CN201420152049.4U patent/CN203799670U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871461A (en) * | 2014-03-31 | 2014-06-18 | 西安华芯半导体有限公司 | Copy-on-write circuit suitable for static random access memory |
| CN103871461B (en) * | 2014-03-31 | 2016-09-14 | 西安紫光国芯半导体有限公司 | A kind of be applicable to SRAM write duplicate circuit |
| CN105577150A (en) * | 2014-10-17 | 2016-05-11 | 円星科技股份有限公司 | Pulse wave width adjusting device |
| CN105577150B (en) * | 2014-10-17 | 2018-08-31 | 円星科技股份有限公司 | Pulse bandwidth regulating device |
| CN105679362A (en) * | 2016-03-31 | 2016-06-15 | 西安紫光国芯半导体有限公司 | Copy-on-write circuit applicable to static random access memory |
| CN105679362B (en) * | 2016-03-31 | 2018-08-21 | 西安紫光国芯半导体有限公司 | It is a kind of to write duplicate circuit suitable for Static RAM |
| CN112712834A (en) * | 2019-10-25 | 2021-04-27 | 长鑫存储技术(上海)有限公司 | Write operation circuit, semiconductor memory and write operation method |
| WO2021077773A1 (en) * | 2019-10-25 | 2021-04-29 | 长鑫存储技术有限公司 | Write operation circuit, semiconductor memory, and write operation method |
| US11244709B2 (en) | 2019-10-25 | 2022-02-08 | Changxin Memory Technologies, Inc. | Write operation circuit, semiconductor memory, and write operation method |
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