CN203799668U - Static random access memory as well as bit line precharge self-timing circuit - Google Patents
Static random access memory as well as bit line precharge self-timing circuit Download PDFInfo
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Abstract
The utility model provides a static random access memory as well as a bit line precharge self-timing circuit. A replication unit simulates load on a normal bit line; a replication bit line precharge circuit simulates the precharge circuit of the normal bit line for precharging and resetting operation for the replication bit line; a state machine circuit is used for controlling the station conversion of beginning and ending of the precharge operation of the replication bit line and generating a self-timing signal for the precharge operation of the normal bit line. The circuit provides accurate self-timing for the precharge operation of bit lines for the static random access memory at different technology voltage temperatures by simulating the precharge process of the normal bit line. Compared with the traditional bit line precharge signal generated based on inverter chain time delay, the circuit has a better capability of resisting technology voltage temperature deviation.
Description
[technical field]
The utility model relates to static RAM design field, particularly a kind of static RAM and bit line precharge self-timing circuit thereof.
[background technology]
According to International Technology Roadmap for Semiconductors (ITRS) prediction, the area of static RAM, by increasing, by 2015, will account for the more than 94% of whole SOC (system on a chip) (SOC) area.Along with the continuous evolution of technology, constantly the dwindling of dimensions of semiconductor devices, local and overall process deviation, the performance to integrated circuit, the impact that reliability causes is increasing.
Refer to shown in Fig. 1, Fig. 1 is typical static random access memory data path schematic diagram.This typical data path comprises bit line precharge and equalizing circuit, storage unit, sense amplifier and write driver.
Precharge and equalizing circuit consist of PMOS transistor 101,102,103.The phase inverter 105,107 that storage unit is coupled by pair of cross and NMOS transfer tube 104,106 form.Sense amplifier and write driver 108 are as shown in Figure 1.
Before the read-write operation of static RAM starts, must pairs of bit line 111 (BL) and anti-112 (BLB) of bit line carry out precharge operation, make it reach bit line pre-charge level (being VDD in present principles figure).During bit line precharge operation, word line 110 (WL) is closed, and storage unit is in Holdover mode.Precharging signal 109 (PRE_N) is (Low level effective) effectively, in PMOS pipe 101,102 one of them meeting pairs of bit line 111 (BL) and anti-112 (BLB) of bit line, is the charging of low level one end, makes its level draw high pre-charge level.The time of precharge is to determine the effective time of precharging signal 109 (PRE_N).
After precharge operation completes, precharging signal 109 (PRE_N) invalid, according to word line 110 (WL) decode results and sense amplifier, enable the value that 113 (SAE) and write driver enable 114 (WE), corresponding storage unit is carried out to read or write, and the value that data writing 115 (D) is written in corresponding storage unit or storage unit appears at sense data 116 (Q) end.
Refer to shown in Fig. 2, Fig. 2 is that the bit line precharging signal based on chain of inverters time delay produces circuit theory diagrams.This circuit consists of chain of inverters 204 and two input nand gates 205.Chain of inverters consists of odd number phase inverter 201～203.The negative edge of the bit line precharging signal 109 (PRE_N) that this circuit produces is determined by the rising edge of local clock 206 (LCLK) and the high to Low propagation delay of two input nand gates 205, negative edge determines by the propagation delay from high to low of chain of inverters 204 and the propagation delay from low to high of two input nand gates 205, and pulse width is by the propagation delay from high to low of reverser chain 204.By adjusting the number (assurance odd number) of phase inverter in chain of inverters 204, can obtain the bit line precharging signal 109 (PRE_N) that pulse width is different.
As shown in Figure 2, traditional precharging signal producing based on chain of inverters time delay, more responsive for process voltage temperature (PVT) environment, therefore when design, need to reserve many allowances, read and write access time and the minimum clock cycle of static memory are had to negative effect.Therefore, designing a precharging signal self-timing circuit for process voltage temperature-insensitive is highly significant.
[utility model content]
The purpose of this utility model is to propose a kind of static RAM and bit line precharge self-timing circuit thereof, this bit line precharge self-timing circuit is by the pre-charge process of the normal bit line of simulation, for the bit line precharge operation of static RAM under different process voltage temperature provides accurate self-timing.
To achieve these goals, the utility model adopts following technical scheme:
A static RAM, comprises code translator, storage array, copied cells, control circuit and pre-decode device, bit line precharge and equalizing circuit, copies bit-line pre-charge circuit, state machine circuit and sense amplifier and write driver;
Code translator connects storage array by many word lines, and code translator also connects control circuit and pre-decode device by many pre-decode device outputs;
Storage array connects bit line precharge and equalizing circuit and sense amplifier and write driver by multiple bit lines;
Copied cells is by copying bit line Connection-copy bit-line pre-charge circuit and state machine circuit;
Control circuit and pre-decode device are by local clock connect state machine circuit; Control circuit also enables to enable to be connected sense amplifier and write driver with write driver by sense amplifier with pre-decode device;
Bit line precharge and equalizing circuit are by copying precharging signal connect state machine circuit and copying bit-line pre-charge circuit, and bit line precharge and equalizing circuit are also by bit line precharging signal connect state machine circuit.
The utility model further improves and is: described copied cells, simulate the load on normal bit line, and for copying bit line, provide load.
The utility model further improves and is: described in copy bit-line pre-charge circuit, simulate the precharging circuit of normal bit line, to copying bit line, carry out precharge and reset operation.
The utility model further improves and is: described state machine circuit, and control and copy the beginning of bit line precharge operation and the conversion of the state of end, for normal bit line precharge operation produces self-timing signal.
The utility model further improves and is: copied cells is by N and be connected in the sub-copied cells copying on bit line and form; Sub-copied cells comprises trombone slide and NMOS access pipe under the upper trombone slide of PMOS, NMOS; The source electrode of the upper trombone slide of PMOS meets VDD, and grid meets VSS; Under NMOS, the grid of trombone slide meets VSS, source ground, and drain electrode connects the source electrode of NMOS access pipe, the drain electrode Connection-copy bit line of NMOS access pipe, the grid of NMOS access pipe meets VSS; The normal memory cell of sub-copied cells simulation when Holdover mode, provides load for copying bit line.
The utility model further improves and is: copy bit-line pre-charge circuit and form by copying bit line precharge PMOS transistor and copying bit line reset NMOS pipe; The grid of the transistorized grid Connection-copy of PMOS bit line precharging signal and NMOS pipe, the transistorized source electrode of PMOS meets VDD, the drain electrode of PMOS transistorized drain electrode Connection-copy bit line and NMOS pipe, the source ground of NMOS pipe; When copying bit line precharging signal and be low level, copy bit line precharge PMOS transistor and open, copy bit line reset NMOS pipe and close, copy bit line precharge PMOS transistor to copying bit line charging; When copying bit line precharging signal and be high level, copy bit line precharge PMOS transistor and close, copy bit line reset NMOS pipe and open, copy bit line reset NMOS pipe to copying bit line discharges, be reset to low level.
The utility model further improves and is: state machine is comprised of phase inverter, the first rejection gate, the second rejection gate, Sheffer stroke gate and impact damper; Local clock LCLK connects the input end of phase inverter and the first input end of Sheffer stroke gate, the output terminal of phase inverter connects the first input end of the first rejection gate, the output terminal of the first rejection gate connects the first input end of the second rejection gate, copies the second input end that bit line connects the second rejection gate; The output terminal of the second rejection gate connects the second input end of the first rejection gate and the second input end of Sheffer stroke gate; The output terminal output of Sheffer stroke gate copies bit line precharging signal and connects the input end of impact damper, the output terminal output bit-line precharging signal of impact damper; The first rejection gate and the second rejection gate form RS-trigger.
A kind of bit line precharge self-timing circuit of static RAM, this bit line precharge self-timing circuit is by the pre-charge process of the normal bit line of simulation, for the bit line precharge operation of static RAM under different process voltage temperature provides accurate self-timing.
A bit line precharge self-timing circuit for static RAM, comprises copied cells, copies bit-line pre-charge circuit and state machine circuit; Copied cells is by copying bit line Connection-copy bit-line pre-charge circuit and state machine circuit; State machine circuit connects control circuit and the pre-decode device of static RAM by local clock, state machine circuit also connects bit line precharge and equalizing circuit and copies bit-line pre-charge circuit by copying precharging signal, and state machine circuit also connects bit line precharge and equalizing circuit by bit line precharging signal;
Copied cells is by N and be connected in the sub-copied cells copying on bit line and form; Sub-copied cells comprises trombone slide and NMOS access pipe under the upper trombone slide of PMOS, NMOS; The source electrode of the upper trombone slide of PMOS meets VDD, and grid meets VSS; Under NMOS, the grid of trombone slide meets VSS, source ground, and drain electrode connects the source electrode of NMOS access pipe, the drain electrode Connection-copy bit line of NMOS access pipe, the grid of NMOS access pipe meets VSS; The normal memory cell of sub-copied cells simulation when Holdover mode, provides load for copying bit line;
Copying bit-line pre-charge circuit forms by copying bit line precharge PMOS transistor and copying bit line reset NMOS pipe; The grid of the transistorized grid Connection-copy of PMOS bit line precharging signal and NMOS pipe, the transistorized source electrode of PMOS meets VDD, the drain electrode of PMOS transistorized drain electrode Connection-copy bit line and NMOS pipe, the source ground of NMOS pipe; When copying bit line precharging signal and be low level, copy bit line precharge PMOS transistor and open, copy bit line reset NMOS pipe and close, copy bit line precharge PMOS transistor to copying bit line charging; When copying bit line precharging signal and be high level, copy bit line precharge PMOS transistor and close, copy bit line reset NMOS pipe and open, copy bit line reset NMOS pipe to copying bit line discharges, be reset to low level;
State machine is comprised of phase inverter, the first rejection gate, the second rejection gate, Sheffer stroke gate and impact damper; Local clock LCLK connects the input end of phase inverter and the first input end of Sheffer stroke gate, the output terminal of phase inverter connects the first input end of the first rejection gate, the output terminal of the first rejection gate connects the first input end of the second rejection gate, copies the second input end that bit line connects the second rejection gate; The output terminal of the second rejection gate connects the second input end of the first rejection gate and the second input end of Sheffer stroke gate; The output terminal output of Sheffer stroke gate copies bit line precharging signal and connects the input end of impact damper, the output terminal output bit-line precharging signal of impact damper; The first rejection gate and the second rejection gate form RS-trigger.
With respect to prior art, the utlity model has following advantage: this circuit is by the pre-charge process of the normal bit line of simulation, for the bit line precharge operation of static RAM under different process voltage temperature provides accurate self-timing.Traditional circuit based on chain of inverters time delay generation precharging signal, more responsive for process voltage temperature (PVT) environment, therefore when design, need to reserve many allowances, read and write access time and the minimum clock cycle of static memory are had to negative effect.Compare with traditional method based on chain of inverters time delay generation bit line precharging signal, this circuit has the ability of better anti-process voltage temperature deviation.
[accompanying drawing explanation]
Fig. 1 is typical static RAM data path schematic diagram.
Fig. 2 is that the bit line precharging signal based on chain of inverters time delay produces circuit theory diagrams.
Fig. 3 is a static RAM instance graph of implementing according to the utility model.
Fig. 4 is the design concept figure of copied cells.
Fig. 5 is for copying bit-line pre-charge circuit design concept figure.
Fig. 6 is state machine circuit design concept figure.
Fig. 7 is the oscillogram of main signal in example illustrated.
[embodiment]
Below in conjunction with accompanying drawing, embodiment of the present utility model is described further.
As shown in Figure 3, Fig. 3 is a static RAM example of implementing according to the utility model.This static RAM comprises code translator 301, storage array 302, copied cells 303, control circuit and pre-decode device 304, bit line precharge and equalizing circuit 305, copies bit-line pre-charge circuit 306, state machine circuit 307 and sense amplifier and write driver 308.
Code translator 301 connects storage array 302 by many word lines (WL) 309, and code translator 301 also connects control circuit and pre-decode device 304 by many pre-decode device outputs (PRE_DEC) 312.
Storage array 302 also connects bit line precharge and equalizing circuit 305 and sense amplifier and write driver 308 by multiple bit lines (BL) 310.
Copied cells 303 is by copying bit line (DBL) 311 Connection-copy bit-line pre-charge circuits 306 and state machine circuit 307.
Control circuit and pre-decode device 304 are also by local clock (LCLK) 315 connect state machine circuit 307; Control circuit and pre-decode device 304 also enable (SAE) 316 by sense amplifier and enable (WE) 317 with write driver and be connected sense amplifier and write driver 308.
Bit line precharge and equalizing circuit 305 are by copying precharging signal (DPRE_N) 313 connect state machine circuit 307 and copying bit-line pre-charge circuit 306, and bit line precharge and equalizing circuit 305 are also by bit line precharging signal (PRE_N) 314 connect state machine circuit 307.
Refer to main signal oscillogram in Fig. 7 example illustrated, the utility model static RAM specific works principle is as follows:
The rising edge of clock 318 (CLK) externally, control circuit and code translator 304 produce local clocks 315 (LCLK).At the rising edge of local clock 315 (LCLK), trigger state machine circuit 307, make to copy the bit line precharging signal 314 (PRE_N) effective (Low level effective) after bit line precharging signal 313 (DPRE_N) and driving thereof.At the negative edge that copies bit line precharging signal 313 (DPRE_N), copy 306 pairs of bit-line pre-charge circuits and copy bit line 311 (DBL) charging, copy bit line 311 (DBL) and started to draw high by low level.At the negative edge of bit line precharging signal 314 (PRE_N), bit line precharge is carried out precharge and balanced with 305 pairs of normal bit lines 310 of equalizing circuit (BL), in normal bit line 310 (BL), for low level one end, starts to draw high.At the rising edge that copies bit line 311 (DBL), 307 resets of triggering state machine circuit, make to copy bit line precharging signal 313 (DPRE_N) and bit line precharging signal 314 (PRE_N) is invalid.At the rising edge that copies bit line precharging signal 313 (DPRE_N), copy 306 pairs of bit-line pre-charge circuits and copy bit line 311 (DBL) electric discharge, be reset to low level.At the rising edge of bit line precharging signal 314 (PRE_N), bit line 310 (BL) is floating empty, and bit line precharge operation finishes.
The sense amplifier producing according to word line 309 (WL) decode results of code translator 310 and control circuit and pre-decode device 304 enables the value that 316 (SAE) and write driver enable 317 (WE), corresponding storage unit in 308 pairs of storage arrays 302 of sense amplifier is carried out read or write, data writing 319 (D) is written into corresponding storage unit, or the value in storage unit appears at sense data 319 (Q) end.
Refer to Fig. 4, Fig. 4 is the design concept figure of copied cells 303.Copied cells 303 is by N and be connected in the sub-copied cells 401～402 copying on bit line 311 (DBL) and form.The schematic diagram of sub-copied cells 401～402, as shown in 403, comprises trombone slide 406 and NMOS access pipe 405 under the upper trombone slide 404 of PMOS, NMOS.Upper trombone slide in the size of transistor 404～406 and normal memory unit, lower trombone slide, accesses the measure-alike of pipe, and it respectively holds level configuration as shown in Figure 4: the source electrode of the upper trombone slide 404 of PMOS meets VDD, and grid meets VSS; Under NMOS, the grid of trombone slide 406 meets VSS, source ground, and drain electrode connects the source electrode of NMOS access pipe 405, the drain electrode Connection-copy bit line 311 (DBL) of NMOS access pipe 405, the grid of NMOS access pipe 405 meets VSS.The normal memory cell of sub-copied cells 403 simulations when Holdover mode, provides load for copying bit line 311.
Refer to Fig. 5, Fig. 5 is for copying bit-line pre-charge circuit 306 design concept figure.Copying bit-line pre-charge circuit 306 forms by copying bit line precharge PMOS transistor 501 and copying bit line reset NMOS pipe 502.The grid of grid Connection-copy bit line precharging signal 313 (DPRE_N) of PMOS transistor 501 and NMOS pipe 502, the source electrode of PMOS transistor 501 meets VDD, the drain electrode of the drain electrode Connection-copy bit line 311 (DBL) of PMOS transistor 501 and NMOS pipe 502, the source ground of NMOS pipe 502.When copying bit line precharging signal 313 (DPRE_N) for low level, copying bit line precharge PMOS transistor 501 opens, with copy bit line reset NMOS pipe 502 and close, copy 501 pairs, bit line precharge PMOS transistor and copy bit line 311 (DBL) charging; When copying bit line precharging signal 313 (DPRE_N) for high level, copying bit line precharge PMOS transistor 501 closes, with copy bit line reset NMOS pipe 502 and open, and copy 502 pairs of bit line reset NMOS pipes and copy bit line 311 (DBL) electric discharge, be reset to low level.
Refer to Fig. 6, Fig. 6 is state machine circuit 307 design concept figure.Refer to Fig. 5, Fig. 5 is state machine circuit design concept figure.This state machine is comprised of phase inverter 601, the first rejection gate 602, the second rejection gate 603, Sheffer stroke gate 604 and impact damper 605.Local clock LCLK connects the input end of phase inverter 601 and the first input end of Sheffer stroke gate 604, the output terminal of phase inverter 601 connects the first input end of the first rejection gate 602, the output terminal of the first rejection gate 602 connects the first input end of the second rejection gate 603, copies the second input end of bit line 311 (DBL) the second rejection gate 603; The output terminal of the second rejection gate 603 connects the second input end of the first rejection gate 602 and the second input end of Sheffer stroke gate 604; The output terminal output of Sheffer stroke gate 604 copies bit line precharging signal 313 (DPRE_N) and connects the input end of impact damper 605, the output terminal output bit-line precharging signal (PRE_N) 314 of impact damper 605.Wherein the output 608 of the first rejection gate 602 is connected to an input end of the second rejection gate 603, and the output 610 of the second rejection gate 603 has been connected to an input end of the first rejection gate 602, and two rejection gates that so connect have formed a simple R S-trigger.
When local clock 315 (LCLK) is low level, RS-trigger is in set, RS-trigger output 610 is high level, local clock 315 (LCLK) and trigger output 610 are after two input nand gates 604, copying bit line precharging signal 313 (DPRE_N) is high level, and its bit line precharging signal 314 (PRE_N) after impact damper 605 is also high level.
Rising edge as local clock 315 (LCLK), RS-triggers and has a high regard for so in SM set mode, RS-trigger output 610 is high level, local clock 315 (LCLK) and trigger output 610 are after two input nand gates 604, copy bit line precharging signal 313 (DPRE_N) for low level, its bit line precharging signal 314 (PRE_N) after impact damper 605 is also low level.
At the rising edge that copies bit line 311 (DBL), RS-trigger reset, RS-trigger output 610 is low level, local clock 315 (LCLK) and trigger output 610 are after two input nand gates 604, copying bit line precharging signal 313 (DPRE_N) is high level, and its bit line precharging signal 314 (PRE_N) after impact damper 605 is also high level.
Refer to Fig. 7, Fig. 7 is the oscillogram of main signal in example illustrated.At the rising edge of local clock (LCLK), copy bit line precharging signal (DPRE_N) and start to drag down.At the negative edge that copies bit line precharging signal (DPRE_N), copy bit line DBL and start to draw high, bit line precharging signal (PRE_N) starts to drag down.At the negative edge of bit line precharging signal (PRE_N), bit line BL starts to draw high.At the rising edge that copies bit line DBL, copy bit line precharging signal (DPRE_N) and start to draw high.At the rising edge that copies bit line precharging signal (DPRE_N), bit line precharging signal (PRE_N) starts to draw high, and copies bit line DBL and starts to drag down.
Claims (8)
1. a static RAM, it is characterized in that, comprise code translator, storage array, copied cells, control circuit and pre-decode device, bit line precharge and equalizing circuit, copy bit-line pre-charge circuit, state machine circuit and sense amplifier and write driver;
Code translator connects storage array by many word lines (WL), and code translator also connects control circuit and pre-decode device by many pre-decode device outputs (PRE_DEC);
Storage array connects bit line precharge and equalizing circuit and sense amplifier and write driver by multiple bit lines (BL);
Copied cells is by copying bit line (DBL) Connection-copy bit-line pre-charge circuit and state machine circuit;
Control circuit and pre-decode device are by local clock (LCLK) connect state machine circuit; Control circuit and pre-decode device also enable (SAE) by sense amplifier and enable (WE) with write driver and be connected sense amplifier and write driver;
Bit line precharge and equalizing circuit are by copying precharging signal (DPRE_N) connect state machine circuit and copying bit-line pre-charge circuit, and bit line precharge and equalizing circuit are also by bit line precharging signal (PRE_N) connect state machine circuit.
2. static RAM according to claim 1, is characterized in that, described copied cells is simulated the load on normal bit line, for copying bit line, provides load.
3. static RAM according to claim 1, is characterized in that, described in copy bit-line pre-charge circuit, simulate the precharging circuit of normal bit line, to copying bit line, carry out precharge and reset operation.
4. static RAM according to claim 1, is characterized in that, described state machine circuit is controlled and copied the beginning of bit line precharge operation and the conversion of the state of end, for normal bit line precharge operation produces self-timing signal.
5. static RAM according to claim 1, is characterized in that, copied cells is by N and be connected in the sub-copied cells copying on bit line (DBL) and form; Sub-copied cells comprises trombone slide (406) and NMOS access pipe (405) under the upper trombone slide (404) of PMOS, NMOS; The source electrode of the upper trombone slide of PMOS (404) meets VDD, and grid meets VSS; The grid of trombone slide under NMOS (406) meets VSS, source ground, and drain electrode connects the source electrode of NMOS access pipe (405), the drain electrode Connection-copy bit line (DBL) of NMOS access pipe (405), the grid of NMOS access pipe (405) meets VSS; The normal memory cell of sub-copied cells simulation when Holdover mode, provides load for copying bit line (DBL).
6. static RAM according to claim 1, is characterized in that, copies bit-line pre-charge circuit and forms by copying bit line precharge PMOS transistor (501) and copying bit line reset NMOS pipe (502); The grid of the grid Connection-copy bit line precharging signal (DPRE_N) of PMOS transistor (501) and NMOS pipe (502), the source electrode of PMOS transistor (501) meets VDD, the drain electrode of the drain electrode Connection-copy bit line (DBL) of PMOS transistor (501) and NMOS pipe (502), the source ground of NMOS pipe (502); When copying bit line precharging signal (DPRE_N) for low level, copying bit line precharge PMOS transistor (501) opens, copy bit line reset NMOS pipe (502) and close, copy bit line precharge PMOS transistor (501) to copying bit line (DBL) charging; When copying bit line precharging signal (DPRE_N) for high level, copying bit line precharge PMOS transistor (501) closes, copying bit line reset NMOS pipe (502) opens, copy bit line reset NMOS pipe (502) to copying bit line (DBL) electric discharge, be reset to low level.
7. static RAM according to claim 1, is characterized in that, state machine is comprised of phase inverter (601), the first rejection gate (602), the second rejection gate (603), Sheffer stroke gate (604) and impact damper (605); Local clock (LCLK) connects the input end of phase inverter (601) and the first input end of Sheffer stroke gate (604), the output terminal of phase inverter (601) connects the first input end of the first rejection gate (602), the output terminal of the first rejection gate (602) connects the first input end of the second rejection gate (603), copies the second input end that bit line (DBL) connects the second rejection gate (603); The output terminal of the second rejection gate (603) connects the second input end of the first rejection gate (602) and the second input end of Sheffer stroke gate (604); The output terminal output of Sheffer stroke gate (604) copies bit line precharging signal (DPRE_N) and connects the input end of impact damper (605), the output terminal output bit-line precharging signal (PRE_N) of impact damper (605); The first rejection gate (602) and the second rejection gate (603) form RS-trigger.
8. a bit line precharge self-timing circuit for static RAM, is characterized in that, comprises copied cells, copies bit-line pre-charge circuit and state machine circuit;
Copied cells is by copying bit line (DBL) Connection-copy bit-line pre-charge circuit and state machine circuit;
State machine circuit connects control circuit and the pre-decode device of static RAM by local clock, state machine circuit also connects bit line precharge and equalizing circuit and copies bit-line pre-charge circuit by copying precharging signal (DPRE_N), and state machine circuit also connects bit line precharge and equalizing circuit by bit line precharging signal (PRE_N);
Copied cells is by N and be connected in the sub-copied cells copying on bit line (DBL) and form; Sub-copied cells comprises trombone slide (406) and NMOS access pipe (405) under the upper trombone slide (404) of PMOS, NMOS; The source electrode of the upper trombone slide of PMOS (404) meets VDD, and grid meets VSS; The grid of trombone slide under NMOS (406) meets VSS, source ground, and drain electrode connects the source electrode of NMOS access pipe (405), the drain electrode Connection-copy bit line (DBL) of NMOS access pipe (405), the grid of NMOS access pipe (405) meets VSS; The normal memory cell of sub-copied cells simulation when Holdover mode, provides load for copying bit line (DBL);
Copying bit-line pre-charge circuit forms by copying bit line precharge PMOS transistor (501) and copying bit line reset NMOS pipe (502); The grid of the grid Connection-copy bit line precharging signal (DPRE_N) of PMOS transistor (501) and NMOS pipe (502), the source electrode of PMOS transistor (501) meets VDD, the drain electrode of the drain electrode Connection-copy bit line (DBL) of PMOS transistor (501) and NMOS pipe (502), the source ground of NMOS pipe (502); When copying bit line precharging signal (DPRE_N) for low level, copying bit line precharge PMOS transistor (501) opens, copy bit line reset NMOS pipe (502) and close, copy bit line precharge PMOS transistor (501) to copying bit line (DBL) charging; When copying bit line precharging signal (DPRE_N) for high level, copying bit line precharge PMOS transistor (501) closes, copying bit line reset NMOS pipe (502) opens, copy bit line reset NMOS pipe (502) to copying bit line (DBL) electric discharge, be reset to low level;
State machine is comprised of phase inverter (601), the first rejection gate (602), the second rejection gate (603), Sheffer stroke gate (604) and impact damper (605); Local clock (LCLK) connects the input end of phase inverter (601) and the first input end of Sheffer stroke gate (604), the output terminal of phase inverter (601) connects the first input end of the first rejection gate (602), the output terminal of the first rejection gate (602) connects the first input end of the second rejection gate (603), copies the second input end that bit line (DBL) connects the second rejection gate (603); The output terminal of the second rejection gate (603) connects the second input end of the first rejection gate (602) and the second input end of Sheffer stroke gate (604); The output terminal output of Sheffer stroke gate (604) copies bit line precharging signal (DPRE_N) and connects the input end of impact damper (605), the output terminal output bit-line precharging signal (PRE_N) of impact damper (605); The first rejection gate (602) and the second rejection gate (603) form RS-trigger.
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| CN201420152048.XU CN203799668U (en) | 2014-03-31 | 2014-03-31 | Static random access memory as well as bit line precharge self-timing circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943142B (en) * | 2014-03-31 | 2017-02-08 | 西安紫光国芯半导体有限公司 | Static random access memory and bit line pre-charging self-timing circuit thereof |
| CN106683692A (en) * | 2015-11-05 | 2017-05-17 | 三星电子株式会社 | Nonvolatile memory device and method of operating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943142B (en) * | 2014-03-31 | 2017-02-08 | 西安紫光国芯半导体有限公司 | Static random access memory and bit line pre-charging self-timing circuit thereof |
| CN106683692A (en) * | 2015-11-05 | 2017-05-17 | 三星电子株式会社 | Nonvolatile memory device and method of operating the same |
| CN106683692B (en) * | 2015-11-05 | 2021-03-12 | 三星电子株式会社 | Nonvolatile memory device and method of operating the same |
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