CN203799669U - Static RAM (random access memory) for reducing write power consumption by adopting static write technology - Google Patents

Static RAM (random access memory) for reducing write power consumption by adopting static write technology Download PDF

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Publication number
CN203799669U
CN203799669U CN201420151870.4U CN201420151870U CN203799669U CN 203799669 U CN203799669 U CN 203799669U CN 201420151870 U CN201420151870 U CN 201420151870U CN 203799669 U CN203799669 U CN 203799669U
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bit line
write
static
writing
advance
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CN201420151870.4U
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Chinese (zh)
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熊保玉
拜福君
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Xian Unilc Semiconductors Co Ltd
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Xian Sinochip Semiconductors Co Ltd
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Abstract

The utility model provides a static RAM (random access memory) for reducing write power consumption by adopting a static write technology. A bit line precharge electric signal generating circuit detects whether write enable is valid at a rising edge of a clock; if the write enable signal is valid, a bit line precharge electric signal is invalid; or else, the bit line precharge electric signal is valid, namely, the bit line precharge electric signal is invalid in write operation; a static write actuator consists of a phase inverter and a three-state gate; when the write enable is valid, output of the static write actuator actuates the bit line directly. Compared with the traditional static RAM, according to the utility model, the bit line is not required to be subjected to precharge operation in write operation; when the continuous write '0' or write '1' operation occurs, because data kept on the bit line are same with the data required to be written, the bit line does not reverses, thereby saving power consumption. Under the condition that the reversal probability of write data is one second, compared with the traditional design, according to the utility model, the write bit line reversal power consumption is reduced by 50%.

Description

A kind of static RAM that adopts static writing technology to reduce to write power consumption
[technical field]
The utility model relates to static RAM design field, particularly a kind of static RAM that adopts static writing technology to reduce to write power consumption.
[background technology]
According to International Technology Roadmap for Semiconductors (ITRS) prediction, the area of static RAM, by increasing, by 2014, will account for the more than 94% of whole SOC (system on a chip) (SOC) area.Therefore, the power consumption of static RAM, will directly have influence on the power consumption of whole SOC.
Refer to shown in Fig. 1, Fig. 1 is that typical static random access memory is write data path schematic diagram.This typical data path comprises bit line precharge and equalizing circuit, storage unit and write driver.
Bit line precharge and equalizing circuit consist of PMOS transistor 101～103.The phase inverter 105,107 that storage unit is coupled by pair of cross and NMOS transfer tube 104,106 form.Write driver is by NMOS pipe 108,109, and phase inverter 110～112 forms.
Before the write operation of static RAM starts, must pairs of bit line 115(BL) and the anti-118(BLB of bit line) carry out the operation of pre-punching electricity, make it reach bit line pre-charge level (being VDD in present principles figure).When bit line rushes electricity operation in advance, word line 114(WL) to close, storage unit is in Holdover mode.
When the write operation of static RAM, input data 122 are being instead transferred to respectively on write bit line 120 and write bit line anti-121 data and data by reverser 110～112.Write and enable 119 (WE) effectively, nmos pass transistor 108-109 opens, and write bit line 120 and write bit line anti-121 is connected with 118 with bit line 115 respectively.In write bit line 120 and write bit line anti-121, for low level one end, the bit line being attached thereto is discharged to low level by pre-charge level VDD.Word line 114(WL) effective, NMOS transfer tube 104,105 is opened, by memory node 116,117 respectively with bit line 115, bit line anti-118 is connected.If the level of memory node 116,117 is identical with the level of bit line 115 and bit line anti-118 respectively, the level of memory node 116,117 does not change.Otherwise bit line 115 and bit line anti-118 will be rewritten the level of memory node 116,117.
Due to write operation each time all will be first will be for low level one end rushes electricity in advance to VDD in bit line 115 and bit line anti-118, then the one end in bit line 115 and bit line anti-118 is discharged to 0.Suppose that the load capacitance on bit line is C bL, the average inversion energy on bit line is C during write operation each time bLvDD 2, and irrelevant with the probability of writing Data flipping.When writing data and occur continuous " 0 " or " 1 ", when the value of the value keeping when bit line 115 and bit line anti-118 on and write bit line 120 and write bit line anti-121 is identical, pre-punching is electric to be operated and discharge operation means extra energy loss.Therefore, design a kind ofly in such cases, the static RAM that adopts certain technology to write power consumption to reduce is highly significant.
[utility model content]
The purpose of this utility model is to propose a kind of static RAM that adopts static writing technology to reduce to write power consumption, and this storer, when write operation, does not need pairs of bit line to carry out precharge operation, to reduce the unnecessary energy loss of storer.
To achieve these goals, the utility model adopts following technical scheme:
Adopt static writing technology to reduce to write a static RAM for power consumption, comprise that code translator, storage array, control circuit and pre-decode device, bit line rush electric signal generation circuit in advance, bit line rushes electricity and equalizing circuit and static write driver in advance;
Code translator connects storage array by many word lines, and code translator also connects control circuit and pre-decode device by many pre-decode device outputs;
Storage array connects bit line by multiple bit lines and rushes in advance electricity and equalizing circuit and static write driver;
Control circuit also rushes electric signal generation circuit by local clock with writing to enable to be connected in advance with pre-decode device; Control circuit also enables to be connected static write driver by write driver with pre-decode device;
Bit line rushes in advance electricity and equalizing circuit and by bit line, rushes in advance electric signal and be connected and rush in advance electric signal generation circuit.
The utility model further improves and is: bit line rush in advance electric signal produce circuit externally the rising edge of clock detect to write and whether effectively enable, if it is effective to write enable signal, to rush in advance electric signal invalid for bit line; Otherwise bit line precharging signal is effective.
The utility model further improves and is: if it is effective to write enable signal, static write driver is directly connected to input data on bit line; According to the word line decoding result of code translator, on bit line, data are written into corresponding storage unit in storage array.
The utility model further improves and is: when write operation, if data writing equate with the value keeping on bit line, bit line does not overturn; If data writing is contrary with the value keeping on bit line, bit line overturns.
The utility model further improves and is: static write driver comprises phase inverter, the first tristate inverter and the second tristate inverter; The input end of phase inverter is connected data writing with the input end of the second tristate inverter; The output terminal of phase inverter connects the input end of the first tristate inverter, and the output terminal of the first tristate inverter connects bit line, and it is anti-that the output terminal of the second tristate inverter connects bit line; The Enable Pin of the Enable Pin of the first tristate inverter and the second tristate inverter is connected writes enable signal; When writing enable signal when effective, data writing and write data and instead drive the anti-and bit line of bit line through the second tristate inverter and the first tristate inverter respectively; When writing enable signal when invalid, bit line and bit line are anti-floating empty.
The utility model further improves and is: bit line rushes in advance electric signal generation circuit and consists of chain of inverters and three input nand gates; The phase inverter that chain of inverters is connected successively by odd number forms; Local clock connects the input end of chain of inverters and the second input end of three input nand gates, writes the first input end that enable signal connects three input nand gates after phase inverter is anti-phase, and the 3rd input end of three input nand gates connects the output terminal of chain of inverters; The output terminal output bit-line of three input nand gates rushes electric signal in advance; When writing enable signal when effective, bit line precharging signal is invalid; When writing enable signal when invalid, bit line precharging signal is effective.
The utility model further improves and is: being comprised of phase inverter and triple gate of static write driver, when writing, enable when effective, the output of static write driver directly drives bit line.
With respect to prior art, the utlity model has following advantage: when there is continuous writing " 0 " or one writing operation, because the data that keep on bit line are identical with the data that need to write, so bit line do not reverse, thus saving power consumption.The situation that is 1/2nd at the upset probability of writing data, the utility model is compared with traditional design, write bit line upset power-dissipation-reduced 50%.
[accompanying drawing explanation]
Fig. 1 is that typical static RAM is write data path schematic diagram.
Fig. 2 is according to the schematic diagram of a static RAM of the utility model enforcement.
Fig. 3 is the schematic diagram of static write driver.
Fig. 4 is that bit line rushes electric signal generation circuit theory diagrams in advance.
[embodiment]
Below in conjunction with accompanying drawing, embodiment of the present utility model is described further.
As shown in Figure 2, a kind of static RAM example that adopt static writing technology reduce write power consumption of Fig. 2 for implementing according to the utility model.This static RAM comprises that code translator 201, storage array 202, control circuit and pre-decode device 204, bit line rush electric signal generation circuit 205 in advance, bit line rushes electricity and equalizing circuit 206 and static write driver 207 in advance.
Code translator 201 connects storage array 202 by many word lines (WL) 208, and code translator 201 also connects control circuit and pre-decode device 204 by many pre-decode device output lines (PRE_DEC) 210;
Storage array 202 also connects bit line by multiple bit lines (BL) 209 and rushes in advance electricity and equalizing circuit 206 and static write driver 207;
Control circuit and pre-decode device 204 are enabled (WE) 212 and are connected and rush in advance electric signal and produce circuit 205 with writing by local clock (LCLK) 213; Control circuit also enables (WE) 212 by write driver with pre-decode device 204 and is connected sense amplifier and static write driver 207;
Bit line rushes in advance electricity and equalizing circuit 205 and by bit line, rushes in advance electric signal (PRE_N) and be connected and rush in advance electric signal generation circuit;
The utility model is a kind of, and to adopt static writing technology to reduce to write the specific works principle of static RAM of power consumption as follows:
Clock 214(CLK externally) rising edge, control circuit and code translator 204 produce writes enable signal 212(WE) and local clock 213(LCLK).At local clock 213(LCLK) rising edge, bit line rush in advance electric signal produce circuit 205 detect write enable signal 212(WE), if write enable signal 212(WE) invalid, bit line rushes electric signal 211(PRE_N in advance) effectively (Low level effective); Otherwise bit line rushes electric signal 211(PRE_N in advance) invalid.If write enable signal 212(WE) effectively, static write driver 207 will be inputted data 215(D) be directly connected to bit line 209(BL) on.According to the word line 208(WL of code translator 201) decode results, bit line 209(BL) upper data are written in storage array corresponding storage unit in 202.
When write operation, if data writing 215(D) with bit line 209(BL) the upper value keeping equates, bit line 209(BL) do not overturn, inversion energy is 0; If data writing 215(D) with bit line 209(BL) the upper value keeping is contrary, bit line 209(BL) overturn, inversion energy is C bLvDD 2.If data writing 215(D) with bit line 209(BL) probability that equates of the upper value keeping is 50%, during write operation, the mean value of the inversion energy of bit line is 0.5C bLvDD 2.
Refer to Fig. 3, the design concept that Fig. 3 is static write driver.Static write driver 207 comprises phase inverter 303, the first tristate inverter 301 and the second tristate inverter 302.The input end of the input end of phase inverter 303 and the second tristate inverter 302 is connected data writing (D); The output terminal of phase inverter 303 connects the input end of the first tristate inverter 301, and the output terminal of the first tristate inverter 301 connects bit line BL, and the output terminal of the second tristate inverter 302 connects the anti-BLB of bit line; The Enable Pin of the Enable Pin of the first tristate inverter 301 and the second tristate inverter 302 is connected writes enable signal 212(WE).When writing enable signal 212(WE) effectively time (WE=1), data writing (D) and write the anti-307(DB of data) through the second tristate inverter 302 and the first tristate inverter 301, drive bit lines instead (BLB) and bit line (BL) respectively.When writing enable signal 212 when invalid (WE=0), bit line (BL) and bit line anti-(BLB) are floating empty.
Refer to Fig. 4, Fig. 4 is that bit line rushes electric signal generation circuit design principle figure in advance.Bit line rushes in advance electric signal generation circuit 205 and consists of chain of inverters 404 and three input nand gates 405.The phase inverter 401～403 that chain of inverters 404 is connected successively by odd number forms.Local clock LCLK connects the input end of chain of inverters 404 and the second input end of three input nand gates 405, write enable signal (WE) 212 and after phase inverter 406 is anti-phase, connect the first input end of three input nand gates 405, the 3rd input end of three input nand gates 405 connects the output terminal of chain of inverters 404; The output terminal output bit-line of three input nand gates 405 rushes electric signal 211(PRE_N in advance).When writing enable signal when effective (WE=1), be now write operation, bit line precharging signal (PRE_N) invalid (Low level effective); When writing enable signal when invalid (WE=0), be now read operation, bit line precharging signal (PRE_N) is effective; Its pulse width is determined by the time delay of anti-phase chain 404.

Claims (3)

1. a static RAM that adopts static writing technology to reduce to write power consumption, it is characterized in that, comprise that code translator, storage array, control circuit and pre-decode device, bit line rush electric signal generation circuit in advance, bit line rushes electricity and equalizing circuit and static write driver in advance;
Code translator connects storage array by many word lines (WL), and code translator also connects control circuit and pre-decode device by many pre-decode device outputs (PRE_DEC);
Storage array connects bit line by multiple bit lines (BL) and rushes in advance electricity and equalizing circuit and static write driver;
Control circuit and pre-decode device are also enabled (WE) and are connected and rush in advance electric signal and produce circuit with writing by local clock (LCLK); Control circuit also enables (WE) by write driver with pre-decode device and is connected static write driver;
Bit line rushes in advance electricity and equalizing circuit and by bit line, rushes in advance electric signal (PRE_N) and be connected and rush in advance electric signal generation circuit.
2. a kind of static RAM that adopts static writing technology to reduce to write power consumption according to claim 1, is characterized in that, static write driver comprises phase inverter (303), the first tristate inverter (301) and the second tristate inverter (302); The input end of the input end of phase inverter (303) and the second tristate inverter (302) is connected data writing (D); The output terminal of phase inverter (303) connects the input end of the first tristate inverter (301), and the output terminal of the first tristate inverter (301) connects bit line (BL), and the output terminal of the second tristate inverter (302) connects bit line anti-(BLB); The Enable Pin of the Enable Pin of the first tristate inverter (301) and the second tristate inverter (302) is connected writes enable signal (WE); When writing enable signal (WE) effectively time, data writing (D) and write data anti-(DB) respectively through the second tristate inverter (302) and the first tristate inverter (301) driving bit line instead (BLB) and bit line (BL); When writing enable signal (WE) when invalid, bit line (BL) and bit line anti-(BLB) are floating empty.
3. a kind of static RAM that adopts static writing technology to reduce to write power consumption according to claim 1, is characterized in that, bit line rushes in advance electric signal and produces circuit by chain of inverters (404) and three input nand gates (405) formation; The phase inverter that chain of inverters (404) is connected successively by odd number forms; Local clock (LCLK) connects the input end of chain of inverters (404) and the second input end of three input nand gates (405), write the first input end of enable signal (WE) connection three input nand gates (405) after phase inverter (406) is anti-phase, the 3rd input end of three input nand gates (405) connects the output terminal of chain of inverters (404); The output terminal output bit-line of three input nand gates (405) rushes electric signal (PRE_N) in advance; When writing enable signal (WE) effectively time, (PRE_N) is invalid for bit line precharging signal; When writing enable signal (WE) when invalid, bit line precharging signal (PRE_N) is effective.
CN201420151870.4U 2014-03-31 2014-03-31 Static RAM (random access memory) for reducing write power consumption by adopting static write technology Expired - Fee Related CN203799669U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103886896A (en) * 2014-03-31 2014-06-25 西安华芯半导体有限公司 Static random access memory for reducing writing power consumption by adopting static writing technology
CN105761747A (en) * 2016-02-16 2016-07-13 上海华虹宏力半导体制造有限公司 Bit line pre-charge circuit of static random access memory
CN107924694A (en) * 2015-08-10 2018-04-17 国际商业机器公司 Design structure for the pre-charge voltage for reducing static RAM

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103886896A (en) * 2014-03-31 2014-06-25 西安华芯半导体有限公司 Static random access memory for reducing writing power consumption by adopting static writing technology
CN103886896B (en) * 2014-03-31 2016-12-07 西安紫光国芯半导体有限公司 A kind of SRAM using static writing technology reduction to write power consumption
CN107924694A (en) * 2015-08-10 2018-04-17 国际商业机器公司 Design structure for the pre-charge voltage for reducing static RAM
CN107924694B (en) * 2015-08-10 2021-07-09 国际商业机器公司 Memory cell layout for SRAM cells and related design structures
CN105761747A (en) * 2016-02-16 2016-07-13 上海华虹宏力半导体制造有限公司 Bit line pre-charge circuit of static random access memory
CN105761747B (en) * 2016-02-16 2019-01-04 上海华虹宏力半导体制造有限公司 Static RAM bit line precharging circuit

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CP01 Change in the name or title of a patent holder

Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4

Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd.

Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4

Patentee before: Xi'an Sinochip Semiconductors Co., Ltd.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140827

Termination date: 20180331