CN105679362B - It is a kind of to write duplicate circuit suitable for Static RAM - Google Patents
It is a kind of to write duplicate circuit suitable for Static RAM Download PDFInfo
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- CN105679362B CN105679362B CN201610202518.2A CN201610202518A CN105679362B CN 105679362 B CN105679362 B CN 105679362B CN 201610202518 A CN201610202518 A CN 201610202518A CN 105679362 B CN105679362 B CN 105679362B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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Abstract
The present invention is a kind of to write duplicate circuit suitable for Static RAM, including line decoder, storage array, bit-line load, control circuit and Pre-decoder are replicated, replicates wordline load, write copied cells, sense amplifier and write driver, write replicated driver and state machine；Line decoder connects storage array by a plurality of wordline and replicates bit-line load；Storage array is loaded by multiple bit lines Connection-copy wordline, sense amplifier and write driver；Bit-line load connection is replicated to write copied cells and write replicated driver；Control circuit is with Pre-decoder by writing commencing signal connection status machine and writing replicated driver；The input terminal link address of control circuit and Pre-decoder and write enabled/clock；Wordline load is replicated by replicating wordline connection status machine, writing copied cells and write replicated driver；Write copied cells connection status machine；Data and reading data signal are write in sense amplifier and write driver connection；State machine connects line decoder.
Description
Technical field
It is specially a kind of multiple suitable for writing for Static RAM the present invention relates to Static RAM design field
Circuit processed.
Background technology
Static RAM is as the important memory element in integrated circuit, and due to its high-performance, high reliability is low
The advantages that power consumption, is widely used in high-performance calculation device system (CPU), system on chip (SOC), the calculating such as handheld device neck
Domain.
With the continuous evolution of technology, the continuous diminution of dimensions of semiconductor devices, local and global process deviation,
It is influenced to the performance of integrated circuit, caused by reliability increasing.In order to overcome this influence, some are to process voltage temperature
(PVT) insensitive on piece adaptive technique has obtained extensive research and application in recent years.Electricity is replicated by increasing on piece
Road to track PVT environmental changes to entire chip performance, the influence of reliability, and feeds back to control system, certain in adjustment circuit
A little key parameters, make chip operation under current PVT environment the best state of attainable Performance And Reliability.
Write duplicate circuit be exactly it is such a be applied to Static RAM in, for tracking under different PVT environment, production
Can be reliable when raw normal write operation, a kind of skill to the required wordline pulse width of storage unit write access is rapidly completed
Art.As shown in the conventional write copied cells design schematic diagram of Fig. 3.The unit 300 includes cross-linked phase inverter 301,302,
NMOS transmission gates 303,304 and phase inverter 305.This writes storage unit when copied cells simulate normal write operation.
When holding pattern, it is low to replicate wordline 134, and NMOS transmission gates 303 turn off；It is height, NMOS transmission gates 304 to replicate wordline anti-310
It opens, writes copied cells data 313 and be written into " 0 ", write copied cells data anti-312 and be written into " 1 ", write and terminate inverted signal 137
For height.In write operation, it is low to replicate wordline anti-310, and NMOS transmission gates 304 turn off；It is height, NMOS transmission to replicate wordline 134
Door 303 is opened, and is write copied cells data anti-312 and is written into " 0 ", writes copied cells data 313 and be written into " 1 ", and the anti-letter of end is write
Numbers 137 for it is low effectively.From the rising edge for replicating wordline 134, to the lower delay by edge for terminating inverted signal 137 is write, as normally
The write operation required self-timing time.This writes wordline when copied cells 300 only simulate normal write operation, and there is no simulate
Bit line when normal write operation and write driver, and be single-ended write operation when write operation, therefore not enough precisely.
Invention content
For problems of the prior art, the present invention provide it is a kind of suitable for Static RAM write duplication electricity
Road is Static RAM in different process voltage temperature to the write operation of storage unit when by simulating normal write operation
Under write operation accurate self-timing is provided.
The present invention is to be achieved through the following technical solutions：
A kind of duplicate circuit of writing suitable for Static RAM, including line decoder, storage array, duplication bit line are negative
It carries, control circuit and Pre-decoder, the load of duplication wordline write copied cells, sense amplifier and write driver, write duplication driving
Device and state machine；Line decoder is by a plurality of wordline WLs connection storage arrays and replicates bit-line load；Storage array passes through a plurality of
Bit line BLs Connection-copy wordline loads, sense amplifier and write driver；Bit-line load is replicated by replicating bit line and replicating position
The anti-DBL＆DBL_N connections of line write copied cells and write replicated driver；Control circuit is with Pre-decoder by writing commencing signal WR_
START connection status machine and write replicated driver；The input terminal link address of control circuit and Pre-decoder and write it is enabled/when
Clock；Wordline load is replicated by replicating wordline DWL connection status machine, writing copied cells and write replicated driver；Write copied cells
Terminate inverted signal WR_DONE_N and reset signal RST connection status machines by writing；Sense amplifier and write driver pass through input
Data and reading data signal are write in output circuit connection；State machine enables WL_EN connection line decoders by wordline.
Preferably, the storage list for writing copied cells for simulating in the storage array being written over when normal write operation
Member；Word-line signal is replicated caused by user equipment, and drive is write when simulating normal write operation under the driving for writing replicated driver
Dynamic device rewrites the process of the storage unit in storage array, and is provided for state machine at the end of writing copied cells and being written over and write knot
Beam inverted signal.
Preferably, the described copied cells of writing are write end driving phase inverter, are born by cross-linked first and second phase inverter
Phase inverter is carried, the first and second NMOS transfer tubes, first and second resets NMOS transistor composition；First NMOS transfer tubes and first reset
The drain terminal of NMOS transistor respectively through write copied cells data instead with the first phase inverter, the input of load inverter and second connection
The output of phase inverter connects；2nd NMOS transfer tubes and second reset the drain terminal of NMOS transistor respectively through writing copied cells data
With the second phase inverter, writes and terminate that the input of phase inverter is driven to connect with the output of the first phase inverter；It writes and terminates driving phase inverter
Output termination writes end inverted signal；The grid end of first and second NMOS transfer tubes is separately connected duplication wordline；First NMOS transfer tubes
Source Connection-copy bit line is anti-；The source Connection-copy bit line of 2nd NMOS transfer tubes；First and second resets the grid of NMOS transistor
End is separately connected reset signal；First source for resetting NMOS transistor connects supply voltage；Second resets the source of NMOS transistor
End ground connection.
Preferably, the write driver for writing replicated driver for simulating when normal write operation, is arrived writing commencing signal
It when coming, rewrites and replicates bit line, and when replicating wordline arrival, write copied cells.
Preferably, the replicated driver of writing includes third phase inverter and the first and second tristate inverter；Third phase inverter
Input, which connects, writes commencing signal, and output connects the input of the first tristate inverter；The enabled termination supply voltage of first tristate inverter,
Output connects duplication bit line；The input of second tristate inverter, which connects, writes commencing signal, enables termination supply voltage, and output, which connects, replicates position
Line is anti-.
Preferably, the state machine is used to provide duplication wordline to write copied cells, and providing wordline for normal write operation makes
Energy；When writing commencing signal arrival, generates and replicate wordline and wordline enable signal；When simulating write operation completion, terminated by writing
Inverted signal reset state machine, will replicate wordline and wordline enable signal turns off, to generate the required wordline of normal write operation
The self-timing time.
Preferably, the state machine by cross-linked fourth, fifth phase inverter and the six, the seven, eight, nine phase inverters,
One, bi-NMOS transistor and two input nand gates composition；Wherein cross-linked fourth, fifth phase inverter, the six, the seven phase inverters,
And first and second NMOS transistor constitute rest-set flip-flop；Commencing signal is write in the input terminal connection of two input nand gates, another
A input terminal connects with the drain terminal of the output end of the 4th phase inverter, the input terminal of the 5th phase inverter and the second NMOS transistor respectively
It connects, output end connects the input terminal of the eight, the nine phase inverters；The output end Connection-copy word-line signal of 8th phase inverter；9th is anti-
The output end of phase device connects wordline enable signal；Commencing signal is write in the input terminal connection of hex inverter, and output end is believed through resetting
Number connection the first NMOS transistor grid end；The drain terminal of first NMOS transistor is separately connected the input terminal of the 4th phase inverter,
The output end of five phase inverters, source ground connection；End inverted signal is write in the input terminal connection of 7th phase inverter, and output end terminates letter through writing
Number connection the second NMOS transistor grid end；The source of second NMOS transistor is grounded.
Compared with prior art, the present invention has technique effect beneficial below：
The present invention is by replicating bit-line load, duplication wordline loads the load for simulating normal bit lines and wordline respectively.It writes multiple
The storage unit being written over when the normal write operation of unit simulation processed replicates word-line signal caused by user equipment, multiple writing
Under the driving of driver processed, write driver rewrites the process of storage unit when simulating normal write operation, and is writing copied cells quilt
It is provided for state machine at the end of rewriting and writes end inverted signal.Write driver when replicated driver simulates normal write operation is write,
It when writing commencing signal arrival, rewrites and replicates bit line, and when replicating wordline arrival, write copied cells.State machine is to write again
Unit processed, which provides, replicates wordline, and it is enabled to provide wordline for normal write operation.When write operation commencing signal arrives, generates and replicate word
Line and wordline enable signal；When simulating write operation completion, terminate inverted signal reset state machine by writing, and wordline and word will be replicated
Line enable signal turns off, to generate the normal write operation required wordline self-timing time.The present invention is write again by increased
Driver processed, write driver drives bit line when simulating normal write operation, rewrites the process of storage unit；And write operation is both-end
It writes, is more matched with storage unit operation is normally write.Compared with prior art, wordline self-timing time when write operation of the present invention subtracts
It is small by 15%.
Description of the drawings
Fig. 1 is a typical data access schematic diagram of Static RAM described in present example.
Fig. 2 writes duplicate circuit schematic diagram for the Static RAM described in present example.
Fig. 3 is to write copied cells structure principle chart in the prior art.
Fig. 4 is to write copied cells circuit structure schematic diagram described in present example.
Fig. 5 is the duplication bit line selector and duplication write driver circuit structure principle chart described in present example.
Fig. 6 is the state machine circuit structure principle chart described in present example.
Specific implementation mode
With reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
As shown in Figure 1, a typical data path example of Static RAM.The data path includes precharge electricity
Road, storage unit, sense amplifier and write driver.
Pre-charge circuit is made of PMOS transistor 12,13,15.Phase inverter 16 that storage unit is coupled by a pair of cross,
17 and the NMOS transfer tubes 19,20 that are respectively connected with memory node 22,23 constitute.Sensitive amplification in sense amplifier such as Fig. 1
Device 36.Write driver is made of phase inverter 38 and a pair of of tristate inverter 35,37.
In the holding pattern of Static RAM, the wordline 14 of storage unit is invalid (high level is effective), bit line 18
It is maintained at pre-charge level VDD with bit line anti-21.Since NMOS transfer tubes 19,20 are closed at this time, end to end phase inverter 16,
17 form positive feedback, and the data for being stored in memory node 22,23 keep stablizing.
In the read operation of Static RAM, bit line 18 and bit line anti-21 are pre-charged to pre-charge level VDD,
Precharging signal 11 is invalid (low level is effective).Wordline 14 is opened, and bit line 18 and bit line anti-21 are according to the value of memory node 22,23
Electric discharge.The one end of " 0 " is stored in storage unit to corresponding bit line discharges, can make the bit-line levels of the side be less than pre-charge level
VDD then establishes voltage difference between two bit lines 18,21.Voltage on bit line 18 and bit line anti-21 is delivered separately to
The input of sense amplifier 36.When the voltage difference on bit line 18 and bit line anti-21 reaches the detectable sensitive electrical of sense amplifier 36
When pressure differential deltap V, effectively (high level is effective), sense amplifier works sense amplifier enable signal 39, by bit line 18 and bit line
Anti- 21 small signal difference is amplified to full swing signal, is output to output data end 41.
In the write operation of Static RAM, bit line 18 and bit line anti-21 are pre-charged to pre-charge level VDD,
Precharging signal 11 is invalid.Enabled 34 effective (high level is effective) are write, input data 40 passes through reverser 38 and tristate inverter
35,37 are respectively transmitted to data and the counter of data on bit line 18 and bit line anti-21.It is low level in bit line 18 and bit line anti-21
One end the bit line being attached thereto is discharged to low level by pre-charge level VDD.Wordline 14 is effective, NMOS transfer tubes 19,20
Open, by memory node 22,23 respectively with bit line 18, bit line anti-21 be connected.If the level of memory node 22,23 respectively with position
The level of line 18 and bit line anti-21 is identical, then memory node 22, and 23 level does not change.Conversely, bit line 18 and bit line anti-21 will
Rewrite the level of memory node 22,23.
Specifically as shown in Fig. 2, being the duplicate circuit example of the present invention suitable for Static RAM.It is wrapped
It includes line decoder 101, storage array 102, replicate bit-line load 103, control circuit and Pre-decoder 104, replicate wordline load
105, copied cells 106, sense amplifier and write driver 107 are write, writes replicated driver 108 and state machine 109.
When write operation starts, writing data by sense amplifier and write driving in data and reading data signal 111 is write
107 write driver drives bit line 124 in device.According to the address of input, write enabled and clock 110, by control circuit with translate in advance
Commencing signal 144 is write in the code generation of device 104.In the rising edge for writing commencing signal 144, write replicated driver 108 will replicate bit line with
Anti- 132 driving of bit line is replicated to high level and low level.In the rising edge for writing commencing signal 144,109 set of state machine replicates
Word-line signal 134 and wordline enable 158 effective (high level is effective).Replicate word-line signal 134 along wordline load 105 is replicated, even
It is connected to and writes copied cells 106 and write replicated driver 108.Duplication bit line 132, which will be stored in advance in, to be write in copied cells 106
" 0 " value is rewritten as " 1 ".It writes and terminates inverted signal 137 effectively (low level is effective), feed back to state machine 109, state machine 109 is answered
It is invalid with wordline enable signal 158 to replicate wordline 134 for position.The pulse width of wordline enable signal 158 is to replicate wordline 134
Pulse width, energy when being by writing normal write operation caused by process voltage temperature of the copied cells 106 according to current circuit
It is enough reliable, it is rapidly completed to 122 pulse width of the required wordline of storage unit write access.Line decoder 101 makes according to wordline
Energy signal 158 intercepts level wordline signal, generates required pulse word-line signal 122 when normal write operation.Wherein
It replicates bit-line load 103 to be used for simulating the load being connected in regular array on bit line, replicates wordline load 105 and be used for simulating just
The load being connected in normal array in wordline.When replicate wordline 134 it is invalid when, writing the value in copied cells 106 will be reset letter
Number it is reset to " 0 ", while replicating bit line and replicating bit line anti-132 and will also be rewritten respectively to low level and height electricity by write driver
It is flat.
As shown in figure 4, writing the circuit structure schematic diagram of copied cells 106.This writes copied cells 106 by cross-linked anti-
Phase device 400,401, writes end driving phase inverter 403, load inverter 402, and NMOS transfer tubes 404,405 reset NMOS crystal
Pipe 406,407 forms.
Replicate the grid end that wordline 410 connects NMOS transfer tubes 404,405.Write copied cells data anti-411 connect phase inverter 400,
402 input, the drain terminal for being also connected with the output of phase inverter 401, being also connected with NMOS transistor 404,406.Write copied cells data
412 connect the input of phase inverter 401,403, are also connected with the output of phase inverter 400, are also connected with the drain terminal of NMOS transistor 405,407.
Replicate the source of the anti-413 connection NMOS transistor 404 of bit line.Replicate the source that bit line 414 connects NMOS405.Reset signal 415
Connect the grid end of NMOS transistor 406,407.It writes and terminates the output that inverted signal 416 connects phase inverter 403.Supply voltage 417 connects
Connect the source of NMOS transistor 406.Ground 418 connects the source of NMOS transistor 407.
In the pattern of holding, commencing signal 144 is write in vain, replicate wordline 134 in vain (high level is effective), NMOS transfer tubes
404,405 shutdown.Reset signal 415 effectively (high level is effective), open by NMOS transistor 406,407.Due to NMOS transistor
406,406 source connects supply voltage 417 and ground 418 respectively, writes copied cells data anti-411 and writes copied cells data 412
It is kept at " 1 " and " 0 ".It replicates bit line anti-413 and duplication bit line 414 is write replicated driver 108 and is driven to " 1 " and " 0 ".
It writes and terminates inverted signal 137 in vain (low level is effective).
In write operation, commencing signal 144 is write effectively, reset signal 415 is invalid (high level is effective), NMOS transistor
406,406 shutdown.It replicates bit line anti-413 and duplication bit line 414 is write replicated driver 108 and is rewritten as " 0 " and " 1 ".Replicate word
Line 134 effectively (high level is effective), open by NMOS transfer tubes 404,405.Replicated driver 108 is write by replicating bit line anti-413
It will write copied cells data anti-411 with duplication bit line 414 and write copied cells data 412 and be rewritten as " 0 " and " 1 " respectively, simultaneously
It writes and terminates inverted signal 137 effectively (low level is effective).
It writes and terminates inverted signal 137 effectively by reset state machine 104, replicate wordline 134 in vain (high level is effective), NMOS is passed
Defeated pipe 404,405 turns off.It writes copied cells data anti-411 and writes copied cells data 412 and remain " 0 " and " 1 " respectively.
When write commencing signal 144 it is invalid when, reset signal 415 effectively (high level is effective), NMOS transistor 406,407 dozens
It opens.Since the source of NMOS transistor 406,406 connects supply voltage 417 and ground 418 respectively, anti-411 He of copied cells data is write
It writes copied cells data 412 and is rewritten as " 1 " and " 0 " respectively, while writing and terminating inverted signal 137 in vain (low level is effective).It is multiple
Bit line anti-413 processed and duplication bit line 414 are write replicated driver 108 and are rewritten as " 1 " and " 0 ".
As shown in figure 5, to write the circuit structure schematic diagram of replicated driver 108.The circuit includes phase inverter 500 and tri-state
Phase inverter 501,502.The input of phase inverter 500, which connects, writes commencing signal 144, and output connects 510.The input of tristate inverter 501 connects
510, termination supply voltage 511 is enabled, output, which connects, replicates bit line 414.The input of tristate inverter 502, which connects, writes commencing signal 144,
Enabled termination supply voltage 511, output, which connects, replicates bit line anti-413.
In the pattern of holding, commencing signal 144 is write in vain (high level is effective), replicate bit line 413 and replicate 414 quilt of bit line
Tristate inverter 502,501 respectively drives as " 1 " and " 0 ".
In write operation, commencing signal 144 is write effectively (high level is effective), replicate bit line anti-413 and replicate 414 quilt of bit line
Tristate inverter 502,501 respectively drives as " 0 " and " 1 ".
As shown in fig. 6, being 109 circuit structure schematic diagram of state machine.The state machine by cross-linked phase inverter 604,
605, phase inverter 600,601,607,608, NMOS transistor 602,603 and two input nand gates 606 form.Wherein cross-couplings
Phase inverter 604,605, phase inverter 600,601, NMOS transistor 602,603 constitute rest-set flip-flop 609.
Wherein write the input that commencing signal 144 connects the input terminal and two input nand gates 606 of phase inverter 600
End.Reset signal 136 connects the output end of phase inverter 600 and the grid end of NMOS transistor 602.End inverted signal 137 is write to connect
The input terminal of phase inverter 601.It writes end signal 610 and connects the output end of phase inverter 601 and the grid end of NMOS transistor 603.RS
The output anti-611 of trigger 609 connects the input terminal of phase inverter 604 and the output end of phase inverter 605 and NMOS transistor 602
Drain terminal.The output 612 of rest-set flip-flop 609 connects the input terminal of phase inverter 605, the output end of phase inverter 604, NMOS transistor 603
Drain terminal and two input nand gates 606 another input terminal.Ground 613 connects the source of NMOS transistor 602,603.Two input with
The output 614 of NOT gate 606 connects the input terminal of the output end and phase inverter 607,608 of input nand gate 606.Replicate word-line signal
134 connect the output of phase inverter 607.Wordline enable signal 158 connects the output of phase inverter 608.
In the pattern of holding, it is low level to write commencing signal 144, writes and terminates inverted signal 137 as high level.Rest-set flip-flop
609 output 612 is high level, and rest-set flip-flop 609 is in SM set mode.It is low level due to writing commencing signal 144, RS- is touched
Send out device 609 output 612 and write commencing signal 144 pass through two input nand gates 606 and non-post, two input nand gates 606 it is defeated
It is high level to go out 614, and it is low level to replicate wordline 134 and wordline enable signal 158.
In write operation, it is high level to write commencing signal 144, and it is high level, rest-set flip-flop 609 to write end inverted signal 137
In hold mode.It is high level due to writing commencing signal 144, the output 612 of rest-set flip-flop 609 is passed through with commencing signal 144 is write
Two input nand gates 606 and non-post are crossed, the output 614 of two input nand gates 606 is low level, and replicating wordline 134 and wordline makes
Energy signal 158 is high level.
Wordline 134 is replicated effectively so that occurring to replicate write operation as replicated r/w cell 106 in Fig. 2.When duplication write operation knot
Shu Shi, writing end inverted signal 137 becomes low level.The output of rest-set flip-flop 609 612 becomes low level, and rest-set flip-flop 609 enters multiple
Position state.Since the output 612 of rest-set flip-flop 609 is low level, the output 612 of rest-set flip-flop 609 is passed through with commencing signal 144 is write
Two input nand gates 606 and non-post are crossed, the output 614 of two input nand gates 606 is high level, and replicating wordline 134 and wordline makes
Energy signal 158 is low level.
Claims (5)
1. a kind of writing duplicate circuit suitable for Static RAM, which is characterized in that including line decoder (101), storage
Array (102) replicates bit-line load (103), control circuit and Pre-decoder (104), replicates wordline load (105), writes duplication
Unit (106), sense amplifier and write driver (107) write replicated driver (108) and state machine (109)；
Line decoder (101) is by a plurality of wordline WLs connections storage array (102) and replicates bit-line load (103)；
Storage array (102) loads (105) by multiple bit lines BLs Connection-copy wordline, sense amplifier and write driver
(107)；
Duplication bit-line load (103) is connected with the duplication anti-DBL＆DBL_N of bit line by duplication bit line and writes copied cells (106) and write
Replicated driver (108)；
Control circuit is with Pre-decoder (104) by writing commencing signal WR_START connection status machine (109) and writing duplication driving
Device (108)；The input terminal link address of control circuit and Pre-decoder (104) and write enabled/clock (110)；
Wordline load (105) is replicated to drive by replicating wordline DWL connection status machine (109), writing copied cells (106) and writing duplication
Dynamic device (108)；
It writes copied cells (106) and terminates inverted signal WR_DONE_N and reset signal RST connection status machine (109) by writing；
Sense amplifier and write driver (107) write data and reading data signal (111) by imput output circuit connection；
State machine (109) enables WL_EN connection line decoders by wordline；
The storage unit that copied cells (106) are write for simulating in the storage array (102) being written over when normal write operation；
Word-line signal (134) is replicated caused by user equipment (109), under the driving for writing replicated driver (108), simulation is normal
Write driver rewrites the process of the storage unit in storage array (102) when write operation, and is written over writing copied cells (106)
At the end of for state machine (109) offer write terminate inverted signal (137)；
The state machine (109) is used to provide duplication wordline to write copied cells (106), and providing wordline for normal write operation makes
Energy；When writing commencing signal (144) arrival, generates and replicate wordline and wordline enable signal；When simulating write operation completion, by writing
Terminate inverted signal reset state machine, wordline will be replicated and wordline enable signal turns off, it is required to generate normal write operation
The wordline self-timing time.
2. according to claim 1 write duplicate circuit suitable for Static RAM, which is characterized in that described writes
Copied cells (106) write end driving phase inverter (403) by cross-linked first and second phase inverter (400,401), and load is anti-
Phase device (402), the first and second NMOS transfer tubes (404,405), first and second, which resets NMOS transistor (406,407), forms；
The drain terminal of first NMOS transfer tubes (404) and the first reset NMOS transistor (406) is anti-through writing copied cells data respectively
(411) it is connected with the first phase inverter (400), the input of load inverter (402) and the output of the second connection phase inverter (401)；
2nd NMOS transfer tubes (405) and second reset the drain terminal of NMOS transistor (407) respectively through writing copied cells data
(412) with the second phase inverter (401), the output for writing the input and the first phase inverter (400) that terminate driving phase inverter (403) connects
It connects；
It writes the output termination for terminating to drive phase inverter (403) and writes and terminate inverted signal (416)；
The grid end of first and second NMOS transfer tubes (404,405), which is separately connected, replicates wordline (410)；First NMOS transfer tubes (404)
Source Connection-copy bit line it is anti-(413)；The source Connection-copy bit line (414) of 2nd NMOS transfer tubes (405)；
The grid end of first and second reset NMOS transistor (406,407) is separately connected reset signal (415)；First resets NMOS crystalline substances
The source connection supply voltage (417) of body pipe (406)；Second resets the source ground connection (418) of NMOS transistor (407).
3. according to claim 1 write duplicate circuit suitable for Static RAM, which is characterized in that described to write again
Driver (108) processed is used to simulate write driver when normal write operation, when writing commencing signal (144) arrival, rewrites and replicates
Bit line, and when replicating wordline arrival, write copied cells (106).
4. according to claim 1 write duplicate circuit suitable for Static RAM, which is characterized in that described to write again
Driver (108) processed includes third phase inverter (500) and the first and second tristate inverter (501,502)；
The input of third phase inverter (500), which connects, writes commencing signal (144), and output connects the input of the first tristate inverter (501)；
The enabled termination supply voltage (511) of first tristate inverter (501), output, which connects, replicates bit line (414)；
The input of second tristate inverter (502), which connects, writes commencing signal (144), enables termination supply voltage (511), and output connects multiple
Bit line processed is anti-(413).
5. according to claim 1 write duplicate circuit suitable for Static RAM, which is characterized in that the state
Machine (109) by cross-linked fourth, fifth phase inverter (604,605) and the six, the seven, eight, nine phase inverters (600,601,
607,608), the first and second NMOS transistor (602,603) and two input nand gates (606) composition；Wherein cross-linked
Four, five phase inverters (604,605), the six, the seven phase inverters (600,601) and the first and second NMOS transistor (602,603) structure
At rest-set flip-flop (609)；
Commencing signal (144) is write in the input terminal connection of two input nand gates (606), another input terminal is anti-with the 4th respectively
The drain terminal of the output end of phase device (604), the input terminal of the 5th phase inverter (605) and the second NMOS transistor (603) connects, output
The input terminal of end the eight, the nine phase inverters of connection (607,608)；The output end Connection-copy word-line signal of 8th phase inverter (607)
(134)；The output end connection wordline enable signal (158) of 9th phase inverter (608)；
Commencing signal (144) is write in the input terminal connection of hex inverter (600), and output end connects first through reset signal (136)
The grid end of NMOS transistor (602)；
The drain terminal of first NMOS transistor (602) is separately connected the input terminal of the 4th phase inverter (604), the 5th phase inverter (605)
Output end, source be grounded (613)；
The input terminal connection of 7th phase inverter (601), which is write, terminates inverted signal (137), and output end is connected through writing end signal (610)
The grid end of second NMOS transistor (603)；The source ground connection (613) of second NMOS transistor (603).
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| CN103943142A (en) * | 2014-03-31 | 2014-07-23 | 西安华芯半导体有限公司 | Static random access memory and bit line pre-charging self-timing circuit thereof |
| CN203799670U (en) * | 2014-03-31 | 2014-08-27 | 西安华芯半导体有限公司 | Write copy circuit applicable to static RAM (random access memory) |
| CN205487357U (en) * | 2016-03-31 | 2016-08-17 | 西安紫光国芯半导体有限公司 | Write copy circuit applicable to static RAM (random access memory) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103943142A (en) * | 2014-03-31 | 2014-07-23 | 西安华芯半导体有限公司 | Static random access memory and bit line pre-charging self-timing circuit thereof |
| CN203799670U (en) * | 2014-03-31 | 2014-08-27 | 西安华芯半导体有限公司 | Write copy circuit applicable to static RAM (random access memory) |
| CN205487357U (en) * | 2016-03-31 | 2016-08-17 | 西安紫光国芯半导体有限公司 | Write copy circuit applicable to static RAM (random access memory) |
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