TWI423258B - Dual port sram having a higher voltage write-word-line in writing operation - Google Patents

Description

Dual port SRAM having a higher voltage write-word-line in writing operation

The present invention relates to a static random access memory (SRAM) for improving the voltage level of a write word line during a write operation, and more particularly to a leakage current. The utility model can reduce the read interference, improve the read reliability, and can solve the double-click static random access memory which is difficult to write the logic 1 by the double-bit SRAM with a single bit line.

Memory plays an indispensable role in the computer industry. Generally, the memory can be classified into a volatile memory and a non-volatile memory according to whether the data can be saved after the power is turned off, and the volatile memory can be further classified into a dynamic random access memory (DRAM) and Two types of static random access memory (SRAM). Dynamic random access memory (DRAM) has the advantages of small area and low price, but it must be refreshed from time to time to prevent data from being lost due to leakage current, resulting in high speed and power consumption. Missing. Conversely, the operation of the static random access memory (SRAM) is simple and does not require an update operation, so it has the advantages of high speed and low power consumption.

The semiconductor memory devices currently used in mobile electronic devices represented by mobile phones are mainly SRAM. This is due to the small standby current of the SRAM, which is suitable for mobile phones with continuous talk time and continuous standby time.

A static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows of memory cells (a). The plurality of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines, each word line corresponding to a column of a plurality of memory cells; and a plurality of bit line pairs, each bit line pair corresponding to one of the plurality of rows of memory cells, and each bit line pair is A meta-line and a complementary bit line are formed.

Figure 1 is a schematic diagram of a 6T static random access memory (SRAM) cell. The PMOS transistors P1 and P2 are called load transistors, and M1 and M2 are called drive transistors. Driving transistor), M3 and M4 are called access transistors, WL is a word line, and BL and BLB are bit lines and complementary bit lines, respectively. ), since the SRAM cell requires 6 transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, the cell ratio) is usually set between 2 and 3, resulting in the presence of Difficulties in high concentration and high prices. The 6T SRAM cell shown in Figure 1 shows the HSPICE transient analysis results during the write operation. As shown in Figure 2, it is modeled using the level 49 model using TSMC 0.35 micron CMOS process parameters. simulation.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line. Compared with the 6T SRAM cell of Figure 1, the 5T static random access memory. The bulk cell has one transistor and one less bit line than the 6T SRAM cell, but the 5T SRAM cell has a problem of writing logic 1 quite difficult. Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is modeled using the level 49 model using TSMC 0.35 micron CMOS process parameters. Simulation, from the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.

Next, we discuss the static random access memory (SRAM) and dual-layer architecture. The 6T static random access memory (SRAM) cell in Figure 1 is a static random access memory (SRAM) crystal. One example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, both reading and writing are achieved through the same pair of bit lines, so that only reading or reading can be performed at the same time. The action of writing, therefore, when designing a dual-static SRAM with simultaneous read and write capabilities, it is necessary to add two access transistors and another pair of bit lines (please refer to Figure 5). a circuit in which WBL and WBLB are write bit line pairs, RBL and RBLB are read bit line pairs, WWL is a write word line, and RWL is a read word line), which makes the memory crystal The area of the cell is greatly increased. If we can simplify the structure of the memory cell, so that one bit line is responsible for the reading action, and the other bit line is responsible for the writing action, then the double-click static random access memory is designed. When you are in the body, the memory cell does not need to add two transistors and another pair of bit lines. The area of the memory cell is much reduced. The reason why the conventional double-squeezing static random access memory cell does not adopt this method is because the problem of writing logic 1 cannot be achieved as described above.

In view of the above, the main object of the present invention is to provide a dual-static static random access memory that improves the voltage level of a write word line during a write operation, which can improve the write character by a write operation. The line voltage level is effective to avoid the problem that it is difficult to write the logic 1 in the double-slot static random access memory cell with a single bit line.

A secondary object of the present invention is to provide a dual-static static random access memory that improves the voltage level of a write word line during a write operation, which can effectively reduce leakage current in standby mode, while reading It can reduce read interference and improve read reliability.

The present invention provides a dual port static random access memory (Dual port SRAM) for improving the voltage level of a write word line during a write operation, which includes a memory array which is composed of a plurality of columns of memories. The unit cell is composed of a plurality of memory cells, each column of memory cells and each row of memory cells each comprising a plurality of memory cells (1); a first bias circuit (2); A second bias circuit (3). The memory cells (1) are connected between a high voltage node (VH) and a low voltage node (VL), and the memory cells (1) are written for a write operation. The power supply voltage (WV _DD ) is supplied to a write word line (WWL), and the level of the write power supply voltage (WV _DD ) is set to at least one high power supply voltage (HV _DD ) plus one Writing the threshold voltage of the select transistor (MWS), and increasing the voltage level of the write word line (WWL) by the write operation to effectively avoid writing the logic 1 is quite difficult; In the standby mode, a low power supply voltage (LV _DD ) is supplied to the high voltage node (VH) and a voltage higher than the ground voltage is supplied to the low voltage node (VL). To effectively reduce the power consumption of the SRAM; further, to set the voltage level of a read word line (RWL) to non-selected to be low during the read operation. Ground voltage (eg -0.5 volts) to effectively reduce read disturb and improve read reliability. As a result, the double-click static random access memory for improving the voltage level of the write word line during the write operation proposed by the present invention can effectively avoid the writing of the double-bit SRAM with a single bit line. Logic 1 is a very difficult problem, and it can also reduce leakage current and read interference and high reliability in standby mode.

According to the above main object, the present invention provides a double-chip static random access memory for increasing the voltage level of a write word line during a write operation, which improves the voltage level of the write word line during the write operation. The double-sound static random access memory system includes a memory array composed of a plurality of memory cells and a plurality of memory cells, each column of memory cells and each row of memory cells. A plurality of memory cells (1) are included; a first bias circuit (2); and a second bias circuit (3).

For the sake of convenience of explanation, the double-chip SRAM memory for increasing the voltage level of the write word line during the write operation shown in FIG. 6 is only one memory cell (1), one write. Word line (WWL), a read word line (RWL), a write bit line (WBL), a read bit line (RBL), a first bias circuit (2) And a second bias circuit (3) is described as an embodiment. The memory cell (1) is connected between a high voltage node (VH) and a low voltage node (VL), and includes a first inverter (by the first PMOS transistor P1 and the first NMOS) a crystal M1 is composed of a second inverter (composed of the second PMOS transistor P2 and the second NMOS transistor M2), a write selection transistor (MWS), and a read selection transistor ( MRS), and an inverting transistor (MINV), wherein the first inverter and the second inverter are connected in an alternating coupling, that is, an output of the first inverter (ie, storage node A) Connected to the input of the second inverter, and the output of the second inverter (ie, the inverting storage node B) is connected to the input of the first inverter, and the output of the first inverter (storage Node A) is used to store the data of the SRAM cell (1), and the output of the second inverter (inverting storage node B) is used to store the inverted data of the SRAM cell (1), the write Selective transistor (MWS) is connected between the storage node (A) and the write bit line (WBL), and the gate is connected to the write word line (WWL); Select one end of the transistor (MRS) The read bit line (RBL) is connected to the inverting transistor (MINV), and the gate is connected to the read word line (RWL); and the inverting transistor (MINV) One end is connected to the read select transistor (MRS), the other end is connected to the low voltage node (VL), and the gate is connected to the inverting storage node (B).

Referring again to FIG. 6, the first bias circuit (2) is composed of a third PMOS transistor (P21), a fourth PMOS transistor (P22), and a third inverter (I23). The source, gate and drain of the third PMOS transistor (P21) are respectively connected to a high power supply voltage (HV _DD ), a first control signal (SAP) and the high voltage node (VH); a source, a gate and a drain of the fourth PMOS transistor (P22) are respectively connected to a low power supply voltage (LV _DD ), an output of the third inverter (I23), and the high voltage node ( VH), and the input of the third inverter (I23) is used to receive the first control signal (SAP). Furthermore, the second bias circuit (3) is composed of a third NMOS transistor (M31) and a fourth NMOS transistor (M32), the source of the third NMOS transistor (M31), The gate and the drain are respectively connected to a ground voltage, a second control signal (SAN) and the low voltage node (VL), and the source of the fourth NMOS transistor (M32) is connected to a ground voltage, and the gate is Connected to the drain and connected to the low voltage node (VL).

It is worth noting here that in order to prevent the sense margin from decreasing, the voltage level of the read word line (RWL) at the nonselected level is set lower than the ground voltage. (eg, -0.5 volts), that is, the read word line (RWL) is set to the high power supply voltage (HV _DD ) during the read operation and low during the read operation. At the voltage level of the ground voltage (for example, -0.5 volts), the write word line (WWL) is set to a level of the write power supply voltage (WV _DD ) during the write operation, the write The level of the incoming power supply voltage (WV _DD ) is set to at least a high power supply voltage (HV _DD ) plus the threshold voltage of the write select transistor (MWS), and outside the write operation The period is set to the ground voltage.

The working principle of the preferred embodiment of the present invention in FIG. 6 is as follows:

(I) active mode

At this time, the first control signal (SAP) is a logic low level, and the second control signal (SAN) is a logic high level, and the logic low level first control signal (SAP) can make the first bias circuit (2) The third PMOS transistor (P21) is ON (on), so that the high power supply voltage (HV _DD ) can be supplied to the high voltage node (VH); and the logic high level second control signal (SAN) can make the first The third NMOS transistor (M31) of the two bias circuits (3) is ON (on), so that the low voltage node (VL) can be pulled down to the ground voltage.

Next, how the present invention of FIG. 6 completes the write operation will be described based on the four write states of the binary random access memory cells.

(1) The storage node (A) originally stores logic 0, but now wants to write logic 0:

Before the write operation occurs (the write word line WWL is the ground voltage), the first NMOS transistor (M1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the high voltage node (VH). ). Since the first NMOS transistor (M1) is turned on, when the write operation is started, the write word line (WWL) is turned from Low (ground voltage) to High (write power supply voltage (WV _DD )). When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M3) (ie, the access transistor), the third NMOS transistor (M3) is turned from OFF (OFF) to ON ( Turn on) At this time, since the write bit line (WBL) is Low (ground voltage), the storage node (A) is discharged, and the logic 0 write operation is completed until the end of the write cycle.

(2) The storage node (A) originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is the ground voltage), the first NMOS transistor (M1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the high voltage node (VH). ). Since the first NMOS transistor (M1) is turned on, when the write operation is started, the write word line (WWL) is turned from Low (ground voltage) to High (write power supply voltage (WV _DD )). When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M3), the third NMOS transistor (M3) is turned from OFF (OFF) to ON (on), at this time because of writing The input bit line (WBL) is High (high power supply voltage HV _DD ), so the storage node (A) is quickly charged; in the storage node (A) charging, the write power supply voltage (WV) _{The level of DD} ) is set to at least the high power supply voltage (HV _DD ) plus the threshold voltage of the write select transistor (MWS), and the write power supply voltage (WV _DD ) is Supply to the write word line (WWL), thus helping the inverting storage node (B) to transition from High (supply voltage Vdd) to Low (ground voltage), when the voltage of the inverting storage node (B) When the level is lowered enough to turn on the first PMOS transistor (P1), the first PMOS transistor (P1) is turned from OFF to ON, and the logic 1 write operation is completed.

(3) The storage node (A) originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor (P1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the voltage node (VH). . When the write word line (WWL) is turned from Low (ground voltage) to High (write power supply voltage (WV _DD )), and the voltage of the write word line (WWL) is greater than the third NMOS transistor At the threshold voltage of (M3), the third NMOS transistor (M3) is turned from OFF (turned) to ON (turned on); at this time, since the write bit line (WBL) is High (high power supply voltage HV _DD ) And because the first PMOS transistor (P1) is still ON, the voltage of the storage node (A) does not change, but is smoothly maintained at the level of the high power supply voltage (HV _DD ) until the end of the write cycle .

(4) The storage node (A) originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor (P1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the voltage node (VH). When the write word line (WWL) is turned from Low (ground voltage) to High (write power supply voltage (WV _DD )), and the voltage of the write word line (WWL) is greater than the third NMOS transistor At the threshold voltage of (M3), the third NMOS transistor (M3) is turned from OFF (OFF) to ON (on), because the write bit line (WBL) is Low (ground voltage) and because of the write The power supply voltage (WV _DD ) is set to at least the high power supply voltage (HV _DD ) plus the threshold voltage of the write select transistor (MWS), so the storage node will be A) A fast discharge completes the write operation of logic 0 until the end of the write cycle.

The preferred embodiment of the present invention, illustrated in Figure 6, then performs the read operation in accordance with the two stored data states of the dual-slide SRAM cell.

(1) Storage node (A) storage logic 0

Before the read operation occurs (the read word line (RWL) is a voltage level lower than the ground voltage, for example, -0.5 volts), the write word line (WWL) is the ground voltage, and the second NMOS transistor (M2) is OFF (off), the second PMOS transistor (P2) is ON (on), and the inverting storage node (B) is High (high power supply voltage HV _DD ). When the read operation starts, the read word line (RWL) is turned from the voltage level lower than the ground voltage to High (high power supply voltage HV _DD ), and when the read word line (RWL) When the voltage is greater than the threshold voltage of the read select transistor (MRS), the read select transistor (MRS) transitions from OFF (turned) to ON (on), at which time the inverted storage node (B) is High. (High power supply voltage HV _DD ), the inverting transistor (MINV) is ON (conducting), so it will be used in the read bit line (RBL), the read select transistor (MRS), and the inverting transistor. A current path is formed between the (MINV) and the ground. This current path reduces the voltage level of the read bit line (RBL), thereby sensing the storage node (A) storing the logic 0 data. And complete the logic 0 read operation.

(2) Storage node (A) storage logic 1

Before the read operation occurs (the read word line (RWL) is a voltage level lower than the ground voltage (for example, -0.5 volts)), the write word line (WWL) is the ground voltage, and the second NMOS is The crystal (M2) is ON (on), the second PMOS transistor (P2) is OFF (off), and the inverting storage node (B) is Low (ground voltage). When the read operation starts, the read word line (RWL) is turned from the voltage level lower than the ground voltage to High (high power supply voltage HV _DD ), and when the read word line (RWL) When the voltage is greater than the threshold voltage of the read select transistor (MRS), the read select transistor (MRS) transitions from OFF (turned) to ON (on), at which time the inverted storage node (B) is Low. (ground voltage), the inverting transistor (MINV) is OFF (off), so it is not in the read bit line (RBL), read select transistor (MRS), inverting transistor (MINV) The current path is formed between the ground and the ground. As a result, the voltage level of the read bit line (RBL) can be smoothly maintained in the High state, thereby sensing the storage node (A) storing the logic 1 data. And complete the logic 1 read action.

In the first embodiment of the present invention shown in FIG. 6, the HSPICE transient analysis simulation result at the time of the write operation is as shown in FIG. 7, which is simulated by the level 49 model and using TSMC 0.35 micron CMOS process parameters. It can be confirmed from the simulation result that the double-chip static random access memory for improving the voltage level of the write word line during the write operation proposed by the present invention can improve the write word line by the write operation. The voltage level is effective to avoid the problem that it is quite difficult to write a logic 1 in a double-slot static random access memory cell with a single bit line.

Finally, how to improve the leakage current of the non-selected double-埠 SRAM cell by reducing the double-slot static random access memory of the write word line voltage level during the write operation proposed by the present invention Current), which achieves the effect of reducing read interference and improving read reliability. During the read operation, the read select transistor (MRS) of the non-selected double-turn SRAM cell is in an OFF state, but there is still leakage current when the read select transistor (MRS) is turned off. The leakage current path is formed between the read bit line (RBL), the read select transistor (MRS), the inverting transistor (MINV), and the ground, and the leakage current path causes read disturb. And reduce read reliability. The present invention connects one end of the inverting transistor (MINV) to the read select transistor (MRS), the other end to the low voltage node (VL), and the gate to the inverting storage node (B) ), although it cannot block the leakage current path of the non-selected SRAM cell, it can still be caused by setting the read word line (RWL) below the ground voltage but higher than the gate-induced drain leakage ( Gate Induced Drain Leakage, GIDL) The voltage level of the current (eg -0.5 volts) to reduce the leakage current of the non-selected double-turn SRAM cell. In fact, the leakage current of the transistor is mainly from the subthreshold current, in the third (A) and 3 (B) drawings of US Pat. No. 6,865,119, March 8, 2005. That is, for the NMOS transistor, the subcritical current when the gate source voltage is -0.1 volt is about 1% of the subcritical current when the gate source voltage is 0 volt, and therefore, by using the readout The word line (RWL) is set lower than the ground voltage but higher than the voltage level at which the gate-induced drain leakage (GIDL) current is generated (eg, -0.5 volts), which can significantly reduce the non-selected double-turn SRAM cell. Leakage current, and can reduce the read interference and improve the read reliability.

(II) Standby mode

At this time, the first control signal (SAP) is a logic high level, and the second control signal (SAN) is a logic low level, and the first control signal (SAP) of the logic high level can make the first bias circuit The third PMOS transistor (P21) in (2) is turned OFF, and the fourth PMOS transistor (P22) is turned ON, so that the low power supply voltage (LV _DD ) can be supplied to the high voltage. a node (VH); and the logic low level of the second control signal (SAN) can cause the third NMOS transistor (M31) in the second bias circuit (3) to be OFF (turned off), since The fourth NMOS transistor (M32) in the bias circuit (3) is still ON, so that the low voltage node (VL) can be maintained at the threshold voltage of the fourth NMOS transistor (M32). quasi.

Next, how to reduce leakage current in the standby mode of the present invention will be described. Please refer to FIG. 8 and FIG. 8 shows the critical leakage current generated by the double-turn SRAM in the standby mode of FIG. 6 (subthreshold leakage). Current) I1, I2, I3, and I4, it is worth noting that the low voltage node (VL) is maintained at a threshold voltage higher than the ground voltage of the fourth NMOS transistor (M32) in the standby mode. The high voltage node (VH) is maintained at a voltage level lower than the low power supply voltage (LV _DD ) of the high power supply voltage (HV _DD ), and the storage node in the double-turn SRAM cell (A) is the logic Low (ground voltage), and the inverting storage node (B) is the logic High (high power supply voltage HV _DD ) as an example to illustrate the critical leakage currents I1, I2, I3 and I4:

(1) Leakage current I1 related to the selected transistor (MWS) flowing through the write

Referring to the prior art of FIG. 5 and the embodiment of the present invention of FIG. 8, since the write word line (WWL) is a ground voltage in the standby mode, the write selection transistor is initially flowed in the standby mode ( The leakage current I1 of MWS has the same leakage current as the prior art of FIG. 5 (the NMOS transistor M3 in the prior art, which is equivalent to the write selection transistor MWS in the embodiment of the present invention) (preset mode initial storage) Node A is the ground voltage), and then the storage node (A) is increased by the ground voltage to the level of the threshold voltage of the fourth NMOS transistor (M32) higher than the ground voltage, during which time the embodiment of the present invention The gate voltage of the write select transistor (MWS) is negative, while the gate voltage of the NMOS transistor (M3) in the prior art is still maintained at 0 volts, and the gate is induced to leak due to the gate (Gate Induced The Drain Leakage (GIDL) effect or the third (A) and 3 (B) diagrams of US Pat. No. 6,865,119, issued March 8, 2005, shows that the leakage current I1 flowing through the write selective transistor (MWS) is Far less than the prior art of Figure 5.

(2) About the leakage current I2 flowing through the first PMOS transistor (P1)

Since the high voltage node (VH) in the standby mode lines with the low power supply voltage (LV _DD) of the voltage level, the low power supply voltage (LV _DD) of the voltage level of the line is less than the high power supply voltage (HV _DD ), because the inverting storage node (B) is at the voltage level of the high power supply voltage (HV _DD ) at the beginning of the standby mode, the gate-induced drain leakage (GIDL) effect and the bungee-induced energy barrier fall. (Drain Induced Barrier Lowering, DIBL) effect, the leakage current I2 flowing through the first PMOS transistor (P1) is much smaller than that of the prior art of FIG. 5 (the PMOS transistor P1 in the prior art is equivalent to the implementation of the present invention) In the example, the first PMOS transistor P1), and then the storage node (B) is reduced by the level of the high power supply voltage (HV _DD ) toward the low power supply voltage (LV _DD ). During the period of the present invention, the gate-source voltage of the first PMOS transistor (P1) still maintains a positive value and the source voltage maintains the voltage level of the low power supply voltage (LV _DD ), and the prior art The gate-source voltage of the PMOS transistor (P1) is maintained at 0 volts and the source voltage is still maintained. The high voltage power supply (HV _DD) of the voltage level, thus according initiator gate drain leakage (the GIDL) effect and drain induced barrier down (the DIBL) effect can be seen, flow through the first PMOS transistor (P1) The leakage current I2 is still smaller than the prior art of FIG.

(3) Leakage current I3 flowing through the second NMOS transistor (M2)

Since the low voltage node (VL) maintains the level of the threshold voltage of the fourth NMOS transistor (M32) in the standby mode, and because the storage node (A) is grounded at the beginning of the standby mode, The extremely induced buckling leakage (GIDL) effect or the leakage current of the second NMOS transistor (M2) can be seen from the figures 3(A) and 3(B) of US Pat. No. 6,865,119, issued March 8, 2005. The I3 system is much smaller than the prior art of FIG. 5 (the NMOS transistor M2 in the prior art is equivalent to the second NMOS transistor M2 in the embodiment of the present invention), and then the storage node (A) is biased by the ground voltage. The level of the threshold voltage of the fourth NMOS transistor (M32) is higher than the ground voltage. During this period, the gate voltage of the second NMOS transistor (M2) is still negative due to the embodiment of the present invention. While the gate-source voltage of the NMOS transistor (M2) in the prior art is maintained at 0 volts, the leakage current I3 flowing through the second NMOS transistor (M2) is still smaller than that of the prior art of FIG.

(4) Leakage current I4 of the selective transistor (MRS) flowing through the reading

Since the read word line (RWL) is set to be lower than the ground voltage in the standby mode but higher than the voltage level at which the gate-induced drain leakage (GIDL) current is generated (for example, -0.5 volts), The phase transistor (MINV) is turned on, so that the source voltage of the read select transistor (MRS) can be fixed at the level of the threshold voltage of the fourth NMOS transistor (M32), thereby causing the gate to be induced according to the gate. The leakage (GIDL) effect or the figures 3(A) and 3(B) of U.S. Patent No. 6,865,119, issued on March 8, 2005, can significantly reduce leakage current flowing through the selective selective transistor (MRS). I4. In contrast, the read word line (RWL) of the NMOS transistor (M6) in the prior art of FIG. 5 is the ground voltage, and the drain of the NMOS transistor (M6) is the high power supply voltage (HV). The voltage level of _DD ) is based on the drain-induced energy barrier (DIBL) effect, and the drain voltage of the higher potential NMOS transistor (M6) increases the leakage current flowing through the NMOS transistor (M6).

From the above analysis, it can be seen that the present invention can effectively reduce leakage current in the standby mode.

The double-static static random access memory for improving the voltage level of the write word line during the write operation proposed by the present invention has the following effects:

(1) Reducing read interference and improving read reliability: due to the double-click SRAM memory for increasing the voltage level of the write word line during the write operation proposed by the present invention, Setting the voltage level of the read word line (RWL) to non-selected is lower than the ground voltage but higher than the voltage level at which the gate-induced drain leakage (GIDL) current is generated (eg, -0.5 volts) As a result, the effect of reducing read interference and improving read reliability can be effectively achieved by greatly reducing the leakage current of the non-selected double-turn SRAM cell.

(2) Low-threshold leakage current: The high-voltage node (VH) system is used in the standby mode when the write-type word line voltage level is increased in the standby mode during the write operation proposed by the present invention. The voltage level of the low power supply voltage (LV _DD ), and the low voltage node (VL) is fixed at the level of the threshold voltage of the fourth NMOS transistor (M32), and the read word line (RWL) The voltage level is fixed below the ground voltage but higher than the voltage level at which the gate-induced drain leakage (GIDL) current is generated (for example, -0.5 volts), so that the writing operation of the present invention improves the writing operation. The double-bit static random access memory with the word line voltage level also has the effect of low-order critical leakage current;

(3) The problem of avoiding the difficulty of writing the logic 1: the double-chip static random access memory for increasing the voltage level of the write word line during the write operation proposed by the present invention can be improved by the write operation It is quite difficult to write the logic level of the word line to effectively avoid the existence of the write logic 1 in the double-slot static random access memory cell with a single bit line.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

M3. . . Access transistor

M4. . . Access transistor

MWS. . . Write transistor

MRS. . . Selective transistor for reading

MINV. . . Inverting transistor

WL. . . Word line

WWL. . . Write word line

RWL. . . Read word line

BL. . . Bit line

BLB. . . Complementary bit line

WBL. . . Write bit line

RBL. . . Read bit line

A. . . Storage node

B. . . Inverting storage node

HV _DD . . . High power supply voltage

LV _DD . . . Low power supply voltage

1. . . SRAM cell

2. . . First bias circuit

3. . . Second bias circuit

SAP. . . First control signal

SAN. . . Second control signal

P21. . . Third PMOS transistor

P22. . . Fourth PMOS transistor

I23. . . Third inverter

M31. . . Third NMOS transistor

M32. . . Fourth NMOS transistor

VH. . . High voltage node

VL. . . Low voltage node

Vdd. . . voltage

Figure 1 is a circuit diagram showing a conventional 6T static random access memory cell;

Figure 2 is a timing chart showing the write operation of a conventional 6T static random access memory cell;

Figure 3 is a circuit diagram showing a conventional 5T static random access memory cell;

Figure 4 is a timing chart showing the write operation of a conventional 5T static random access memory cell;

Figure 5 is a schematic circuit diagram showing a conventional double-chip static random access memory cell;

6 is a circuit diagram showing a double-chip static random access memory for improving the voltage level of a write word line during a write operation proposed by the present invention;

Figure 7 is a timing chart showing the write operation of the double-chip static random access memory for increasing the voltage level of the write word line during the write operation proposed by the present invention;

Figure 8 is a diagram showing the critical leakage currents generated by the dual-static SRAM in the standby mode when the write word line voltage level is increased during the writing operation of Figure 6;

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

MWS. . . Write transistor

MRS. . . Selective transistor for reading

WWL. . . Write word line

RWL. . . Read word line

WBL. . . Write bit line

RBL. . . Read bit line

A. . . Storage node

B. . . Inverting storage node

HV _DD . . . High power supply voltage

LV _DD . . . Low power supply voltage

1. . . SRAM cell

2. . . First bias circuit

3. . . Second bias circuit

SAP. . . First control signal

SAN. . . Second control signal

VH. . . High voltage node

VL. . . Low voltage node

MINV. . . Inverting transistor

P21. . . Third PMOS transistor

P22. . . Fourth PMOS transistor

I23. . . Third inverter

M31. . . Third NMOS transistor

M32. . . Fourth NMOS transistor

Claims (1)

A dual-static static random access memory for increasing the voltage level of a write word line during a write operation, comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells a cell, each column of memory cells and each row of memory cells each include a plurality of memory cells (1); a first bias circuit (2), the first bias circuit (2) The system is configured to receive a first control signal (SAP), and supply a high power supply voltage (HV _DD ) to the first control signal (SAP) when it is a logic low level representing an active mode. a high voltage node (VH), and when the first control signal (SAP) is a logic high level representing a standby mode, a low power supply voltage (LV _DD ) is supplied to the high voltage node (VH) And a second bias circuit (3) for receiving a second control signal (SAN), and wherein the second control signal (SAN) is representative of the active mode The logic high level is on time, the ground voltage is supplied to a low voltage node (VL), and the second control signal (SAN) is representative of the standby mode When the logic low level is on time, a voltage higher than the ground voltage is supplied to the low voltage node (VL); wherein each memory cell (1) further comprises: a first inverter, which is a PMOS transistor (P1) is formed by the first NMOS transistor (M1), the first inverter is connected between the high voltage node (VH) and the low voltage node (VL); The phase device is composed of a second PMOS transistor (P2) and a second NMOS transistor (M2) connected to the high voltage node (VH) and the low voltage node (VL) a storage node (A) formed by the output of the first inverter; an inverting storage node (B) formed by the output of the second inverter; Selecting a transistor (MWS) connected between the storage node (A) and a write bit line (WBL), and the gate is connected to a write word line (WWL); A transistor (MRS) is selected, one end of which is connected to a read bit line (RBL), the other end is connected to an inverting transistor (MINV), and the gate is connected to a read word line ( RWL); and an inverting transistor (MINV), One end is connected to the read select transistor (MRS), the other end is connected to the low voltage node (VL), and the gate is connected to the inverting storage node (B); wherein the first inversion And the second inverter is connected in an alternating coupling manner, that is, an output end of the first inverter (ie, storage node A) is connected to an input end of the second inverter, and the second inversion is The output of the device (ie, the inverting storage node B) is connected to the input end of the first inverter; and the logic high level of the write word line (WWL) is set to at least a high power supply voltage ( HV _DD ) plus the level of the threshold voltage of the write select transistor (MWS), thereby avoiding the difficulty of writing logic 1; and the read word line (RWL) for the read operation The period is set to the high power supply voltage (HV _DD ), and is set to be lower than the ground voltage during the period other than the read operation but higher than the voltage level at which the gate-induced drain leakage (GIDL) current is generated. This is to reduce the leakage current of the non-selected SRAM cell; wherein the first bias circuit (2) is composed of a third P a MOS transistor (P21), a fourth PMOS transistor (P22), and a third inverter (I23). The source, the gate and the drain of the third PMOS transistor (P21) are respectively connected. Up to the high power supply voltage (HV _DD ), the first control signal (SAP) and the high voltage node (VH), the source, the gate and the drain of the fourth PMOS transistor (P22) are respectively connected to The low power supply voltage (LV _DD ), the output of the third inverter (I23) and the high voltage node (VH), and the input of the third inverter (I23) is used to receive the first a control signal (SAP); wherein the second bias circuit (3) is composed of a third NMOS transistor (M31) and a fourth NMOS transistor (M32), the third NMOS transistor ( The source, gate and drain of M31) are respectively connected to a ground voltage, the second control signal (SAN) and the low voltage node (VL), and the source of the fourth NMOS transistor (M32) is connected to The ground voltage is connected, and the gate is connected to the drain and connected to the low voltage node (VL).