TWI423257B - Dual port sram having a lower power voltage in writing operation - Google Patents

Description

Dual-SRAM SRAM with reduced supply voltage during write operation

The present invention relates to a static random access memory (SRAM) for reducing a power supply voltage during a write operation, and more particularly to a method for reducing leakage current and solving a single method. The double-bit SRAM of the bit line is written to the logic 1 difficult double-bit static random access memory.

Memory plays an indispensable role in the computer industry. Generally, the memory can be classified into two types: dynamic random access memory (DRAM) and static random access memory (SRAM) according to whether it can save data after the power is turned off. Dynamic random access memory (DRAM) has the advantages of small area and low price, but it must be refreshed from time to time to prevent data from being lost due to leakage current, resulting in high speed and power consumption. Missing. Conversely, the operation of the static random access memory (SRAM) is simple and does not require an update operation, so it has the advantages of high speed and low power consumption.

The semiconductor memory devices currently used in mobile electronic devices represented by mobile phones are mainly SRAM. This is due to the small standby current of the SRAM, which is suitable for mobile phones with continuous talk time and continuous standby time.

A static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows of memory cells (a). The plurality of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines, each word line corresponding to a column of a plurality of memory cells; and a plurality of bit line pairs, each bit line pair corresponding to one of the plurality of rows of memory cells, and each bit line pair is A meta-line and a complementary bit line are formed.

Figure 1 is a schematic diagram of a 6T static random access memory (SRAM) cell. The PMOS transistors P1 and P2 are called load transistors, and M1 and M2 are called drive transistors. Driving transistor), M3 and M4 are called access transistors, WL is a word line, and BL and BLB are bit lines and complementary bit lines, respectively. ), since the SRAM cell requires 6 transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, the cell ratio) is usually set between 2 and 3, resulting in the presence of Difficulties in high concentration and high prices. The 6T SRAM cell shown in Figure 1 shows the HSPICE transient analysis results during the write operation. As shown in Figure 2, it is modeled using the level 49 model using TSMC 0.35 micron CMOS process parameters. simulation.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line. Compared with the 6T SRAM cell of Figure 1, the 5T static random access memory. The bulk cell has one transistor and one less bit line than the 6T SRAM cell, but the 5T SRAM cell has a problem of writing logic 1 quite difficult. Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is modeled using the level 49 model using TSMC 0.35 micron CMOS process parameters. Simulation, from the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.

Next, we discuss the static random access memory (SRAM) and dual-layer architecture. The 6T static random access memory (SRAM) cell in Figure 1 is a static random access memory (SRAM) crystal. One example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, both reading and writing are achieved through the same pair of bit lines, so that only reading or reading can be performed at the same time. The action of writing, therefore, when designing a dual-static SRAM with simultaneous read and write capabilities, it is necessary to add two access transistors and another pair of bit lines (please refer to Figure 5). a circuit in which WBL and WBLB are write bit line pairs, RBL and RBLB are read bit line pairs, WWL is a write word line, and RWL is a read word line), which makes the memory crystal The area of the cell is greatly increased. If we can simplify the structure of the memory cell, so that one bit line is responsible for the reading action, and the other bit line is responsible for the writing action, then the double-click static random access memory is designed. When you are in the body, the memory cell does not need to add two transistors and another pair of bit lines. The area of the memory cell is much reduced. The reason why the conventional double-squeezing static random access memory cell does not adopt this method is because the problem of writing logic 1 cannot be achieved as described above.

In view of the above, the main object of the present invention is to provide a dual-SRAM which reduces the power supply voltage during a write operation, which can reduce the power supply voltage by a write operation to effectively avoid the two-dimensional static randomness with a single bit line. It is quite difficult to access the memory cell to write logic 1.

A secondary object of the present invention is to provide a dual-SRAM which reduces the power supply voltage during a write operation, which can effectively reduce the leakage current in the standby mode.

Still another object of the present invention is to provide a dual-SRAM which reduces the power supply voltage during a write operation, which reduces the power supply voltage only when logic 1 is written, thereby effectively avoiding the double with a single bit line.埠 Static random access memory cells have a problem of writing logic 1 and are quite difficult, and can also reduce the leakage current in standby mode.

The present invention provides a dual-SRAM which reduces the power supply voltage during a write operation, and includes a memory array composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory. The unit cell and each row of memory cells each include a plurality of memory cells (1); a plurality of first bias circuits (2), each column of memory cells is provided with a first bias circuit (2) The first bias circuit (2) is configured to receive a first control signal (SAP) and a write word line (WWL), the first bias circuit (2) only A low power supply voltage (LV _DD ) when a control signal (SAP) represents a logic high level in the standby mode or the write word line (WWL) is a logic high level representing the selected write state. Supplying to the high voltage node (VH), in addition to supplying a high power supply voltage (HV _DD ) to the high voltage node (VH); and a second bias circuit (3), The second bias circuit (3) is configured to receive a second control signal (SAN), and when the second control signal (SAN) is a logic high level representing the active mode, The ground voltage is supplied to the low voltage node (VL), and when the second control signal (SAN) is a logic low level representing the standby mode, a voltage higher than the ground voltage is supplied to the low voltage node (VL). .

The present invention provides another dual-SRAM which reduces the power supply voltage during a write operation, and includes a memory array composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory. The body cell and each row of memory cells each include a plurality of memory cells (1); a plurality of first bias circuits (2'), each row of memory cells being provided with a first bias circuit (2'), the first bias circuit (2') is configured to receive a first control signal (SAP) and a write bit line (WBL), the first bias circuit (2' Only when the first control signal (SAP) is a logic high level representing a standby mode or the write bit line (WBL) is a logic high level representing a selected write logic 1 state, a low power supply voltage (LV _DD ) is supplied to the high voltage node (VH), in addition to supplying a high power supply voltage (HV _DD ) to the high voltage node (VH); and a second bias voltage a circuit (3), the second bias circuit (3) is configured to receive a second control signal (SAN), and the second control signal (SAN) is a logic representing an active mode When the level is correct, the ground voltage is supplied to the low voltage node (VL), and when the second control signal (SAN) is a logic low level representing the standby mode, a voltage higher than the ground voltage is supplied to the low voltage. Node (VL).

[First Embodiment]

According to the above main object, the present invention provides a dual-SRAM which reduces the power supply voltage during a write operation, and the dual-SRAM system for reducing the power supply voltage during the write operation includes a memory array which is composed of a plurality of columns of memories. The unit cell is composed of a plurality of memory cells, each column of memory cells and each row of memory cells each including a plurality of memory cells (1); a plurality of first bias circuits (2) ), each column of memory cells is provided with a first bias circuit (2); and a second bias circuit (3).

For convenience of explanation, the double-sided SRAM for reducing the power supply voltage during the write operation shown in FIG. 6 has only one memory cell (1), one write word line (WWL), and one read word. a source line (RWL), a write bit line (WBL), a read bit line (RBL), a first bias circuit (2), and a second bias circuit (3) It is explained for the embodiment. The memory cell (1) includes a first inverter (composed of the first PMOS transistor P1 and the first NMOS transistor M1) and a second inverter (by the second PMOS transistor P2 and a second NMOS transistor M2), a write select transistor (MWS), a read select transistor (MRS), and an inverting transistor (MINV), wherein the first inverter And the second inverter is in an alternating coupling connection, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the output of the second inverter is Node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) Then, the inverted data of the SRAM cell is stored, and the write select transistor (MWS) is connected between the storage node (A) and the write bit line (WBL), and the gate is connected to Write word line (WWL); a read select transistor (MRS), one end of which is connected to the read bit line (RBL), the other end is connected to the inverting transistor (MINV), and the gate Extremely connected to the reading character (RWL); and one end of the inverter transistor (MINV) of the readout selection transistor (MRS) is connected, and the other end connected to ground, while the gate is connected to the inverting storage node (B).

Referring to FIG. 6 again, the first bias circuit (2) is composed of a third PMOS transistor (P21), a fourth PMOS transistor (P22), a third inverter (I23), and a third PMOS transistor (P21). a fifth PMOS transistor (P24), a sixth PMOS transistor (P25), and a fourth third inverter (I26), the source, gate and drain of the third PMOS transistor (P21) Connected to the 汲 terminal of the fifth PMOS transistor (P24), the write word line (WWL) and a high voltage node (VH), respectively; the source and gate of the fourth PMOS transistor (P22) Connected to the low power supply voltage (LV _DD ), the output of the third inverter (I23) and the high voltage node (VH), and the input terminal of the third inverter (I23) And receiving the write word line (WWL); the source, the gate and the drain of the fifth PMOS transistor (P24) are respectively connected to a high power supply voltage (HV _DD ), a first a control signal (SAP) and a source terminal of the third PMOS transistor (P21); a source, a gate and a drain of the sixth PMOS transistor (P25) are respectively connected to the low power supply voltage (LV _DD ) The output of the fourth inverter (I26) and the high voltage node (VH) Input terminal of the fourth inverter (I23) for receiving the first of the control signal (SAP). Furthermore, the second bias circuit (3) is composed of a third NMOS transistor (M31) and a fourth NMOS transistor (M32), the source of the third NMOS transistor (M31), The gate and the drain are respectively connected to a ground voltage, a second control signal (SAN) and a low voltage node (VL), and the source of the fourth NMOS transistor (M32) is connected to the ground voltage, and the gate Connected to the drain and connected to the low voltage node (VL).

It is worth noting here that in order to prevent the sense margin from decreasing, the voltage level of the read word line (RWL) at the nonselected level is set lower than the ground voltage. (eg, -0.5 volts), that is, the read word line (RWL) is set to the high power supply voltage (HV _DD ) during the read operation and low during the read operation. At the voltage level of the ground voltage (for example, -0.5 volts), the write word line (WWL) is set to the high power supply voltage (HV _DD ) during the write operation, and is outside the write operation. The period is set to the ground voltage.

The working principle of the preferred embodiment of the present invention in FIG. 6 is as follows:

(I) active mode

At this time, the first control signal (SAP) is a logic low level, and the second control signal (SAN) is a logic high level, and the logic high level second control signal (SAN) can make the second bias circuit ( 3) The third NMOS transistor (M31) is ON (on), so the low voltage node (VL) can be pulled down to the ground voltage.

And the logic low level first control signal (SAP) can make the fifth PMOS transistor (P24) of the first bias circuit (2) ON (on), if the write word line (WWL) is a logic low level on behalf of the unselected write state, then the third PMOS transistor (P21) in the first bias circuit (2) is turned ON (on), so that the high power supply voltage can be HVDD) is supplied to the high voltage node (VH); conversely, if the write word line (WWL) is a logic high level representing the selected write state at this time, the first bias circuit (2) is enabled The third PMOS transistor (P21) is turned OFF, and the fourth PMOS transistor (P22) is turned ON, so that the low power supply voltage (LV _DD ) can be supplied to the high voltage node (VH) ).

Next, how the writing operation of the first embodiment of the present invention in Fig. 6 is completed will be described based on the four writing states of the double-sided SRAM cell.

(1) Node A originally stores a logic 0, but now wants to write a logic 0:

Before the write operation occurs (the write word line WWL is the ground voltage), the first NMOS transistor (M1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the high voltage node (VH). ). Since the first NMOS transistor (M1) is ON, the write word line (WWL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ) when the write operation starts. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M3) (ie, the access transistor), the third NMOS transistor (M3) is turned from OFF (OFF) to ON ( Turning on, at this time, because the write bit line (WBL) is the ground voltage, node A is discharged, and the logic 0 write operation is completed until the end of the write cycle. It is worth noting here that the high voltage node (VH) has the low power supply voltage (LV _DD ) level at the beginning of writing, and has the high power supply voltage (HV _{DD )} after the end of the write cycle. ) The standard.

(2) Node A originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is the ground voltage), the first NMOS transistor (M1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the high voltage node (VH). ). Since the first NMOS transistor (M1) is ON, the write word line (WWL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ) when the write operation starts. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M3), the third NMOS transistor (M3) is turned from OFF (OFF) to ON (on), at this time because of writing The incoming bit line (WBL) is High (high power supply voltage HV _DD ); since the high voltage node (VH) drops from the high power supply voltage (HV _DD ) level to the low power supply voltage (LV) _{The level of DD} ) helps the first PMOS transistor (P1) to change from OFF to ON, and the first PMOS transistor (P1) changes from OFF to ON. When the node B transitions from High to Low, when the voltage level of the node B drops enough to turn on the first PMOS transistor (P1), the first PMOS transistor (P1) changes from OFF to (ON) ), the node A can be charged to a high power supply voltage (HV _DD ) minus the third NMOS transistor (M3) threshold voltage or the low power supply voltage (LV _DD ) to complete The write operation of logic 1. It is worth noting here that since the high voltage node (VH) has the low power supply voltage (LV _DD ) level at the beginning of writing, after the end of the write cycle The level of the high power supply voltage (HV _DD ) is such that after the end of the write cycle, the node A is charged to the level of the high power supply voltage (HV _DD ).

(3) Node A originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor (P1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the voltage node (VH). . When the write word line (WWL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ), and the voltage of the write word line (WWL) is greater than that of the third NMOS transistor (M3) At the threshold voltage, the third NMOS transistor (M3) is turned from OFF (turned) to ON (on); after the low power supply voltage (LV _DD ) is supplied to the high power supply node (v _DD ), at this time, because of writing The bit line (WBL) is High (high power supply voltage HV _DD ), and since the first PMOS transistor (P1) is still ON, the voltage of the node A is lowered to a high power supply voltage (HV _DD ) minus the first The larger of the threshold voltage of the three NMOS transistor (M3) or the low power supply voltage (LV _DD ), the high power supply voltage (HV _DD ) is supplied to the voltage node (VH) until the end of the write cycle.

(4) Node A originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor (P1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the voltage node (VH). When the write word line (WWL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ), and the voltage of the write word line (WWL) is greater than that of the third NMOS transistor (M3) At the threshold voltage, the third NMOS transistor (M3) is turned from OFF (off) to ON (on), and at this time, since the write bit line (WBL) is Low (ground voltage), the node A is discharged. The write operation of logic 0 is completed until the end of the write cycle. It is worth noting here that the high voltage node (VH) has the low power supply voltage (LV _DD ) level at the beginning of writing, and has the high power supply voltage (HV _{DD )} after the end of the write cycle. ) The standard.

The preferred embodiment of the present invention, illustrated in Figure 6, then performs the read operation in accordance with the two stored data states of the dual-slide SRAM cell.

(A) node A stores logic 0

Before the read operation occurs (the read word line (RWL) is a voltage level lower than the ground voltage, for example, -0.5 volts), the write word line (WWL) is the ground voltage, and the second NMOS transistor (M2) is OFF (off), the second PMOS transistor (P2) is ON (on), and node B is High (high power supply voltage HV _DD ). When the read operation starts, the read word line RWL is turned from the voltage level lower than the ground voltage to High (high power supply voltage HV _DD ), and when the read word line (RWL) voltage is greater than When the threshold voltage of the selective transistor (MRS) is read, the read selection transistor (MRS) is turned from OFF (turned) to ON (on), and at this time, since the node B is High, the inverted transistor (MINV) ) is ON, so a current path is formed between the read bit line (RBL), the read select transistor (MRS), the inverting transistor (MINV), and the ground. This current path is The voltage level of the read bit line (RBL) is lowered, thereby sensing that node A stores the logic 0 data and completes the logic 0 read operation.

(2) Node A storage logic 1

Before the read operation occurs (the read word line (RWL) is a voltage level lower than the ground voltage (for example, -0.5 volts)), the write word line (WWL) is the ground voltage, and the second NMOS is The crystal (M2) is ON (on), the second PMOS transistor (P2) is OFF (off), and the node B is Low (ground voltage). When the read operation starts, the read word line (RWL) is turned from the voltage level lower than the ground voltage to High (high power supply voltage HV _DD ), and when the read word line (RWL) When the voltage is greater than the threshold voltage of the read select transistor (MRS), the read select transistor (MRS) transitions from OFF (turned) to ON (on), and since node B is Low (ground voltage), The inverting transistor (MINV) is OFF (off), so it is not between the read bit line (RBL), the read select transistor (MRS), the inverting transistor (MINV), and the ground. As a result, the current path is formed, and as a result, the voltage level of the read bit line (RBL) can be smoothly maintained in the High state, thereby sensing that the node A stores the data of the logic 1 and completes the reading of the logic 1. action.

In the first embodiment of the present invention shown in FIG. 6, the HSPICE transient analysis simulation result at the time of the write operation is as shown in FIG. 7, which is simulated by the level 49 model and using TSMC 0.35 micron CMOS process parameters. It can be confirmed from the simulation results that the double-turn SRAM which reduces the power supply voltage during the write operation of the present invention can reduce the power supply voltage by the write operation, thereby effectively avoiding the double-twist static randomness with a single bit line. It is quite difficult to access the memory cell to write logic 1.

Finally, how to reduce the read current and reduce the read leakage of the nonselected dual-SRAM cell by reducing the leakage current of the non-selected dual-SRAM cell during the write operation of the present invention. Take the effect of reliability. During the read operation, the read select transistor (MRS) of the non-selected double-turn SRAM cell is in an OFF state, but there is still leakage current when the read select transistor (MRS) is turned off. The leakage current path is formed between the read bit line (RBL), the read select transistor (MRS), the inverting transistor (MINV), and the ground, and the leakage current path causes read disturb. And reduce read reliability. The present invention reduces the non-voltage level (e.g., -0.5 volts) by setting the read word line (RWL) to be lower than the ground voltage but higher than the gate-induced drain leakage (GIDL) current. Select the leakage current of the double-turn SRAM cell. In fact, the leakage current at the time of the turn-off of the transistor is mainly from the sub-resist current, and the US Patent Publication No. US6865119, issued on March 8, 2005, is the third (A) and the third (B) In the figure, it is revealed that for the NMOS transistor, the subcritical current when the gate source voltage is -0.1 volt is about 1% of the subcritical current when the gate source voltage is 0 volt, and therefore, The read word line (RWL) is set lower than the ground voltage but higher than the voltage level at which the gate-induced drain leakage (GIDL) current is generated (for example, -0.5 volts), which can significantly reduce the non-selective double-turn SRAM. The leakage current of the unit cell can reduce the read interference and improve the read reliability.

(II) Standby mode

At this time, the first control signal (SAP) is a logic high level, and the second control signal (SAN) is a logic low level, and the first control signal (SAP) of the logic high level can make the first bias circuit The fifth PMOS transistor (P24) in (2) is turned OFF, and the sixth PMOS transistor (P25) is turned ON, so that the low power supply voltage (LV _DD ) can be supplied to the high voltage. a node (VH); and the logic low level of the second control signal (SAN) can cause the third NMOS transistor (M31) in the second bias circuit (3) to be OFF (turned off), since The fourth NMOS transistor (M32) in the bias circuit (3) is still ON, so that the low voltage node (VL) can be maintained at the threshold voltage of the fourth NMOS transistor (M32). quasi.

Next, how to reduce leakage current in the standby mode of the present invention will be described. Please refer to FIG. 8 and FIG. 8 shows the critical leakage current generated by the double-turn SRAM in the standby mode of FIG. 6 (subthreshold leakage). Current) I1, I2, I3, and I4, wherein the storage node A in the double-turn SRAM cell is assumed to be a logical Low (ground voltage), and the inverting storage node (B) is a logic high (high power supply voltage HV _DD ). Referring again to the prior art of FIG. 5 and the embodiment of the present invention of FIG. 8, the leakage current I1 flowing through the write selection transistor (MWS) is due to the write word line (WWL) in the standby mode. It is a ground voltage, and therefore flows through the leakage current I1 of the write select transistor (MWS) and the prior art of FIG. 5 (the NMOS transistor M3 in the prior art is equivalent to the write selection in the embodiment of the present invention) The transistor MWS) has the same leakage current; with respect to the leakage current I2 flowing through the first PMOS transistor (P1), the voltage mode node (VM) has a low power supply voltage (LV _DD ) voltage level due to the standby mode. The voltage level of the low power supply voltage (LV _DD ) is less than the high power supply voltage (HV _DD ), and because the inverted storage node B is logic High (high power supply voltage HV _DD ), The leakage current I2 of the first PMOS transistor (P1) is much smaller than that of the prior art of FIG. 5 (the PMOS transistor P1 in the prior art is equivalent to the first PMOS transistor P1 in the embodiment of the present invention); Leakage current I3 flowing through the second NMOS transistor (M2), due to the low voltage node (VL) in the standby mode Maintaining the level of the threshold voltage of the fourth NMOS transistor (M32), and because the storage node A is logic Low (ground voltage), the leakage current I3 flowing through the second NMOS transistor (M2) is far It is smaller than the prior art of FIG. 5 (the NMOS transistor M2 in the prior art is equivalent to the second NMOS transistor M2 in the embodiment of the present invention); the leakage current flowing through the selective transistor (MRS) for reading I4, since the read word line (RWL) is set to a voltage level lower than the ground voltage (for example, -0.5 volts) in the standby mode, and because the inverting transistor (MINV) is turned on, the The source voltage of the read select transistor (MRS) is fixed at the level of the threshold voltage of the fourth NMOS transistor (M32), thereby greatly reducing the leakage current flowing through the read select transistor (MRS) I4.

From the above analysis, it can be seen that the present invention can effectively reduce leakage current in the standby mode.

[Second embodiment]

According to still another object described above, the present invention proposes another dual-SRAM which reduces the power supply voltage during a write operation, which reduces the power supply voltage only when writing logic 1, and reduces the power supply voltage during the write operation. The access memory system comprises a memory array consisting of a plurality of memory cells and a plurality of memory cells, each column of memory cells and each row of memory cells each comprising a plurality of cells. a memory cell (1); a plurality of first bias circuits (2'), each row of memory cells is provided with a first bias circuit (2'); and a second bias circuit (3) ).

For convenience of explanation, the double-sided SRAM for reducing the power supply voltage during the write operation shown in FIG. 9 has only one memory cell (1), one write word line (WWL), and one read word. a source line (RWL), a write bit line (WBL), a read bit line (RBL), a first bias circuit (2'), and a second bias circuit (3) This will be explained as an example. The memory cell (1) includes a first inverter (composed of the first PMOS transistor P1 and the first NMOS transistor M1) and a second inverter (by the second PMOS transistor P2 and a second NMOS transistor M2), a write select transistor (MWS), a read select transistor (MRS), and an inverting transistor (MINV), wherein the first inverter And the second inverter is in an alternating coupling connection, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the output of the second inverter is Node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) Then, the inverted data of the SRAM cell is stored, and the write select transistor (MWS) is connected between the storage node (A) and the write bit line (WBL), and the gate is connected to Write word line (WWL); a read select transistor (MRS), one end of which is connected to the read bit line (RBL), the other end is connected to the inverting transistor (MINV), and the gate Extremely connected to the reading character (RWL); and an inverting transistor (MINV), one end of the readout selection transistor (MRS) is connected to the other end connected to ground, while the gate is connected to the inverting storage node (B).

Referring again to FIG. 9, the first bias circuit (2') is composed of a third PMOS transistor (P21), a fourth PMOS transistor (P22), and a third inverter (I23). a fifth PMOS transistor (P24), a sixth PMOS transistor (P25) and a fourth third inverter (I26), the source, the gate and the drain of the third PMOS transistor (P21) Connected to the 汲 terminal of the fifth PMOS transistor (P24), the write bit line (WBL) and a high voltage node (VH), respectively; the source and gate of the fourth PMOS transistor (P22) The pole and the drain are respectively connected to a low power supply voltage (LV _DD ), an output of the third inverter (I23) and the high voltage node (VH), and the input of the third inverter (I23) The terminal is configured to receive the write bit line (WBL); the source, the gate and the drain of the fifth PMOS transistor (P24) are respectively connected to a high power supply voltage (HV _DD ), a first a control signal (SAP) and a source terminal of the third PMOS transistor (P21); a source, a gate and a drain of the sixth PMOS transistor (P25) are respectively connected to the low power supply voltage (LV _DD ), the output of the fourth inverter (I26) and the high voltage node (VH) Input terminal of the fourth inverter (I23) for receiving the first of the control signal (SAP). Furthermore, the second bias circuit (3) is composed of a third NMOS transistor (M31) and a fourth NMOS transistor (M32), the source of the third NMOS transistor (M31), The gate and the drain are respectively connected to a ground voltage, the second control signal (SAN) and the low voltage node (VL), and the source of the fourth NMOS transistor (M32) is connected to a ground voltage, and the gate is Connected to the drain and connected to the low voltage node (VL).

It should be noted here that in order to prevent the detection tolerance from being lowered, the voltage level of the read word line (RWL) at the time of non-selection is set to be lower than the ground voltage (for example, -0.5 volts). That is, the read word line (RWL) is set to the high power supply voltage (HV _DD ) during the read operation, and is set to a lower voltage level than the ground voltage during the read operation. (For example, -0.5 volts), the write word line (WWL) is set to the high power supply voltage (HV _DD ) during the write operation, and is set to the ground voltage during the period other than the write operation.

The second embodiment of the present invention can effectively avoid the problem of writing logic 1 by reducing the power supply voltage only when logic 1 is written. Since the writing principle is similar to that of the first embodiment, it will not be described herein.

【Effects of invention】

The double-turn SRAM for reducing the power supply voltage during the write operation proposed by the present invention has the following effects:

(1) Low read disturb and high read reliability: Since the double-sided SRAM which reduces the power supply voltage during the write operation proposed by the present invention is in the read operation, the read word line (RWL) is not The voltage level when nonselected is set lower than the ground voltage (for example, -0.5 volts), and as a result, the read can be effectively reduced by greatly reducing the leakage current of the nonselected double-turn SRAM cell. Interference and improve read reliability;

(2) Low-threshold leakage current: The high voltage node (VH) is the voltage level of the low power supply voltage (LV _DD ) when the double-turn SRAM that reduces the power supply voltage during the write operation of the present invention is in the standby mode. The low voltage node (VL) is fixed at the level of the threshold voltage of the fourth NMOS transistor (M32), and the voltage level of the read word line (RWL) is fixed below the ground voltage ( For example, the voltage level of -0.5 volts, therefore, the double-turn SRAM which reduces the power supply voltage during the write operation proposed by the present invention also has the effect of low-order critical leakage current;

(3) Avoiding the problem of writing logic 1: When the double-SRAM of the power supply voltage is reduced during the write operation of the present invention, the voltage of the high voltage node (VH) can be lowered by the write operation during the write operation. The level of writing to the logic 1 is quite difficult to effectively avoid the conventional double-slot static random access memory cell with a single bit line.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

M3. . . Third NMOS transistor

M4. . . Fourth NMOS transistor

MWS. . . Write transistor

MRS. . . Selective transistor for reading

MINV. . . Inverting transistor

WL. . . Word line

WWL. . . Write word line

RWL. . . Read word line

BL. . . Bit line

BLB. . . Complementary bit line

WBL. . . Write bit line

RBL. . . Read bit line

A. . . Storage node

B. . . Inverting storage node

HV _DD . . . High power supply voltage

LV _DD . . . Low power supply voltage

SAP. . . First control signal

SAN. . . Second control signal

P21. . . Third PMOS transistor

P22. . . Fourth PMOS transistor

I23. . . Third inverter

P24. . . Fifth PMOS transistor

P25. . . Sixth PMOS transistor

I26. . . Fourth inverter

M31. . . Third NMOS transistor

M32. . . Fourth NMOS transistor

VH. . . High voltage node

VL. . . Low voltage node

1. . . SRAM cell

2. . . First bias circuit

3. . . Second bias circuit

Vdd. . . voltage

2'. . . First bias circuit

Figure 1 is a circuit diagram showing a conventional 6T static random access memory cell;

Figure 2 is a timing chart showing the write operation of a conventional 6T static random access memory cell;

Figure 3 is a circuit diagram showing a conventional 5T static random access memory cell;

Figure 4 is a timing chart showing the write operation of a conventional 5T static random access memory cell;

Figure 5 is a schematic circuit diagram showing a conventional double-chip static random access memory cell;

Figure 6 is a circuit diagram showing a double-turn SRAM for reducing a power supply voltage during a write operation proposed in the first embodiment of the present invention;

Figure 7 is a timing chart showing the write operation of the double-turn SRAM for reducing the power supply voltage during the write operation proposed in the first embodiment of the present invention;

Figure 8 shows the critical leakage currents generated by the double-turn SRAM in the standby mode in Figure 6;

Fig. 9 is a circuit diagram showing a double-turn SRAM for reducing a power supply voltage in a write operation proposed in the second embodiment of the present invention.

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

MWS. . . Write transistor

MRS. . . Selective transistor for reading

WWL. . . Write word line

RWL. . . Read word line

WBL. . . Write bit line

RBL. . . Read bit line

A. . . Storage node

B. . . Inverting storage node

HV _DD . . . High power supply voltage

LV _DD . . . Low power supply voltage

SAP. . . First control signal

SAN. . . Second control signal

VH. . . High voltage node

VL. . . Low voltage node

P21. . . Third PMOS transistor

P22. . . Fourth PMOS transistor

I23. . . Third inverter

P24. . . Fifth PMOS transistor

P25. . . Sixth PMOS transistor

I26. . . Fourth inverter

M31. . . Third NMOS transistor

M32. . . Fourth NMOS transistor

1. . . SRAM cell

2. . . First bias circuit

3. . . Second bias circuit

MINV. . . Inverting transistor

Claims (5)

A double-sided SRAM for reducing a power supply voltage during a write operation includes: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each a row of memory cells each including a plurality of memory cells (1); a plurality of first bias circuits (2'), each row of memory cells being provided with a first bias circuit (2'), The first bias circuit (2') is configured to receive a first control signal (SAP) and a write bit line (WBL), and only the first control signal (SAP) represents a standby mode A low power supply voltage (LV _DD ) is supplied to a high voltage node when the logic high level of the standby mode or the write bit line (WBL) is a logic high level of the selected write logic 1 state ( VH), in addition to supplying a high power supply voltage (HV _DD ) to the high voltage node (VH); and a second bias circuit (3), the second bias circuit (3) ) for receiving a second control signal (SAN), and supplying the ground voltage to a low when the second control signal (SAN) is a logic high level representing the active mode a voltage node (VL), and when the second control signal (SAN) is a logic low level representing a standby mode, a voltage higher than a ground voltage is supplied to the low voltage node (VL); wherein each memory The body cell (1) further includes: a first inverter composed of a first PMOS transistor (P1) and a first NMOS transistor (M1), the first inverter being connected to the high voltage a node (VH) and the low voltage node (VL); a second inverter consisting of a second PMOS transistor (P2) and a second NMOS transistor (M2), the second inverter Connected between the high voltage node (VH) and the low voltage node (VL); a storage node (A) formed by the output of the first inverter; an inverted storage node (B) Formed by the output of the second inverter; a write select transistor (MWS) is connected between the storage node (A) and the write bit line (WBL), and The gate is connected to a write word line (WWL); a read select transistor (MRS) has one end connected to a read bit line (RBL) and the other end connected to an inverting transistor ( MINV) is connected, while the gate is connected Connected to a read word line (RWL); and an inverting transistor (MINV) having one end connected to the read select transistor (MRS) and the other end connected to the low voltage node (VL) And the gate is connected to the inverting storage node (B); wherein the first inverter and the second inverter are connected in an alternating coupling, that is, the output of the first inverter (ie, storage) Node A) is coupled to the input of the second inverter, and the output of the second inverter (ie, the inverting storage node B) is coupled to the input of the first inverter. A double-turn SRAM for reducing a power supply voltage during a write operation as described in claim 1, wherein the first bias circuit (2') is composed of a third PMOS transistor (P21) and a fourth PMOS. a transistor (P22), a third inverter (I23), a fifth PMOS transistor (P24), a sixth PMOS transistor (P25), and a fourth third inverter (I26), the first The source, gate and drain of the three PMOS transistor (P21) are respectively connected to the 汲 terminal of the fifth PMOS transistor (P24), the write bit line (WBL) and the high voltage node (VH) The source, gate and drain of the fourth PMOS transistor (P22) are respectively connected to the low power supply voltage (LV _DD ), the output of the third inverter (I23) and the high voltage a node (VH), the input end of the third inverter (I23) is configured to receive the write bit line (WBL); the source, the gate and the drain of the fifth PMOS transistor (P24) Connected to the high power supply voltage (HV _DD ), the first control signal (SAP) and the source terminal of the third PMOS transistor (P21); the source and gate of the sixth PMOS transistor (P25) The pole and the drain are respectively connected to the low power supply voltage (L V _DD ), an output of the fourth inverter (I26) and the high voltage node (VH), and an input of the fourth inverter (I23) is configured to receive the first control signal (SAP). A double-turn SRAM for reducing a power supply voltage during a write operation as described in claim 1, wherein the second bias circuit (3) is composed of a third NMOS transistor (M31) and a fourth NMOS device. a crystal (M32), the source, the gate and the drain of the third NMOS transistor (M31) are respectively connected to a ground voltage, the second control signal (SAN) and the low voltage node (VL), The source of the fourth NMOS transistor (M32) is connected to the ground voltage, and the gate is connected to the drain and connected to the low voltage node (VL). A double-sided SRAM for reducing a power supply voltage during a write operation as described in claim 1, wherein the write bit line (WBL) is the high power supply voltage when the selected write logic 1 state ( The level of HV _DD ). A double-turn SRAM for reducing a power supply voltage during a write operation as described in claim 1, wherein the read word line (RWL) is set to the high power supply voltage during a read operation (HV _DD) ), while the period other than the read operation is set to a voltage level lower than the ground voltage.