201027532 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種寫入操作時降低電源電壓之雙埠靜態隨機存 取 §己憶體（Static Random Access Memory，簡稱 SRAM )，尤指一種可 降低漏電流(leakage current)且能解決習知具單一位元線之雙埠sram 寫入邏輯1困難之雙埠靜態隨機存取記憶體。 . 【先前技術】 5己憶體在電腦工業中扮演著無可或缺的角色。通常，記憶體可依照 其能否在電源關閉後仍能保存資料，而區分為動態隨機存取記憶體 (DRAM)及靜態隨機存取記憶體(SRAM)兩種。動態隨機存取記憶體 (DRAM)具有面積小及價格低等優點，但操作時必須不時地更新(reftesh) 以防止資料因漏電流而遺失，而導致存在有高速化困難及消耗功率大 等缺失。相反地，靜態隨機存取記憶體(SRAM^操作則較為簡易且毋 須更新操作，因此具有高速化及消耗功率低等優點。 目前以行動電話為代表之行動電子設備所採用之半導體記憶裝 φ 置，係以SRAM為主流。此乃由於SRAM待機電流小，適於連續通話 時間、連續待機時間盡可能延長之手機》 - 靜態隨機存取記憶體(SRAM)主要包括一記憶體陣列（memory 抓吵）’該記憶體陣列係由複數列記憶體晶胞（a plurality of rows of memory cells)與複數行記憶體晶胞（aplurality〇fc〇lunms〇fmem〇iy cells)所組成，每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個 記憶體晶胞；複數條字元線(word Hne)，每一字元線對應至複數列記憶 體晶胞中之一列’以及複數位元蜂對(bit pdrs)，每一位元線對係對 應至複數行記憶體晶胞中之一行，且每一位元線對係由一位元線及一 互補位元線所組成。 3 201027532 第1圖所示即是6T靜態隨機存取記憶體(SRAM)晶胞之電路示意 圖，其中，PMOS電晶體P1和P2稱為負載電晶體（load transistor)， Ml和M2稱為驅動電晶體（driving transistor) ’ M3和M4稱為存取電 晶體（access transistor) ’ WL 為字元線(wordline)，而 BL 及 BLB 分別 為位元線（bit line)及互補位元線（complementary bit line)，由於該 SRAM晶胞需要6個電晶體，且驅動電晶體與存取電晶體間的電流驅 動能力比(即單元比率(cell ratio))通常設定在2至3之間’而導致存在有 高集積化困難及價格高等缺失。第1圖所示6T靜態隨機存取記憶體晶 _ 胞，於寫入操作時之HSPICE暫態分析模擬結果，如第2圖所示，其係 以level 49模型且使用TSMC 0.35微米CMOS製程參數加以模擬。 用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種 方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5丁靜態隨 機存取記憶體晶胞之電路示意圖，與第丨圖之6T靜態隨機存取記憶體 晶胞相比，此種5Τ靜態隨機存取記憶體晶胞比6Τ靜態隨機存取記憶 體晶胞少一個電晶體及少一條位元線，惟該57靜態隨機存取記憶體晶 胞存在寫人賴1相當_之問題。財慮織晶胞左側_ Α原本 ❷ 儲存邏輯〇的情況，由於節點Α之電荷僅單獨自位元線(BL)傳送，因 此很難將節點A中先前寫入的邏輯〇蓋寫成邏輯卜第3圖所示5τ靜 •4隨機存取記憶體晶胞，於寫入操作時之HSPICE暫態分析模擬結果， 如第4圖所* ’其係以level 49模型且使用TSMC Ο·%微米cm〇s製 程參數加以模擬，由該模擬結果可註實，具單一位元線之灯靜態隨機 存取έ己憶體晶胞存在寫入邏輯1相當困難之問題。 接下來討論靜態隨機存取記憶體(SRAM)之單埠及雙埠架構，第工 圖之6T靜態隨機存取記憶體(SRAM)a%胞即是科靜態隨機存取記憶 體(SRAM)曰曰曰胞之一例，其係使用兩條位元線BL及blb做讀寫的動 作’也就是賴寫均是經由同__對位元線來賴，是以在同一時 4 201027532201027532 VI. Description of the Invention: [Technical Field] The present invention relates to a static random access memory (SRAM) for reducing a power supply voltage during a write operation, and more particularly to a It can reduce leakage current and can solve the problem of double-click static random access memory which is difficult to write logic 1 with a single bit line. [Prior Art] 5 Remembrance plays an indispensable role in the computer industry. Generally, memory can be classified into dynamic random access memory (DRAM) and static random access memory (SRAM) according to whether it can save data after the power is turned off. Dynamic random access memory (DRAM) has the advantages of small area and low price, but it must be updated from time to time to prevent data from being lost due to leakage current, resulting in high speed and power consumption. Missing. On the contrary, the SRAM^ operation is simpler and requires no update operation, so it has the advantages of high speed and low power consumption. Currently, the semiconductor memory device used in mobile electronic devices represented by mobile phones is set. SRAM is the mainstream. This is because the SRAM has a small standby current and is suitable for continuous talk time and continuous standby time as long as possible. - Static Random Access Memory (SRAM) mainly includes a memory array (memory The memory array is composed of a plurality of columns of memory cells and a plurality of memory cells (aplurality〇fc〇lunms〇fmem〇iy cells), each column of memory crystals The cell and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word Hne), each word line corresponding to one of the plurality of memory cells, and a plurality of bit bees For (bit pdrs), each bit line pair corresponds to one of the plurality of rows of memory cells, and each bit line pair is composed of one bit line and one complementary bit line. 3 201027532 Figure 1 is a schematic diagram of a 6T static random access memory (SRAM) cell. The PMOS transistors P1 and P2 are called load transistors, and Ml and M2 are called drive transistors. Driving transistor) ' M3 and M4 are called access transistors ' WL is a word line, and BL and BLB are bit lines and complementary bit lines, respectively. Since the SRAM cell requires 6 transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, the cell ratio) is usually set between 2 and 3', resulting in a high presence. The difficulty of accumulation and the high price are missing. The 6T static random access memory cell shown in Fig. 1 shows the HSPICE transient analysis simulation result during the write operation. As shown in Fig. 2, it is a level 49 model. And simulated using TSMC 0.35 micron CMOS process parameters. One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a single bit 5-D static random access memory The circuit diagram of the bulk cell, compared with the 6T SRAM cell of the second figure, the 5" SRAM cell has one less transistor than the 6Τ SRAM cell and There is one less bit line, but the 57 static random access memory cell has a problem that the writer is quite ok. The left side of the cell is _ Α ❷ ❷ 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存3 shows the 5τ static•4 random access memory cell, the HSPICE transient analysis simulation result during the write operation, as shown in Fig. 4', which is based on the level 49 model and uses TSMC Ο·% micron cm The 〇s process parameters are simulated, and the simulation results can be inferred. It is quite difficult to have a single bit line lamp static random access έ memory cell exists to write logic 1. Next, we discuss the static random access memory (SRAM) and double-frame architecture. The 6T static random access memory (SRAM) a% cell is the static random access memory (SRAM). One example of a cell, which uses two bit lines BL and blb for reading and writing, that is, the write is performed by the same __ bit line, at the same time 4 201027532
❹ 間内只能進行讀或寫的動作，因此，當欲設計具有同時讀寫能力之雙 埠靜態隨機存取記憶體時，便需要多加人兩顆存取電晶體以及另一對 位元線（請參考第5圖所示電路，其中WBL及WBLB為寫入用位元線 對、RBL及RBLB為讀取祕元麟、wwl域人財元線、R· 為λ取用子元線）使得§己憶晶胞的面積大大地增加，如果我們能夠 簡化記憶晶胞的架構’使得—條位元線貞責讀取的動作，^另一條位 元線負責寫人_作’财設計雙轉紐機存取記紐時，記憶晶 胞便不需要多加人兩顆電晶體及另__對位元線，這樣記憶晶胞的面積 便會減小許多。傳統的雙轉態隨機存取記髓晶胞之所以不採用這 種方法’是目為如前所述之無法達絲人邏輯丨的問題。 有鑑於此，本發明之主要目的係提出一種寫入操作時降低電源電壓 之雙淳SRAM ’其能藉由寫入操作時降低電源電壓以有效避免習知具 單一位元狀雙轉贿機棘記舰晶赫«人邏輯1相當困難 之問題。 本發明作之次要目㈣提出__種寫人操作時降低電源電壓之雙缚 SRAM > 耕之漏電流。 本發明之再-目的係提出另—種寫人操作時降低電源電壓之雙蜂 目R^M :僅於寫人邏輯1時方降低電源賴’俾藉此以有效避免習知 ’、位元線之雙琿靜態隨機存取記紐晶胞存在寫人邏輯1相當困 難問題，並且也驗將機赋_低漏餘之功效。 【發明内容】 本發月提ill種寫人操作時降低電源電壓之雙槔sram，其係包 括曰讀斯列’該記憶财職由複數列記舰晶胞與複數行記憶 體明胞所减每-列魏體晶胞與每—行記麵晶胞各包括有複數 個讀體舶胞⑴，複數個第—偏壓電路⑺，每-列記憶體晶胞設 置-個第-偏壓電路(2)，該第—偏壓電路(2)制以接收—第一控制信 5 201027532 號(SAP)與一寫入用字元線(瓢)，該第一偏壓電路⑺僅於該第一控制 佗號(SAP)為代表待機模式(standby m〇(Je)之邏輯高位準或該寫入用字 元線(WWL)為代表選定寫入狀態之邏輯高位準時，方將一低電源供應 電壓(lvdd)供應至該高電壓節點(VH)，除此之外，則將一高電源供應 電壓(HVDD)供應至該高電壓節點;以及一第二偏壓電路⑶，該第 二偏壓電路⑶係用以接收一第二控制減(SAN)，且於該第二控制信號 (SAN)域表絲赋之賴純料，將接地電祕應至雜電壓節 • 點(VL) ’而於該第二控制信號(SAN)為代表待機模式之邏輯低位準時， *〇 則將較接地電壓為高之一電廢供應至該低電壓節點(VL)。 本發明提出另一種寫入操作時降低電源電壓之雙埠SRAM，其係 包括-記賴_ ’該記賴_係由複數列記賴晶賴複數行記 憶體晶胞所域，每—航舰晶胞與每—行記賴晶齡包括有複 數個記憶體晶胞⑴；複數個第—偏壓電路(2，），每_行記憶體晶胞 a又置一個第一偏壓冑路(2，），該第一偏麼冑路⑺係肖以接收一第一控 制信號(SAP)與-寫入用位元線(WBL)，該第一偏壓電路(2，)僅於該第 控制t號(SAP)為代表待機模式(standby m〇de)之邏輯高位準或該寫 _ 人用位元線([)域表敎寫人邏輯1狀態之邏輯高位料，方將一 低電源供應電壓(lvdd)供應至該高電壓節點(VH)，除狀外，則將一 间電源供應電壓(hvdd)供應至該高電壓節點_);以及一第二偏壓電 路(3) ’該第二偏壓電路(3)係用以接收一第二控制信號(SAN)，且於該 第二控制信號(SAN)為代表主動模式之邏輯高位準時，將接地電壓供應 至該低電壓節點(VL)，而於該第二控制信號(SAN)為代表待機模式之邏 輯低位準時，則將較接地電壓為高之一電壓供應至該低電壓節點⑽。 【實施方式】 【第1實施例】 201027532 輯上述之主要目的，本㈣辦-種冑人操作時降低電源電塵之 蜂SRAM ’該寫入操作時降低電源電壓之雙埠s麵係包括一記憶 ^車列4記紐陣舰由複朗記㈣晶胞與複數行記憶體晶胞所 =成每列s己憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體 晶胞⑴；複數個-第-偏壓電路⑵，每—列記憶體晶胞設置一 個第一偏壓電路⑵；以及-第二偏壓電路⑴。 、為了便魏明起見’帛6 _示之寫人猶畴低魏電壓之雙璋 RAM僅以個5己憶體晶胞〇)、一條寫入用字元線、一 ·_ 條讀糊字元線（RWL)、—條S人雜元線(WBL)、-條讀取用位元 線(RBL)、-第一偏壓電路⑵以及一第二偏麼電路⑴做為實施例 來說明。該記憶體晶胞⑴係包括一第一反相器(由第一 pM〇s電晶 體P1與第一 NMOS電晶體Ml所組成）、一第二反相器(由第二pM〇s 電晶體P2與第二nm〇S電晶體M2所組成）、一寫入用選擇電晶體 (MWS)、一讀取用選擇電晶體(mrs)、以及一反相電晶體(Miisfy),其 中，該第一反相器和該第二反相器係呈交互輕合連接，亦即該第一反 相器之輸出（即節點A)係連接該第二反相器之輸入，而該第二反相器之 • 輸出（即節點B)則連接該第一反相器之輸入，並且該第一反相器之輸出 (節點A)係用於儲存SRAM晶胞之資料，而該第二反相器之輸出（節點 B)則用於儲存SRAM晶胞之反相資料，該寫入用選擇電晶體(mws)， - 係連接在該儲存節點(A)與寫入用位元線(WBL)之間，且閘極連接至寫 入用字元線(WWL); —讀取用選擇電晶體(MRS)，其一端連接至讀取用 位元線(RBL)，另一端與反相電晶體(MINV)相連接，而閘極則連接至讀 取用字元線(RWL);而該反相電晶體(MINV)之一端與該讀取用選擇電 晶體(MRS)相連接，另一端連接至接地，而閘極則連接至反相儲存節點 ⑼。 請再參考第6圖，該第一偏壓電路(2)係由一第三PM〇s電晶體 7 201027532 (P21)、一第四PMOS電晶體(P22)、一第三反相器(123)、一第五PMOS 電晶體(P24)、一第六PMOS電晶體(P25)以及四第三反相器(126)所組 成，該第三PMOS電晶體(P21)之源極、閘極與汲極係分別連接至該第 五PMOS電晶體(P24)之汲極端、該寫入用字元線（WWL)與一高電壓 節點(VH);該第四PMOS電晶體(P22)之源極、閘極與汲極係分別連接 至一低電源供應電壓(LVDD)、該第三反相器(123)之輸出端與該高電壓節 點(VH) ’該第三反相器(123)之輸入端則用以接收該寫入用字元線 (WWL);該第五PMOS電晶體(P24)之源極、閘極與汲極係分別連接 至一高電源供應電壓(HVDD)、一第一控制信號(SAP)與該第三PMOS電 曰曰體(P21)之源極端，該第六PMOS電晶體(P25)之源極、閘極與没極 係分別連接至該低電源供應電壓(LVDD)、該第四反相器(126)之輸出端與 該高電壓節點(VH)，該第四反相器(123)之輸入端則用以接收該第一控 制信號(SAP)。再者’該第二偏壓電路⑶係由一第三麵⑽電晶體(M3i) 以及一第四NMOS電晶體(M32)所組成，該第三]sf]v[〇s電晶體如31) 之源極、閘極與汲極係分別連接至接地電壓、一第二控制信號(SAN) 與一低電壓節點(VL)，該第四NM0S電晶體(M32)之源極係連接至接地 電壓，而閘極與沒極係連接在一起，並連接至該低電壓節點 在此值得注意的是，本發明為了防止感測容限(sense margin)降 低於疋將該凟取用子元線(RWL)於非選擇(nonseiected)時之電壓位準 設定成低於接地電壓(例如_0·5伏特），亦即，該讀取用字元線(RWL)於 頃取操作朗係設定為該高電源供應電壓(HV如），而於讀取操作以外 之期間則設定為低於接地電壓之電壓位準(例如·05伏特），至於該寫入 用字元線(WWL)於寫人鮮_係設定為該高電源供應電壓(取即）， 而於寫入操作以外之期間則設定為接地電壓。 兹依雙埠SRAM之工作模式說明第6圖之本發明較佳實施例的工 作原理如下： 8 201027532 (I)主動模式(active mode) 此時該第一控制信號(SAP)為邏輯低位準，而該第二控制信號(SAN) 為邏輯高位準，該邏輯高位準之第二控制信號(SAN)可使得第二偏壓 電路(3)中之第三NM〇S電晶體(M31)〇雨通），於是可將低電壓節點 (VL)拉下至接地電壓。 而該邏輯低辦之第-鋪信號(SAP)可使_第—碰電路(2) 中之第五PMOS電晶體(PM) on(導通)，此時若該寫入用字元線(WWL) 為代表非選定寫入狀態之邏輯低位準時，則使該第一偏壓電路(2)中之 Φ 第—PM〇S電晶體的1) ON(導通），於是可將高電源供應電壓(HVDD) 供應至該高電壓節點(VH);反之，若此時該寫入用字元線(wwl)為代 表選定寫人狀態之邏輯高轉時，則使該第—偏壓電路(2)中之第三 PMOS電晶體(P2l) 〇FF(截止），並使第四pm〇s電晶體(P22) ON(導 通）於疋可將該低電源供應電壓(LvDD)供應至該高電壓節點yH)。 接下來依雙埠SRAM晶胞之4種寫入狀態來說明第6圖之本發明第i 實施例如何完成寫入動作。 (一）節點A原本儲存邏輯0，而現在欲寫入邏輯〇: φ 在寫入動作發生前(寫入用字元線WWL為接地電壓），第一 nm〇s 電晶體(Ml)為ON(導通），該高電源供應電壓供應至該高電壓節 點(VH)。因為第一 nM〇S電晶體(M1)為〇N，所以當寫入動作開始時， 寫入用字το線(WWL)由Low(接地電壓)轉High(高電源供應電壓 HVDD)。當寫入用字元線(WWL)的電壓大於第三麵〇3電晶體（M3) (即存取電晶體）的臨界電壓時，第三观⑽電晶體（M3)由〇ff(截 止)轉變為ON(導通），此時因為寫入用位元線（WBL)是接地電壓， 所以會將節點A放電，而完成邏輯〇的寫入動作，直到寫入週期結束。 在此值得注意的是，該高電壓節點(VH)於寫入初期係具有該低電源供 應電壓(LVDD)之位準，而於寫入週期結束後則具有該高電源供應電壓 201027532 (hvdd)之位準。 (二）節點A原本儲存邏輯〇，而現在欲寫入邏輯1 :Only read or write can be performed in the middle. Therefore, when designing a dual-static static random access memory with simultaneous read and write capability, it is necessary to add two access transistors and another pair of bit lines. (Please refer to the circuit shown in Figure 5, where WBL and WBLB are bit line pairs for writing, RBL and RBLB are for reading secret yuan, wwl domain, and R· is λ for sub-line) The area of § 忆 晶 晶 大大 大大 大大 , , , , , , § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § When the switch is accessed, the memory cell does not need to add two transistors and another __ bit line, so the area of the memory cell will be much reduced. The reason why the traditional double-transition random access memory cell is not used in this way is that the problem of the inability to reach the human logic is as described above. In view of the above, the main object of the present invention is to provide a dual-SRAM that reduces the power supply voltage during a write operation, which can reduce the power supply voltage by a write operation to effectively avoid the conventional single-transfer double-transfer machine. Remember the ship Jinghe «Human Logic 1 is quite difficult. The secondary item (4) of the present invention proposes a double-binding SRAM of the power supply voltage when the writer operates, and the leakage current of the ploughing. The re-purpose of the present invention is to propose another type of double-humming R^M for reducing the power supply voltage during the operation of the writer: the power supply is reduced only when the logic 1 is written, thereby effectively avoiding the conventional 'bits. The line double-static static random access memory cell has a problem of writing human logic 1 and it is also a problem of low leakage. [Summary of the Invention] This month raises the sram, which reduces the power supply voltage during the operation of the person, including the reading of the column. The memory of the memory is reduced by the plural column of the unit cell and the complex line of memory cells. - The Levin body cell and each row cell include a plurality of read cells (1), a plurality of first-bias circuits (7), and each column memory cell is provided with a first-bias circuit ( 2), the first bias circuit (2) is configured to receive - the first control letter 5 201027532 (SAP) and a write word line (scoo), the first bias circuit (7) only The first control nickname (SAP) is a low power source that represents the standby mode (standby m〇(Je) logic high level or the write word line (WWL) is a logic high level representing the selected write state. Supply voltage (lvdd) is supplied to the high voltage node (VH), in addition to supplying a high power supply voltage (HVDD) to the high voltage node; and a second bias circuit (3), the second The bias circuit (3) is configured to receive a second control minus (SAN), and in the second control signal (SAN) domain, the wire is assigned to the pure material, and the grounding voltage is applied to the hybrid voltage. • Point (VL) 'When the second control signal (SAN) is a logic low level representing the standby mode, *〇 is supplied to the low voltage node (VL) one of the higher than the ground voltage. Another type of double-strip SRAM that reduces the power supply voltage when writing is proposed, which includes -remembering _ 'the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Each of the lines includes a plurality of memory cells (1); a plurality of first-bias circuits (2,), and each of the memory cells a is further provided with a first bias circuit (2,), The first bias circuit (7) is configured to receive a first control signal (SAP) and a write bit line (WBL), and the first bias circuit (2) is only for the first control t number (SAP) is a logic high level representing the standby mode (standby m〇de) or the write _ human bit line ([) domain table writes the logic high state of the logic state 1 to a low power supply voltage ( Lvdd) is supplied to the high voltage node (VH), and in addition to the shape, a power supply voltage (hvdd) is supplied to the high voltage node _); and a second bias circuit (3) ' The second bias circuit (3) is configured to receive a second control signal (SAN), and supply the ground voltage to the low voltage node when the second control signal (SAN) is a logic high level representing the active mode (VL), and when the second control signal (SAN) is a logic low level representing the standby mode, a voltage higher than the ground voltage is supplied to the low voltage node (10). [Embodiment] [First Embodiment] 201027532 The main purpose of the above-mentioned series is to reduce the power supply voltage of the bee SRAM during the operation of the monk. Memory ^Car List 4 New Zealand Ships From Fu Lang Ji (4) Unit Cell and Complex Line Memory Cell = = Each column of the memory cell and each row of memory cells each including a plurality of memory cells (1); a plurality of --biasing circuits (2), each of which is provided with a first biasing circuit (2); and - a second biasing circuit (1). In order to make it clear to Wei Ming, '帛6 _ shows that the writers are still in the low-voltage voltage of the double-chip RAM only with a 5 memory cell 〇), a write word line, a _ reading paste word A line (RWL), a strip of S human moiré lines (WBL), a stripe read bit line (RBL), a first bias circuit (2), and a second bias circuit (1) are illustrated as an embodiment. . The memory cell (1) includes a first inverter (composed of a first pM〇s transistor P1 and a first NMOS transistor M1) and a second inverter (by a second pM〇s transistor) P2 is composed of a second nm 〇S transistor M2), a write selection transistor (MWS), a read selection transistor (mrs), and an inversion transistor (Miisfy), wherein the An inverter and the second inverter are in an interactive light connection, that is, an output of the first inverter (ie, node A) is connected to an input of the second inverter, and the second inversion is The output (ie, node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store data of the SRAM cell, and the second inverter The output (node B) is used to store the inverted data of the SRAM cell, and the write select transistor (mws) is connected to the storage node (A) and the write bit line (WBL). And the gate is connected to the write word line (WWL); - the read select transistor (MRS), one end of which is connected to the read bit line (RBL), and the other end is connected to the inverting transistor ( MINV) is connected, and The pole is connected to the read word line (RWL); one end of the inverting transistor (MINV) is connected to the read select transistor (MRS), the other end is connected to the ground, and the gate is connected To the inverting storage node (9). Referring again to FIG. 6, the first bias circuit (2) is composed of a third PM 〇s transistor 7 201027532 (P21), a fourth PMOS transistor (P22), and a third inverter ( 123), a fifth PMOS transistor (P24), a sixth PMOS transistor (P25), and a fourth third inverter (126), the source and gate of the third PMOS transistor (P21) And the drain is connected to the drain terminal of the fifth PMOS transistor (P24), the write word line (WWL) and a high voltage node (VH), respectively; the source of the fourth PMOS transistor (P22) The pole, the gate and the drain are respectively connected to a low power supply voltage (LVDD), an output of the third inverter (123) and the high voltage node (VH) 'the third inverter (123) The input end is configured to receive the write word line (WWL); the source, the gate and the drain of the fifth PMOS transistor (P24) are respectively connected to a high power supply voltage (HVDD), a first control signal (SAP) and a source terminal of the third PMOS transistor (P21), wherein the source, the gate and the gate of the sixth PMOS transistor (P25) are respectively connected to the low power supply voltage (LVDD), the output of the fourth inverter (126) and High voltage node (VH), the fourth inverter (123) is configured to receive the input of the first control signal (SAP). Furthermore, the second bias circuit (3) is composed of a third surface (10) transistor (M3i) and a fourth NMOS transistor (M32), and the third]sf]v[〇s transistor such as 31 The source, the gate and the drain are respectively connected to a ground voltage, a second control signal (SAN) and a low voltage node (VL), and the source of the fourth NMOS transistor (M32) is connected to the ground Voltage, and the gate is connected to the galvanic pole and connected to the low voltage node. It is worth noting here that the present invention prevents the sense margin from being lowered by 子 using the sub-line (RWL) is set to a voltage level lower than the ground voltage (eg, _0·5 volts) when nonseiected, that is, the read word line (RWL) is set to The high power supply voltage (HV, for example) is set to a voltage level lower than the ground voltage (for example, ·05 volts) during a period other than the read operation, and the write word line (WWL) is written to the person. The fresh_ is set to the high power supply voltage (ie, it is), and is set to the ground voltage during periods other than the write operation. The working principle of the preferred embodiment of the present invention is as follows: 8 201027532 (I) active mode At this time, the first control signal (SAP) is at a logic low level. The second control signal (SAN) is a logic high level, and the logic high level second control signal (SAN) can make the third NM〇S transistor (M31) in the second bias circuit (3) Yutong), so the low voltage node (VL) can be pulled down to the ground voltage. And the logic-lower-first signal (SAP) can make the fifth PMOS transistor (PM) on in the _first-touch circuit (2), if the write word line (WWL) In order to represent the logic low level of the unselected write state, 1) of the Φ-PM〇S transistor in the first bias circuit (2) is turned ON, so that the high power supply voltage can be applied. (HVDD) is supplied to the high voltage node (VH); conversely, if the write word line (wwl) is a logic high rotation representing the selected write state, the first bias circuit is enabled ( 2) The third PMOS transistor (P2l) 〇 FF (off), and the fourth pm 〇s transistor (P22) ON (on) can supply the low power supply voltage (LvDD) to the high Voltage node yH). Next, how the i-th embodiment of the present invention in Fig. 6 completes the writing operation will be described in accordance with the four writing states of the double-sided SRAM cell. (1) Node A originally stores logic 0, but now wants to write logic 〇: φ Before the write operation occurs (write word line WWL is the ground voltage), the first nm〇s transistor (Ml) is ON. (On), the high power supply voltage is supplied to the high voltage node (VH). Since the first nM〇S transistor (M1) is 〇N, when the write operation starts, the write word το line (WWL) is turned from Low (ground voltage) to High (high power supply voltage HVDD). When the voltage of the write word line (WWL) is greater than the threshold voltage of the third face 电3 transistor (M3) (ie, the access transistor), the third view (10) transistor (M3) is determined by 〇ff (off) When it is turned ON, at this time, since the write bit line (WBL) is the ground voltage, the node A is discharged, and the logic 〇 write operation is completed until the end of the write cycle. It is worth noting here that the high voltage node (VH) has the low power supply voltage (LVDD) level at the beginning of writing, and has the high power supply voltage 201027532 (hvdd) after the end of the writing period. The level of it. (2) Node A originally stores the logical 〇, but now wants to write logic 1:
在寫入動作發生前(寫入用字元線WWL為接地電壓），第一 NMOS 電晶體(Ml)為ON (導通）’該高電源供應電壓(HVdd)供應至該高電壓 節點(VH：^因為第一 NM0S電晶體(M1)為〇N，所以當寫入動作開始 時，寫入用字元線(WWL)由Low(接地電壓)轉High(高電源供應電壓 HVDD)。當寫入用字元線(界^)的電壓大於第三_〇8電晶體（M3) • 的臨界電壓時，第三NMOS電晶體（M3)由OFF(截止)轉變為ON(導 φ 通），此時因為寫入用位元線（WBL)是High(高電源供應電壓HVdd); 由於該高電壓節點(VH)會由該高電源供應電壓(HVdd)之位準下降至該 低電源供應電壓(LVDD)之位準，因此有助於第一 pm〇S電晶體(P1)由 OFF(截止)轉變為〇N(導通），待第一 PM〇s電晶體⑻)由〇FF(截止)轉 變為ON(導通)時(由於節點B由朝L〇w方向轉變，當節點B之電 壓位準下降至足以使第一 PM〇s電晶體(pl)導通時，該第一 pM〇s電 晶體(P1)即由OFF轉變為(0N)，即可將節點a充電至高電源供應電壓 (hvdd)扣減該第三NM0S電晶體（M3)的臨界電壓或該低電源供應電 φ 壓(LVdd)兩者中之較大者，而完成邏輯1的寫入動作。在此值得注意的 是，由於該高電壓節點(VH)於寫入初期係具有該低電源供應電壓(lvdd) 之位準’而於寫入週期結束後則具有該高電源供應電壓(HVdd)之位 準，因此，寫入週期結束後，該節點A會被充電至該高電源供應電壓 (HV〇d)之位準。 (二）節點A原本儲存邏輯丨，而現在欲寫入邏輯1 : 在寫入動作發生前(寫入用字元線WWL為接地電壓），第一 PMOS 電晶體(P1)為0N(導通）’該高電源供應電壓(HVDD)供應至該電壓節點 (VH)。當寫入用字元線(WWL)由Low(接地電壓)轉High(高電源供應電 壓HVDD)，且該寫入用字元線(WWL)的電壓大於第三NMQS電晶體 201027532 (M3)的臨界電壓時，第三電晶體（M3)由〇FF(截止)轉變為 ON(導通）；待該低電源供應電壓(LVdd)供應至高電源節點以加)後，此 時因為寫入用位元線（WBL)是扭非(高電源供應電壓取㈤），並且因 為第一 PMOS電晶體(P1)仍為〇N，所以節點A的電壓會降低至高電源 供應電壓(hvdd)扣減該第三醒〇31晶體（M3)的臨界電壓或該低電 源供應電壓(LVDD)兩者中之較大者，直到寫入週期結束該高電源供應電 壓(HVDD)供應至電壓節點_)。 (四）節點A原本儲存邏輯丨，而現在欲寫入邏輯〇 : 〇 在寫入動作發生前(寫入用字元線WWL為接地電壓），第一 PM〇s 電晶體(P1)為0N(導通）’該高電源供應電壓(HVDD)供應至電壓節點 (VH)。虽寫入用字元線(舊邮L〇w(接地電壓)轉只㈣高電源供應電 壓HVdD) ’且該寫入用字元線(WWL)的電壓大於第三nm〇s電晶體 (M3)的臨界電壓時，第三NMOS電晶體（M3)由〇FF(截止)轉變為 〇N(導通）’此時因為寫入用位元線（WBL)是Low (接地電壓），所 以會將即點A放電而完成邏則的寫人動作，直到寫人聊結束。在 此值得注意岐’該高電壓_呢賊人初_猶舰電源供應 〇 電邮Vdd)之傅’而於寫人週麟束制具有該高電雜應電壓 (hvdd)之位準。 緊接著依雙埠SRAM晶胞之二種儲存資料狀態說明第6圖之本發 明較佳實施例如何完成讀取動作。 (一）節點A儲存邏輯〇Before the write operation occurs (the write word line WWL is the ground voltage), the first NMOS transistor (M1) is turned ON (the high power supply voltage (HVdd) is supplied to the high voltage node (VH: ^Because the first NM0S transistor (M1) is 〇N, when the write operation starts, the write word line (WWL) turns from Low (ground voltage) to High (high power supply voltage HVDD). When the voltage of the word line (boundary ^) is greater than the threshold voltage of the third _8 transistor (M3), the third NMOS transistor (M3) is turned from OFF (turned off) to ON (conducted φ pass), Because the write bit line (WBL) is High (high power supply voltage HVdd); since the high voltage node (VH) drops from the high power supply voltage (HVdd) level to the low power supply voltage ( The level of LVDD) helps the first pm〇S transistor (P1) to change from OFF (off) to 〇N (on), and the first PM〇s transistor (8) to be converted from 〇FF (off) When ON (conducting) (since node B is changed toward L〇w direction, when the voltage level of node B drops enough to turn on the first PM〇s transistor (pl), the first pM〇s transistor (P1) is by OF F is converted to (0N), and the node a can be charged to a high power supply voltage (hvdd) to deduct the threshold voltage of the third NMOS transistor (M3) or the low power supply φ pressure (LVdd). The larger one, and complete the write operation of logic 1. It is worth noting here that since the high voltage node (VH) has the level of the low power supply voltage (lvdd) at the beginning of writing, the write cycle is in the write cycle. After the end, it has the level of the high power supply voltage (HVdd), so after the end of the write cycle, the node A will be charged to the level of the high power supply voltage (HV〇d). The logic 丨 is originally stored, and now I want to write logic 1: before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor (P1) is 0N (on)' the high power supply The voltage (HVDD) is supplied to the voltage node (VH). When the write word line (WWL) is turned from Low (ground voltage) to High (high power supply voltage HVDD), and the write word line (WWL) When the voltage is greater than the threshold voltage of the third NMQS transistor 201027532 (M3), the third transistor (M3) is changed from 〇FF (off) to ON (on) After the low power supply voltage (LVdd) is supplied to the high power supply node to be added, at this time, since the write bit line (WBL) is twisted (high power supply voltage is taken (5)), and because the first PMOS transistor (P1) is still 〇N, so the voltage of node A will decrease to a high power supply voltage (hvdd) minus the threshold voltage of the third awake 31 crystal (M3) or the low power supply voltage (LVDD) Larger, the high power supply voltage (HVDD) is supplied to the voltage node _) until the end of the write cycle. (4) Node A originally stores the logic 丨, but now wants to write the logic 〇: 前 Before the write operation occurs (the write word line WWL is the ground voltage), the first PM 〇s transistor (P1) is 0N. (Conduction) 'This high power supply voltage (HVDD) is supplied to the voltage node (VH). Although the write word line (old mail L〇w (ground voltage) is only (4) high power supply voltage HVdD) 'and the write word line (WWL) voltage is greater than the third nm 〇s transistor (M3 When the threshold voltage is applied, the third NMOS transistor (M3) is changed from 〇FF (off) to 〇N (on). At this time, since the write bit line (WBL) is Low (ground voltage), That is, point A discharges and completes the writing action of the logic until the end of the chat. It is worth noting that the high voltage _ thief first _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The preferred embodiment of the present invention of Figure 6 illustrates how the read operation is accomplished, in accordance with the two stored data states of the dual SRAM cell. (1) Node A stores logic〇
為Hlgft(鬲電源供應電壓 hvdd)。當讀取動作開始時，讀取用字元線 準， 晶體 ;接地雙之電壓辦轉為High(高電源供應電|HVDD)， 201027532 且當該讀取用字元線(RWL)的電壓大於該讀取用選擇電晶體(MRS)之 臨界電壓時，讀取用選擇電晶體(MRS)由OFF(截止)轉變為ON(導通）， 此時由於節點B為High，反相電晶體(MINV)為ON(導通），因此，會 在讀取用位元線(RBL)、讀取用選擇電晶體(MRS)、反相電晶體 (MINV)、及接地間形成電流路徑，此電流路徑即會使讀取用位元線 (RBL)之電壓位準降低，藉此即可感測出節點a係儲存邏輯〇之資料， 並完成邏輯0的讀取動作。 (二）節點A儲存邏輯1 在讀取動作發生前(讀取用字元線(RWL)為低於接地電壓之電壓位 準(例如-0.5伏特)），寫入用字元線(WWL)為接地電壓，第二NMOS電 晶體(M2)為ON (導通）’第二PMOS電晶體(P2)為OFF(截止），節點B 為Low (接地電壓）。當讀取動作開始時，讀取用字元線(RWL)由低 於接地電壓之電壓位準轉為High(高電源供應電壓HVDD)，且當該讀取 用字元線(RWL)的電壓大於該讀取用選擇電晶體(MRS)之臨界電壓 時’讀取用選擇電晶體(MRS)由OFF(截止)轉變為ON(導通），此時由於 節點B為Low (接地電壓），反相電晶體(MINV)為〇FF(戴止），因此， 並不會在讀取用位元線(RBL)、讀取用選擇電晶體(MRS)、反相電晶體 (MINV)、及接地間形成電流路徑，結果，讀取用位元線^之電壓位 準月b平穩地保持在High狀態’藉此即可感測出節點a係儲存邏輯1之 資料，並完成邏輯1的讀取動作。 第6圖所示之本發明第1實施例，於寫入操作時之HSpiCE暫態分 析模擬結果，如第7圖所示，其係以ievei 49模型且使用TSMC 0.35 微米CMOS製程參數加以模擬，由該模擬結果可註實，本發明所提出 之寫入操作時降低電源電壓之雙埠SRAM，能藉由寫入操作時降低電 源電壓，以有效避免習知具單一位元線之雙埠靜態隨機存取記憶體晶 胞存在寫入邏輯1相當困難之問題。 12 201027532 最後’說明本發明所提出之寫入操作時降低電源電壓之雙埠SRAM 如何藉由降低非選擇(nonselected)雙埠SRAM晶胞之漏電流(leaking current) ’而達成降低讀取干擾及提高讀取可靠度之功效。於讀取操作 期間，非選擇雙埠SRAM晶胞之讀取用選擇電晶體(MRS)係呈戴止 (OFF)狀態，但該讀取用選擇電晶體(MRS)截止時仍會有漏電流存在， 該漏電流路徑係形成於讀取用位元線(RBL)、讀取用選擇電晶體 (MRS)、反相電晶體(MINV)及接地之間，此漏電流路徑即會產生讀取 • 干擾並降低讀取可靠度。本發明係藉由將該讀取用字元線設定成 .⑩ 低於接地電壓但商於產生閘極引發沒極、;_(GIDL)電流之電壓位準(例 如-0.5伏特）’以降低非選擇雙埠SRAM晶胞之漏電流。事實上電晶體 截止時之漏電流(leaking CUITent)主要是來自次臨界電流(subthresh〇ld current)，於20〇5年3月8日公告之美國專利公告第US6865U9號專利 案第3(A)及3⑻圖中，即揭露對於nm〇s電晶體而言，閘源極電壓為 -0.1伏特時之次臨界電流__極電壓為Q伏特時之次臨界電流的 1%，因此，藉由將該讀取用字元線(RWL)設定成低於接地電壓但高於 產生閘極引發汲極洩漏(GIDL)電流之電壓位準(例如_〇 5伏特），確實可 φ A幅地降低非選擇雙埠SRAM晶胞之漏電流，並能謀求降低讀取干擾 及提高讀取可靠度之功效。 (11)待機模式(standby mode) 此時该第一控制信號(SAP)為邏輯高位準，而該第二控制信號(SAN) 鱗輯恤準，該賴高位準之鱗—控制信娜Ap)可使得第一偏壓 電路(2)中之第五PMOS電晶體(P24) 0FF(截止），並使得第六pM〇s電 晶f(P25)〇N(導通）’於是可將該低電源供應電壓(LVdd)供應至該高電 m_(vh);而該賴低轉之該第三控制錢(SAN)可使得第二偏 壓電路(3)中之第二nm〇s電晶體(M3 u 〇FF(截止)，由於此時第二偏壓 13 201027532 電路(3)中之第四nmos電晶體(M32)仍為0N(導通），於是可將該低電 壓節點(VL)維持在該第四]^河〇8電晶體如32)之臨界電壓的位準。 接下來說明本發明於待機模式(standby mode)時如何減少漏電流， 請參考第8圖，第8圖表示了第6圖雙埠SRAM處於待機模式時所產 生之各次臨界漏電流(subthreshold leakage current)Il、L2、I3 和 μ，其 中假設雙埠SRAM晶胞中之儲存節點A為邏輯L〇w(接地電壓），而反 相儲存節點(B)為邏輯High(高電源供應電壓HVDD)。請再參考第5圖之 . 先前技藝與第8圖之本發明實施例，關於流經寫入用選擇電晶體(Mws) .❹ 之漏電流^，由於待機模式時寫入用字元線(WWL)係為接地電壓，因 此流經寫人用選擇電晶體(MWS)之漏電流〗丨與第5 @之先前技藝（先 前技藝中之NMOS電晶體M3即相當於本發明實施例中之該寫入用選 擇電晶體MWS)具有相同的漏電流；關於流經第一 pM〇s電晶體(ρι) 之漏電流12 ’由於待顧鱗魏賴謂點(γΜ)储有低電源供應 電壓(lvdd)之電壓位準’該低電源供應電壓(LVdd)之電壓位準係小於該 尚電源供應電壓(HVDD)，又因驗反擔存節點B為邏輯High(高電源 供應電壓hvdd)，因此流經第—PM〇s電晶體(ρι)之漏電、流12係遠小 φ 於第5圖之先前技藝者（先前技藝中之PMOS電晶體P1即相當於本發 明實施例中之該第- PM0S電晶體pl);關於流經第二丽〇8電晶體 (M2)之漏糕D，由於雜赋喃低電壓節點㈤係轉在該第四 NMOS電晶體(M32)之臨界輕的辦，又因為該齡_ a為邏輯 Low(接地電壓）’因此流經該第二聰〇|5電晶體㈣)之漏電流i3係遠 小於第5圖之先前技藝者（先前技藝中^NM〇s電晶體m2即相當於 本發明實施财之該第二_S電· Μ2) ; 電晶體(MRS)之漏電流Ι4 ’由於待機模式時該讀取用字元線(rwl)係設 定成低於接地電壓(例如-0.5伏特)之電壓位準，又因為該反相電晶體 (MINV)導通’於疋可將賴取用選擇電晶體障&之源極電壓固定在 201027532 該第四NMOS電晶體(M32)之臨界電壓的位準，因此可大幅減少流經該 讀取用選擇電晶體(MRS)之漏電流14。 經由以上分析可知，本發明於待機模式(standby m〇de)時確實可有 效減少漏電流。 【第2實施例】 根據上述之再一目的，本發明提出另一種寫入操作時降低電源電壓 之雙痒SRAM ’其僅於寫入邏輯！時方降低電源電壓，該寫入操作時 •降低電源電壓之雙埠靜態隨機存取記憶體係包括一記憶體陣列，該記 〇 憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列 記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞;複 數個一第一偏壓電路（2’），每一行記憶體晶胞設置一個第一偏壓電路 (2’）；以及第二偏壓電路（3)。 為了便於說明起見’第9圖所示之寫入操作時降低電源電壓之雙埠 SRAM僅以一個記憶體晶胞（1)、一條寫入用字元線（wwl)、一 條讀取用字元線（RWL)、一條寫入用位元線(WBL)、一條讀取用位元 線(RBL)第—偏壓電路（2，）錢-第三偏壓電路⑴做為實施例 參 來說明。該έ己憶體晶胞（1)係包括一第一反相器(由第一 PMOS電晶 體Ρ1與第一 NMOS電晶體Ml所組成）、一第二反相器(由第二PM〇s 電晶體P2與第二NM〇s電晶體M2所組成）、一寫入用選擇電晶體 (MWS)、—讀取用選擇電晶體(MRS)、以及一反相電晶體(MINV)，其 中，該第一反相器和該第二反相器係呈交互耦合連接，亦即該第一反 相器之輸出（即節點A)係連接該第二反相器之輸入，而該第二反相器之 輸出（即節.點B)則連接該第一反相器之輸人，並且該第一反相器之輸出 (節點AK_於儲存SRAM晶胞之資料，而該第二反相器之輸出（節點 B)則用於儲存SRAM晶胞之反相資料，該寫入用選擇電晶體(Mws)， 係連接在該儲存節點(A)與寫入用位元線(WBL)之間，且閘極連接至寫 15 201027532 入用字元線(WWL); —讀取用選擇電晶體(MRS)，其一端連接至讀取用 位元線(RBL)，另一端與反相電晶體(MINV)相連接，而閘極則連接至讀 取用字元線(RWL);以及一反相電晶體(MINV)，其一端與該讀取用選 擇電晶體(MRS)相連接’另··-端連接至接地，而閘極則連接至反相儲存 節點(B)。 請再參考第9圖’該第一偏壓電路(2’)係由一第三pm〇s電晶體 (P21)、一第四PMOS電晶體(P22)、一第三反相器(123)、一第五PMOS 電晶體(P24)、一第六PMOS電晶體(P25)以及四第三反相器(〇6)所組 參成，該第三PMOS電晶體(P21)之源極、閘極與汲極係分別連接至該第 五PMOS電晶體(P24)之;及極端、該寫入用位元線（WBL)與一高電壓 節點(VH);該第四PMOS電晶體(P22)之源極、閘極與汲極係分別連接 至一低電源供應電壓(LVDD)、該第三反相器(123)之輸出端與該高電壓節 點(VH)，該第三反相器(123)之輸入端則用以接收該寫入用位元線 (WBL) ’該第五PMOS電晶體(P24)之源極、閘極與沒極係分別連接 至一咼電源供應電壓(hvdd)、一第一控制信號(SAP)與該第三PM〇s電 晶體(P21)之源極端；該第六PM〇s電晶體(p25)之源極、閘極與没極 m 係分別連接至該低電源供應電壓(lvdd)、該第四反相器(126)之輸出端與 該面電壓節點(VH)，該第四反相n(i23)之輸人端顧以接收該第一控 制信號(SAP)。再者’該第二偏壓電路⑶係由一第三丽〇8電晶體(M3i) 以及-第四NM〇S電晶體(M32)所組成，該第三應〇8電晶體(觀） 之源極、閘極與祕係分猶接至接地電壓、該第二控制信號(⑽) 與該低電壓節點㈣’該第凹nm〇s電晶體(M32)之雜係連接至接地 電壓，而閘極與沒極係連接在一起，並連接至該低電壓節點⑽）。 在此值得注意的是’本發明為了防止感測容限降低，於是將該讀取 用字元線(RWL)於非選擇時之電壓鱗設定成低於接地電壓(例如_〇.5 伏特）’亦# ’該讀取用字元線(RWL)於讀取操作期間係設定為該高電 201027532 ， 源供應電_、）’而於讀取操作以外之期間則設定為低於接地電壓 之電壓位蝴如_〇.5 _，至於該寫人科元線(WWL)於寫入操作期 間係設定為該高電源供應電雖VDD)，而於寫入操作 定為接地電壓。 π j⑴叹 本發明峨ihH糊，可融翻^人邏輯i时降低電源 電壓以有效避免寫人邏輯！相當困難之問題。由於其寫人原理相仿於 第1實施例’在此不再贅述。 【發明功效】 Ό 效 Ο) 本發明所提出之寫人操作畴低魏輕之雙埠SRAM，具有如下功 由於本發明所提出之寫入操作時降低電源 電壓之雙郫RAM於讀取操作時，雜讀取財元線障）於非選擇 ncmselected)時之電驗準設定成低於接地電壓(例如_〇·5伏特），結果， =由大幅地降低非選擇(n〇nselected)雙埠SRAM晶胞之漏電流二有 效達成降低讀取干擾及提高讀取可靠度等功效； (2) 低次臨界漏電流：由於本發明所提出之寫人操作時降低電源電壓之雙 SRAM於待機模式時，高電壓節點㈣係、為低電源供應電壓d)之電 2準’而低電壓節點(VL)係峡在該第四丽〇8電晶體_2)之臨界 、的位準’且讀取用字元線(RWL)之電壓位準係固定在低於接地電壓 (二列如-0.5伏特）之電壓位準，因此本發明所提出之寫入操作時降低電源 電壓之雙埠SRAM亦賤低她界漏電流之功效； (3) 避免寫人邏輯1雜之_··本發明所提出之寫人操作時降低電源· 之雙埠SRAM於‘寫入操作時，可藉由寫入操作時降低高電壓節點_) 之電壓位準以有效避免習知具單一位元線之雙埠靜態隨機存取記憶體 晶胞存在寫入邏輯1相當困難之問題。 ,雖然本發明铜揭露並描述了所選之較佳實關，但舉凡熟悉本技 術之^士可明瞭任何形式或是細節上可能的變化均未脫離本發明的精 神與，圍。目此’所有細技術射狀改變都包括在本發明之申請 專利範圍内。 17 201027532 【圖式簡單說明】 第1圖係顯示習知6T靜態隨機存取記憶體晶胞之電路示意圖. 第2圖係顯示習知6T靜態隨機存取記憶體晶胞之寫入動$時序 第3圖係顯示習知5Τ靜態隨機存取記憶體晶胞之電路示意圖.， 第4圖係顯示習知5Τ靜態隨機存取記憶體晶胞之寫入動作時序圖； 第5圖係顯示習知雙雜態隨機存取記憶體晶胞之電路示意圖； 第6圖軸示本發㈣1實施觸提丨之寫人操作畴低電源電壓之 雙埠SRAM之電路示意圖；For Hlgft (鬲 power supply voltage hvdd). When the read operation starts, the read word line is normal, the crystal; the ground double voltage is turned to High (high power supply | HVDD), 201027532 and when the read word line (RWL) voltage is greater than When the threshold voltage of the selective transistor (MRS) is read, the read selection transistor (MRS) is turned from OFF (turned) to ON (on), and at this time, since the node B is High, the inverted transistor (MINV) ) is ON, so a current path is formed between the read bit line (RBL), the read select transistor (MRS), the inverting transistor (MINV), and the ground. This current path is The voltage level of the read bit line (RBL) is lowered, thereby sensing that the node a stores the data of the logical volume and completes the logic 0 reading operation. (2) Node A stores logic 1 before the read operation occurs (the read word line (RWL) is a voltage level lower than the ground voltage (for example, -0.5 volt)), and the write word line (WWL) For the ground voltage, the second NMOS transistor (M2) is ON (on), the second PMOS transistor (P2) is OFF (off), and the node B is Low (ground voltage). When the read operation starts, the read word line (RWL) is turned from the voltage level lower than the ground voltage to High (high power supply voltage HVDD), and when the read word line (RWL) voltage When the threshold voltage of the read selective transistor (MRS) is larger than the threshold voltage of the read select transistor (MRS) is turned from OFF (turned off) to ON (on), at this time, since the node B is Low (ground voltage), The phase transistor (MINV) is 〇FF (wearing), so it is not used in the read bit line (RBL), the read select transistor (MRS), the inverting transistor (MINV), and the ground. As a result, the current path is formed, and as a result, the voltage level qu of the bit line of the reading bit b is smoothly maintained in the High state, thereby sensing that the node a stores the data of the logic 1 and completes the reading of the logic 1. action. The first embodiment of the present invention shown in FIG. 6 shows the simulation results of the HSpiCE transient analysis during the write operation, as shown in FIG. 7, which is simulated by the ievei 49 model and using TSMC 0.35 micron CMOS process parameters. It can be noted from the simulation result that the double-turn SRAM for reducing the power supply voltage during the write operation proposed by the present invention can reduce the power supply voltage by the write operation, thereby effectively avoiding the double-static static with a single bit line. The presence of random access memory cells in writing logic 1 is quite difficult. 12 201027532 Finally, how to reduce the read interference by reducing the leakage current of the nonselected dual-SRAM cell by reducing the leakage current of the non-selected dual-SRAM cell during the write operation of the present invention Improve read reliability. During the read operation, the read select transistor (MRS) of the non-selected double-turn SRAM cell is in an OFF state, but there is still leakage current when the read select transistor (MRS) is turned off. There is a leakage current path formed between the read bit line (RBL), the read select transistor (MRS), the inverting transistor (MINV), and the ground, and the leakage current path is read. • Interfere and reduce read reliability. The present invention reduces the voltage level (eg, -0.5 volts) of the _(GIDL) current by setting the read word line to .10 lower than the ground voltage. The leakage current of the non-selected double-turn SRAM cell. In fact, the leakage current (CUITent) of the transistor is mainly from the subcritical current (subthresh〇ld current), and the US Patent Publication No. US6865U9 Patent No. 3(A) published on March 8, 20, 2005. And 3 (8), it is revealed that for the nm〇s transistor, the subcritical current __ pole voltage when the gate source voltage is -0.1 volt is 1% of the subcritical current at Q volts, therefore, The read word line (RWL) is set lower than the ground voltage but higher than the voltage level at which the gate-induced drain leakage (GIDL) current is generated (for example, _〇5 volts), and the φ A amplitude can be reduced. Select the leakage current of the double-埠SRAM cell, and can reduce the read interference and improve the read reliability. (11) standby mode (standby mode) At this time, the first control signal (SAP) is a logic high level, and the second control signal (SAN) scales the standard, the scale of the high level - control Xinna Ap) The fifth PMOS transistor (P24) in the first bias circuit (2) may be made 0FF (off), and the sixth pM 〇s electro-crystal f(P25) 〇 N (on) may be made low. A power supply voltage (LVdd) is supplied to the high power m_(vh); and the third control money (SAN) of the low turn enables the second nm 〇s transistor in the second bias circuit (3) (M3 u 〇 FF (off), since the fourth nmos transistor (M32) in the second bias 13 201027532 circuit (3) is still 0N (on), the low voltage node (VL) can be maintained The level of the threshold voltage in the fourth] ^ 〇 8 transistor such as 32). Next, how to reduce the leakage current in the standby mode of the present invention is described. Please refer to FIG. 8 and FIG. 8 shows the critical leakage current generated by the double-turn SRAM in the standby mode in FIG. 6 (subthreshold leakage). Current)Il, L2, I3, and μ, assuming that the storage node A in the double-埠SRAM cell is a logic L〇w (ground voltage), and the inverting storage node (B) is a logic high (high power supply voltage HVDD) . Referring to FIG. 5 again, the prior art and the embodiment of the present invention in FIG. 8 relate to the leakage current ^ flowing through the selective transistor (Mws) for writing, due to the writing word line in the standby mode ( WWL) is a ground voltage, so it flows through the prior art of the leakage current of the selected transistor (MWS) and the 5th prior art (the NMOS transistor M3 in the prior art is equivalent to the embodiment of the present invention) The write selection transistor MWS) has the same leakage current; the leakage current 12' flowing through the first pM〇s transistor (ρι) stores a low power supply voltage due to the point (γΜ) The voltage level of lvdd) 'the voltage level of the low power supply voltage (LVdd) is less than the power supply voltage (HVDD), and because the verification of the storage node B is logic high (high power supply voltage hvdd), Leakage through the first PM〇s transistor (ρι), stream 12 is much smaller than the prior art of Figure 5 (the prior art PMOS transistor P1 is equivalent to the first in the embodiment of the invention - PM0S transistor pl); about the leakage cake D flowing through the second Radisson 8 transistor (M2), due to the low voltage node (5) In the fourth NMOS transistor (M32), the critical light is handled, and because the age _ a is the logic Low (the ground voltage), the leakage current i3 flowing through the second 〇 〇 5 transistor (4) is far away. It is less than the prior art of FIG. 5 (the prior art ^NM〇s transistor m2 is equivalent to the second _S electric Μ2 of the implementation of the present invention); the leakage current of the transistor (MRS) Ι4 ' due to the standby mode When the read word line (rwl) is set to a voltage level lower than the ground voltage (for example, -0.5 volts), and because the inverting transistor (MINV) is turned on, the voltage can be selected. The source voltage of the crystal barrier & is fixed at the threshold voltage of the fourth NMOS transistor (M32) in 201027532, so that the leakage current 14 flowing through the read selection transistor (MRS) can be greatly reduced. From the above analysis, it can be seen that the present invention can effectively reduce leakage current in the standby mode. [Second Embodiment] According to still another object described above, the present invention proposes another double-itch SRAM which reduces the power supply voltage during a write operation, which is only written logic! When the power supply voltage is lowered, the double-static static random access memory system that reduces the power supply voltage during the write operation includes a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows of memory cells. Each cell consists of a memory cell and each row of memory cells each including a plurality of memory cells; a plurality of first bias circuits (2'), each row of memory cells set a first a bias circuit (2'); and a second bias circuit (3). For the sake of convenience, the double-sided SRAM that reduces the power supply voltage during the write operation shown in FIG. 9 has only one memory cell (1), one write word line (wwl), and one read word. A line (RWL), a write bit line (WBL), a read bit line (RBL) first-bias circuit (2,) money-third bias circuit (1) as an embodiment See the instructions. The memory cell (1) includes a first inverter (composed of the first PMOS transistor 与1 and the first NMOS transistor M1) and a second inverter (by the second PM 〇s) a transistor P2 and a second NM〇s transistor M2), a write select transistor (MWS), a read select transistor (MRS), and an inverting transistor (MINV), wherein The first inverter and the second inverter are connected in an alternating coupling manner, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the second The output of the phase comparator (ie, point B) is connected to the input of the first inverter, and the output of the first inverter (node AK_ is stored in the SRAM cell, and the second inversion) The output of the device (node B) is used to store the inverted data of the SRAM cell, and the write select transistor (Mws) is connected to the storage node (A) and the write bit line (WBL). Between, and the gate is connected to the write 15 201027532 input word line (WWL); - read select transistor (MRS), one end of which is connected to the read bit line (RBL), the other end and the reverse phase Crystal (MINV) connection The gate is connected to the read word line (RWL); and an inverting transistor (MINV), one end of which is connected to the read select transistor (MRS), and the other end is connected to the ground. And the gate is connected to the inverting storage node (B). Please refer to Figure 9 again. The first bias circuit (2') is composed of a third pm 电s transistor (P21), a fourth PMOS transistor (P22), a third inverter (123), a fifth PMOS transistor (P24), a sixth PMOS transistor (P25), and a fourth third inverter (〇6) The source, the gate and the drain of the third PMOS transistor (P21) are respectively connected to the fifth PMOS transistor (P24); and the terminal, the write bit line (WBL) and the a high voltage node (VH); a source, a gate and a drain of the fourth PMOS transistor (P22) are respectively connected to a low power supply voltage (LVDD) and an output of the third inverter (123) And the high voltage node (VH), the input end of the third inverter (123) is configured to receive the write bit line (WBL) 'the source and gate of the fifth PMOS transistor (P24) The pole and the poleless are respectively connected to a power supply voltage (hvdd), a first a signal (SAP) and a source terminal of the third PM〇s transistor (P21); a source, a gate and a gate m of the sixth PM〇s transistor (p25) are respectively connected to the low power supply a voltage (lvdd), an output of the fourth inverter (126) and the surface voltage node (VH), and the input end of the fourth inverted n(i23) receives the first control signal (SAP) Furthermore, the second bias circuit (3) is composed of a third 〇8 transistor (M3i) and a fourth NM 〇S transistor (M32), the third 〇8 transistor (view) The source, the gate and the secret are connected to the ground voltage, the second control signal ((10)) and the low voltage node (4) 'the first recessed nm〇s transistor (M32) are connected to the ground voltage And the gate is connected to the immersion system and connected to the low voltage node (10). It is worth noting here that the present invention prevents the sensing tolerance from being lowered, so that the voltage scale of the read word line (RWL) at the time of non-selection is set lower than the ground voltage (for example, _〇.5 volt). '也#' The read word line (RWL) is set to the high power 201027532 during the read operation, and the source supply power _,)' is set to be lower than the ground voltage during the period other than the read operation. The voltage level is as _〇.5 _, and the write unit line (WWL) is set to the high power supply VDD during the write operation, and the write operation is set to the ground voltage. π j (1) sigh The invention 峨ihH paste, can be turned over when the human logic i reduce the power supply voltage to effectively avoid writing logic! Quite difficult problem. Since the principle of writing is similar to that of the first embodiment, it will not be described again. [Effects of the Invention] The effect of the present invention is to write a human-operating domain with a low-frequency Shuangshuang SRAM, which has the following work. Due to the read operation of the present invention, the double-turn RAM of the power supply voltage is reduced during the read operation. , the miscellaneous reading of the financial element line barrier) when the non-selected ncmselected) is set to be lower than the ground voltage (for example, _ 〇 · 5 volts), and the result is greatly reduced by non-selective (n〇nselected) The leakage current of the SRAM cell is effectively achieved to reduce the read interference and improve the read reliability; (2) Low-threshold leakage current: the dual SRAM that reduces the power supply voltage during the write operation of the present invention is in standby mode. When the high voltage node (four) is the low power supply voltage d), the low voltage node (VL) is at the critical level of the fourth Radisson 8 transistor_2) and reads The voltage level of the fetch word line (RWL) is fixed at a voltage level lower than the ground voltage (two columns such as -0.5 volts), so the double-SRAM which reduces the power supply voltage during the write operation proposed by the present invention is also Depreciate the effect of her leakage current; (3) Avoid writing logic 1 _·· this According to the description of the write-down operation of the double-turn SRAM in the write operation, the voltage level of the high-voltage node _ can be reduced by the write operation to effectively avoid the conventional single-bit line. It is quite difficult to write a logic 1 in a double-埠 static random access memory cell. While the invention has been described and described with respect to the preferred embodiments of the present invention, it is understood that the invention may be modified in any form or detail without departing from the spirit and scope of the invention. It is intended that all of the detailed technical changes are included in the scope of the patent application of the present invention. 17 201027532 [Simple diagram of the diagram] Figure 1 shows the circuit diagram of the conventional 6T SRAM cell. Figure 2 shows the write timing of the conventional 6T SRAM cell. Figure 3 is a schematic diagram showing the circuit of a conventional 5 Τ static random access memory cell. Figure 4 is a timing chart showing the write operation of a conventional 5 Τ static random access memory cell; A schematic diagram of a circuit of a double-hybrid random access memory cell; FIG. 6 is a schematic diagram of a circuit of a dual-SRAM of a low-supply voltage of a human touch domain;
第7圖係顯示本發明第1實施例所提出之寫入操作時降低電源電壓之 雙埠SRAM之寫入動作時序圖； 第8圖係顯示第6圖雙埠SRam於待麵式時所產生之各次臨界漏電 流； 第9圖係顯TF本發明第2實施觸提^寫人操作瞒低電源電壓之 雙埠SRAM之電路示意圖。 【主要元件符號說明】 P1 第一 PMOS電晶體 P2 第二PMOS電晶體 Ml 第一 NMOS電晶體 M2 第二NMOS電晶體 M3 第三NMOS電晶體 M4 第四NMOS電晶體 MWS 寫入用選擇電晶體 MRS 讀取用選擇電晶體 MINV 反相電晶體 WL 字元線 WWL 寫入用字元線 RWL 讀取用字元線 BL 位元線 BLB 互補位元線 WBL 寫入用位元線 RBL 讀取用位元線 A 儲存節點 B 反相儲存節點 hvdd 高電源供應電壓 LVdd 低電源供應電壓 SAP 第一控制信號 SAN 第二控制信號 18 201027532 P21 第三PMOS電晶體 P22 第四PMOS電晶體 123 第三反相器 P24 第五PMOS電晶體 P25 第六PMOS電晶體 126 第四反相器 M31 第三：NMOS電晶體 M32 第四NMOS電晶體 VH 高電壓節點 VL 低電壓節點 1 SRAM晶胞 2 第一偏壓電路 3 第二偏壓電路 Vdd 電源電壓 2， 第一偏壓電路 *❿ 19Fig. 7 is a timing chart showing the writing operation of the double-turn SRAM for reducing the power supply voltage in the write operation proposed in the first embodiment of the present invention; Fig. 8 is a view showing the generation of the double-sided SRam in the standby mode when the sixth figure is shown. Each of the critical leakage currents; Figure 9 is a schematic diagram of the circuit of the double-turn SRAM of the second embodiment of the present invention. [Description of main component symbols] P1 first PMOS transistor P2 second PMOS transistor M1 first NMOS transistor M2 second NMOS transistor M3 third NMOS transistor M4 fourth NMOS transistor MWS write selection transistor MRS Read selection transistor MINV Inverting transistor WL word line WWL Write word line RWL Read word line BL Bit line BLB Complementary bit line WBL Write bit line RBL Read bit Yuan line A storage node B inverting storage node hvdd high power supply voltage LVdd low power supply voltage SAP first control signal SAN second control signal 18 201027532 P21 third PMOS transistor P22 fourth PMOS transistor 123 third inverter P24 Fifth PMOS transistor P25 Sixth PMOS transistor 126 Fourth inverter M31 Third: NMOS transistor M32 Fourth NMOS transistor VH High voltage node VL Low voltage node 1 SRAM cell 2 First bias circuit 3 second bias circuit Vdd power supply voltage 2, first bias circuit *❿ 19