TWM391711U - Single port sram having a discharging path - Google Patents

Description

M391711 V. New description: [New technical field] This is a static random access memory (SRAM) with a discharge path, especially when it is high in memory capacity. A static random access memory capable of high reliability and high stability write operations. [Prior Art] Memory plays an indispensable role in the computer industry. Generally, memory can be classified into dynamic random access memory (DRAM) and static random access memory (SRAM) according to whether it can save data after the power is turned off. Dynamic random access memory (DRAM) has the advantages of small area and low price, but it must be refreshed from time to time to prevent the -becay material from being lost due to leakage current, resulting in high speed and power consumption. Greatly missing. On the contrary, the SRAM (the operation of the 511^ is relatively simple and does not require an update operation, so it has the advantages of high speed and low power consumption. It is a semiconductor memory device used in mobile electronic devices represented by mobile phones. 'SRAM is the mainstream. This is because the SRAM touches the small size, suitable for continuous talk time, continuous standby time as long as possible. Static random access memory (SRAM) mainly includes - memory array (memory array), The memory disconnect is composed of a plurality of memory cells (a 〇 〇fr〇ws 〇f me ory cells) and a plurality of memory cells (a pi cells) Each row of memory cells includes a plurality of hidden ab cells' complex word lines (WQfdline) 'every __ character lines to multiple columns of memory cells, and complex bits For the pair, each bit line pair corresponds to a plurality of rows of cells, and each bit line pair consists of a bit line and a 3 M391711 complementary bit line. The 6T static random access memory (SRAM) cell is shown. Circuit diagram 'where PMOS transistors P1 and p2 are called load transistors (1〇ad café), NMOS transistors M1 and M2 are called drive transistors (driving coffee), and transistors M3 and JVM are called Access to the electron crystal access (access), the milk is the word line (w〇rd line) ' and BL· and BLB are the bit line and the complementary line (complementaiy bitline) respectively due to the SRam unit cell Six transistors are required, and the current drive capability ratio between the drive transistor and the access transistor (ie, the cell ratio (cdl)) is usually set between 2 and 3', resulting in the difficulty of enthalpy accumulation and price. Higher Defects. The 6T SRAM cell shown in Figure 1 shows the HSpiCE transient analysis simulation results during the write operation. As shown in Figure 2, it is modeled on the ievei 49 and uses TSMC 0.35 micron CMOS. The process parameters are simulated (the zero-substrate bias voltage values Vtho of the pM〇s transistor and the Radisson 3 transistor are -0.7866083V and 0.582913V, respectively), wherein the channel width to length ratio of the PMOS transistor P and P2 are respectively Both are (W/L)=(1[mi/1 4μιη), and the width and length ratio of the channel of M1 and M2 are both The channel width to length ratio of the transistor 143 and the ^4 are both (Wei) = (1 button 111 / 〇. 35 哗).

One way to reduce the number of transistors in a 6T SRAM (SRAM^sa cell is disclosed in Figure 3. Figure 3 shows a static random access memory cell with only a single bit line). The circuit diagram of the cell is compared with the 6T SRAM cell of Figure 1 'This 5T SRAM cell is one less transistor and one less than the 6T SRAM cell. Bit line, except that the SRAM cell has a write logic 1 equivalent without changing the channel width-to-length ratio of the PMOS transistors Pi and P2 and the NM〇s transistors VQ, M2, and M3. Difficult problem. Consider the case where the left side of the memory cell, point A, originally stores the logical 〇, since the charge of node a is only transmitted from the bit line (BL) alone, it is difficult to write the logic previously written in node a. The cover is written as logic 1. The 5T static random access memory cell shown in Figure 3, the HSPICE 4 M391711 transient analysis simulation result during the write operation, as shown in Figure 4, is used in the level 49 model and used. TSMC 0.35 micron CMOS process parameters are simulated (its pM〇s transistor and NM) The zero-substrate bias voltage value Vth〇 of the OS transistor is -0.7866083V and 0.582913V, respectively, wherein the channel width to length ratio of the PMOS transistor P and P2 are both, and the channel width and length of the NMOS transistors M1 and M2 are long. The ratio is (W/L)=(2Mm/0.35gm), and the channel width-to-length ratio of the NMOS transistor M3 is (w/L)=(1.3Mm/0.35pm), which can be confirmed by the simulation result. It is quite difficult to write logic 1 in a 5T SRAM cell with a single bit line. So far, there are many 5T SRAM cells with a single bit line. For example, Non-Patent Document 1 (I. Carlson et al. A high density, low leakage, 5T SRAM for embedded caches,, 5 Solid-State Circuits Conference, 2004.

The 5T SRAM of ESSCIRC 2004· Proceeding of the 30th European, ρρ.215·218, 2004·) is due to the channel length and length of the two driving transistors, the two load transistors and one access transistor by redesigning the unit cell. Than to solve the write logic! Difficult problem, which causes damage to the symmetry relationship between the driving transistor and the load transistor in the original unit cell and is thus susceptible to process variation; Non-Patent Document 2 (M. Wieckowski et al., ''A novel five -transistor (5T) sram cell for high performance each; 5 IEEE Conference on SOC, pp. 1001-1002, 2005 ·) 5T SRAM is set by a long channel length access between two load transistors in the unit cell The transistor solves the problem of difficulty in writing logic 1', resulting in a lack of access speed; Patent Document 3 (June 1, 1986, TW M358390) reduces the power supply voltage during write operations. Random access memory (which is mainly represented as shown in Figure 5) can effectively solve the problem of writing logic 1 'only when writing operation, because high voltage node (VH) is supplied by high power supply voltage (hvdd) The lack of an effective discharge path in the process of dropping to a low power supply voltage (lvdd) results in problems such as low write reliability and low write stability at still memory capacity and/or high speed operation. space. 5 M391711 has a clock here. The main purpose of this creation is to propose a static random access memory with a circuit, which not only can effectively avoid the problem of writing logic, but also high memory capacity and / / High-speed operation can still have high reliability and high stability of the write operation. [New content] This paper proposes a static random access memory (SRAM) with a discharge path, which includes a memory array, a plurality of word lines, a plurality of bit lines, and a plurality of write voltage controls. The circuit (2) and the plurality of discharge paths (3) each of which has a write voltage control circuit and a discharge path (3). The write voltage (4) circuit (2) is used to indicate the logic of the selected logic 1 when the thief's control number (CTL) is selected. The surface is high-voltage node (the potential of (4) is discharged via the corresponding discharge noise-predetermined time' - the aspect - the low electrical test voltage (lVdd) is supplied to the high voltage node (VH), wherein the control signal (CTL) is a write enable (write

EnaWe, _ WE) signal, write data signal and corresponding word line drop) signal AND gate operation result, that is, only the write enable (Μ) signal, write the material minus Should it? The control line (CTL) is logically high when the it line (WL) touches the logic scale; the lake signal (ctl) of the secret line is the logical residual material representing the unselected write or non-human logic , the job - Wei Wei supply voltage (HVDD) supply the high voltage node (four). Silk, the surface of the surface, such as the circuit of the 單埠 static _ machine access record (four), not only can effectively avoid the problem of logical 丨 phase #, and even in high memory capacity, 佩 has high energy and high stability Sex write operation. [Embodiment] According to the above main object, the present invention proposes a static random random access memory with a discharge path. The static random access memory system with a discharge path includes a memory array. The memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells. 'Each column of memory cells and each row of memory cells each include a plurality of memory cells (1); a plurality of words a meta-line, each word line corresponding to one of a plurality of columns of memory cells; a plurality of bit lines, each bit line corresponding to one of a plurality of rows of memory cells; a plurality of write voltage controls a circuit (2); and a plurality of discharge paths (3), wherein 'each column memory cell is provided with a write voltage control circuit (2) and a discharge path (3) for convenience of explanation, as shown in FIG. The static random access memory has only one memory cell (1), one word line (WL), one bit line (BL), a write voltage control circuit (2), and A discharge path (3) is preferred The memory cell (1) includes a first inverter (composed of a first PMOS transistor P1 and a first NMOS transistor M1) and a second inverter (by a second). a PMOS transistor P2 and a second nm 〇S transistor M2) and a third nmos transistor (M3) 'where the first inverter and the second inverter are connected in an alternating manner, that is, The output of the first inverter (ie node A) is connected to the input of the second inverter, and the output of the first inverter (ie node B) is connected to the input of the first inverter, and The output of the first inverter (node A) is used to store the data of the SRAM cell, and the round of the second inverter (node B) is used to store the inverted data of the SRAM cell. The third NM〇s transistor (M3) is used as an access transistor, and its gate is connected to a pre-element (WL) 'the word line (WL) is selected (selected) It is a logic level with a high power supply voltage (HV〇d), and a non-selected (nonselected) logic low level with a ground voltage of 7 M391711. Please refer to FIG. 6 again. The write voltage control circuit (2) is composed of a third pm 电 transistor (P21), a fourth PMOS transistor (P22), and a third inverter (123). The source, the gate and the drain of the third PMOS transistor (P21) are respectively connected to the high power supply voltage (HVDD), a control signal (CTL) and a high voltage node (vh); The source, gate and immersion of the four PMOS transistors (P22) are respectively connected to a low power supply voltage (LVDD), an output of the inverter (123) and the high voltage node (vh), and the The input of the third inverter (123) is used to receive the control signal (CTL). The control signal (CTL) is an AND gate operation result of a Write Enable (WE) signal, a write data signal, and a corresponding word line (WL) signal, that is, only When the write enable (WE) signal, the write data signal, and the corresponding word line (wl) signal are both logic high level, the control signal (CTL) side is a logic high level; and the control is corresponding thereto. The signal (CTL) is a logic low level on behalf of the unselected write state or non-write logic 1, and a high power supply voltage (HVDD) is supplied to the high voltage node (VH). When the control signal (CTL) is a logic high level representing the write logic 1, the logic high level of the control signal (CTL) can cause the third PMOS transistor (P21) in the write voltage control circuit (2) OFF (off), and makes the fourth pm 〇S transistor (P22) ON (on), then the low power supply voltage (lvdd) can be supplied to the high voltage node (VH); and the control signal (CTL) In order to represent the unselected write state or the logic low level of the non-write logic 1, the logic low level of the control signal (CTL) can cause the third PMOS transistor in the write voltage control circuit (2) ( P21) ON, then the high power supply voltage (HVDD) can be supplied to the high voltage node (VH). 8 M391711 Please refer to FIG. 6 again. The discharge path (3) is composed of a fourth nmqs transistor (M31), a fifth NMOS transistor (M32) and a delay circuit (D33). a source, a gate and a drain of the transistor (M31) are respectively connected to a drain of the fifth NMOS transistor (M32), the control signal (CTL) and the high voltage node (γΗ); the fifth NMOS The source, the gate and the drain of the transistor (M32) are respectively connected to the ground, the output of the delay circuit (D33) and the source of the fourth NMOS transistor (M31), and the delay circuit (D33) The input terminal is configured to receive the output of the third inverter (123) in the write voltage control circuit (2). Wherein, when the control signal (CTL) is a logic high level representing the write logic i, the discharge path provided by the discharge path (3) can be used to discharge the charge stored at the high voltage node (VH). a predetermined time, which is equal to the delay time provided by the delay circuit (D33) plus the fall propagation delay time of the third inverter (Κ3), it is worth noting that The delay circuit (D33) is connected in series by an even number of inverters. Therefore, the delay time provided by the delay circuit (D33) can be adjusted by changing the number of the even number of inverters, so when the control signal (CTL) is a logic high level on behalf of write logic 1, and the voltage path of the high voltage node (VH) can be easily passed from the high power supply voltage (HVDD) by the discharge path provided by the discharge path. The level is discharged to a level slightly lower than the low power supply voltage (lvdd) and is turned on by the fourth PMOS transistor (P22) in the write voltage control circuit (2) to accurately The voltage level of the high voltage node (VH) is fixed at this low Voltage level of the supply voltage source (LVDD) provided by registration. Next, how the writing operation of the preferred embodiment of Fig. 6 is completed depends on the four writing states of the static random access memory cell. 9 M391711 (1) Node A originally stores the logic 〇, but now wants to write logic 〇: Before the write action occurs (word line WL is the ground voltage), the first NMOS transistor M1 is 0N (conducting) 'this high A power supply voltage (HVDD) is supplied to the voltage node (VH). Since the first NMOS transistor M1 is on', when the write operation starts, the word line (WL) is turned from the Low voltage (high power supply voltage, and the voltage of the node a follows the sub-line (WL). The voltage rises. When the voltage of the word line (wl) is greater than the threshold voltage of the third _8 transistor (M3) (ie, the access transistor), the third Lancome 8 transistor (M3) is turned OFF. (cutoff) is changed to 0N (conduction). At this time, since the bit line (BL) is the ground voltage, node A is discharged, and the logic 0 write operation is completed until the end of the write cycle. Yes, the voltage node (VH) has the level of the low power supply voltage (LVDD) at the beginning of writing and has the level of the high power supply voltage (HVdd) after the end of the writing period. Node A originally stores the logic 〇, and now wants to write logic 1: Before the write action occurs (word line WL is the ground voltage), the first NMOS transistor M1 is ON (on), and the high power supply voltage is supplied to The voltage node _. Since the first NMOS transistor M1 is ON, when the write operation starts, the word line (wl) is Low ( The ground voltage is turned to High (high power supply voltage HVDD), and the voltage of node A rises following the voltage of the word line (WL). When the voltage of the word line (WL) is greater than that of the third NMOS transistor (M3) When the threshold voltage and the threshold voltage of the fourth NMOS transistor (M31) in the discharge path (3) are changed, the third NMOS transistor (M3) is turned from OFF (turned off) to turned "on", at this time because of the bit element. The line (BL) is High (high power supply voltage HVDD), and since the first NMOS transistor M1 is still ON and the node B is still at an initial level of voltage level close to the voltage level of the high power supply voltage (HVDD) The discharge state, so the first pM〇s transistor pi is still OFF (cutoff), and the node A is quickly charged to the third NM〇s transistor (M3) conduction equivalent resistance (Rm3) and the first The NMOS transistor (Ml) turns on the equivalent voltage M391711 resistance (Rmi) shows the voltage dividing voltage level 'this voltage dividing voltage level is equal to the voltage level provided by the 13⁄4 power supply voltage (HV〇d), At this time, since the third NMOS transistor (M3) operates in a saturation region and the first NMOS transistor ( Ml) operates in a triode region, so the on-resistance equivalent (~) of the third NMOS transistor (M3) is much larger than the on-resistance equivalent (Rm!) of the first transistor (M1). Node A then assumes a low voltage division voltage level that is approximately equal to the .52 mV simulated by the conventional 5T SRAM cell of Figure 4 during a period of 25 nanoseconds to 30 nanoseconds. Then, the node B is gradually discharged to a lower voltage level, and the lower voltage level of the node B causes the on-resistance equivalent (r^) of the first NMOS transistor (M1) to exhibit a higher resistance value. A high resistance value will result in a higher voltage level at node A, and the higher voltage level of the node A will pass through the second inverter (composed of the second PMOS transistor P2 and the second NMOS transistor M2). And causing the node B to obtain a lower voltage level, and the lower voltage level of the node B is again caused by the first inverter (composed of the first PMOS transistor P1 and the first NMOS transistor M1) Node A obtains a higher voltage level, and accordingly, the node A can be charged to a high power supply voltage (HVDD) to deduct the threshold voltage of the third NMOS transistor (M3) or the low power supply voltage (LVdd). The larger of them, and the logic 1 write operation is completed. It is worth noting here that the voltage node (VH) has the low power supply voltage (lvdd) level at the beginning of writing, and has the high power supply voltage (HVDD) after the end of the writing period. The level, therefore, after the end of the write cycle 'the node A will be charged to the level of the high power supply voltage (hvdd). (3) Node A originally stored logic 1, but now wants to write logic! : Before the write action occurs (the word line WL is the ground voltage) 'The first pm 电S transistor P1 is ON (on), and the high power supply voltage (HVDD) is supplied to the voltage node (_. The line (WL) turns from Low (ground voltage) to High (high power supply voltage HVDD), and the voltage of the word line CWL) is greater than the threshold voltage of the third NMOS transistor (M3), the 11th M391711 three nmos transistor (10)) is changed to 〇N (conducting); after the low supply voltage (lvdd) is supplied to the wire node (Vdd), the phase is the bit line (bl) β,

High (high power supply voltage hvdd), and because the _pM〇s transistor decays ^

The voltage at point A of (4) will decrease the high-voltage voltage (5) minus the threshold voltage of the first NMOS transistor (M3) or the lower power supply voltage (lVdd). Write the person's weekly reduction of the high-ply wire to take (10)) wire to the voltage node (VH) ° * (d) 卽 point A originally stored logic 1, and now want to write logic 〇: before the write action occurs (word The source line WL is the ground voltage), and the -pMGS transistor P1 is ON (on). The high power supply voltage is supplied to the voltage node (γΗ^ when the word line (WL) is turned from the Low (ground voltage) to the milk (high) When the power supply voltage is applied, and the voltage of the NMOS line (WL) is greater than the threshold voltage of the third nmos transistor (M3), the third NMOS transistor (M3) is changed from OFF (off) to 〇N (on), Since the bit line (BL) is Low (ground voltage), the node is discharged to complete the logic write operation until the end of the write cycle. It is worth noting that the voltage node (_ write In the initial stage, the low power supply voltage (LVdd) is used, and after the end of the write cycle, the high power supply voltage (hvdd) is used. The preferred embodiment of the present invention shown in FIG. 6 shows the results of the HSpICE transient analysis simulation during the write operation, as shown in FIG. 7 'which is simulated by the ievei 49 model and using TSMC 0.35 micron CMOS process parameters ( The zero-substrate bias voltage value Vth〇 of the PMOS transistor and the νμο^ transistor is -0.7866083V and 0.582913V, respectively, wherein the PMOS transistors PI and P2 have the channel width-to-length ratio, and the NMOS transistor M1 The channel width to length ratio of M2 and M2 are both (ΐ>=(2μπι/0.35μπι), and the channel width to length ratio of NMOS transistor M3 is (w/L)=(1.3pm/0.35pm) by the simulation. As a result, it can be noted that the static random access memory with a discharge path proposed by the present invention can reduce the power supply voltage by the writing operation, thereby effectively avoiding the conventional 5T static 12 random storage shown in FIG. It is quite difficult to write the memory cell 1 to write logic 1. Lushanshan cold + creation of the static random access memory with the discharge path, even if it is operated with t = memory capacity and / or When the static random access memory of the operation is high, the circuit can still be provided by the present creation = (3) To effectively improve the reliability and stability of the write operation. [Simplified description of the drawing] Fig. 1 is a schematic circuit diagram showing a conventional 6T static random access memory cell; Fig. 2 shows a conventional 6Τ Static random access memory cell cell write action timing diagram; Figure 3 shows the circuit diagram of the conventional 5Τ static random access memory cell; 4th figure _ shows the 5 Τ 纽 纽 取 memory Figure 7 shows the circuit diagram of the human cell action; Figure 5 shows the circuit diagram of the 5 Τ static random access memory cell of the TW Μ 3 〇 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Schematic diagram of the SRAM static random access memory; Fig. 7 shows the write operation timing diagram of the preferred embodiment of the sixth drawing [main component symbol description]

P2 M2 M4 BLB Ρ1 first PMOS transistor

Ml first NMOS transistor M3 third NMOS transistor BL bit line WL word line A storage node HV〇d still power supply voltage 1 SRAM cell discharge path second PMOS transistor second NMOS transistor fourth NMOS Crystal Complementary Bit Line VH High Voltage Node B Inverting Storage Node lvdd Low Power Supply Voltage 2 Write Electric Control Circuit CTL Control Signal 13 3 M391711 P21 Third PMOS Transistor P22 Fourth PMOS Transistor M31 Fourth NMOS Transistor M32 fifth NMOS transistor D33 delay circuit 123 third inverter

Claims (1)

M391711 VI. Patent Application Range: 1. A 單埠SRAM with a discharge path, comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells. The body cell and each row of memory cells each include a plurality of memory cells (1); a plurality of sub-member lines, each word line corresponding to one of the plurality of columns of memory cells; a plurality of bit lines Each bit line corresponds to one of the plurality of rows of memory cells; a plurality of write voltage control circuits (2), each column of memory cells is provided with a write voltage control circuit; and a plurality of discharge paths ( 3), each column of memory cells is provided with a discharge path (3); wherein each memory cell (1) further comprises: a first inverter, which is composed of a first PMOS transistor (P1) and a An NM〇s transistor (jvq), the first inverter is connected between a high voltage node and a ground voltage; and a second inverter is connected by a second PM〇s transistor (P2) Composed of the second _〇!§ transistor_), the second inverter is connected Connected between the high voltage node (VfJ) and the ground voltage; a storage node (A) ' is formed by the output of the first inverter; an inverted storage node (B) is the second An output of the inverter is formed; and an access transistor (M3) is connected between the storage node (A) and a corresponding bit line, and the gate is connected to a corresponding word line (WL) The first inverter and the second inverter are in an inter-active connection, that is, the output end of the first inverter (ie, the storage node A) is connected to the second inverter. The input end, and the output end of the first inverter (ie, the inverting storage node B) is connected to the wheel-in end of the first inverter; wherein each of the write voltage control circuit (2) further comprises: - the third PMOS transistor (P21), the source, the close-pole and the immersion of the third PMOS transistor (4) are connected to the high-power electric (^hvdd), the control (CTL) blood ^ High voltage node (VH); a fourth PMOS transistor (P22), the source, the closed pole and the drain of the fourth PMOS transistor are respectively connected to a low power supply voltage (lVdd), a third reverse Phase device (123) a turn-out terminal and the high voltage node (VH); and a 15 M391711-third inverter (123), the input of the third inverter (123) is configured to receive the control signal (CTL), and the The output of the third inverter (123) is connected to the gate of the fourth pm S transistor (P22); wherein each discharge path (3) further comprises: a fourth NMOS transistor (M31) The source, gate and drain of the fourth NMOS transistor (M31) are respectively connected to the drain of a fifth NMOS transistor (M32), the control signal (CTL) and the high voltage node (VH) a fifth NMOS transistor (M32), the source, the gate and the immersion of the fifth NMOS transistor (M32) are respectively connected to a ground voltage, an output of a delay circuit (D33), and the fourth NMOS a source of the transistor (M31); and a delay circuit (D33) 'the input terminal of the delay circuit (D33) for receiving the third inverter (123) in the corresponding write voltage control circuit (2) The output of the delay circuit (£) 33) is connected to the gate of the fifth NMOS transistor (M32). 2. The 單埠SRAM having a discharge path as described in claim 1 wherein the control signal (CTL) is a write enable (WE) signal, a write data signal, and a corresponding word line. The AND gate operation result of the (WL) signal, that is, only when the write enable (^) signal, the write data signal, and the corresponding word line (WL) signal are both at a logic high level, The control signal (CTL) side is a logic high level; and when the corresponding control signal (CTL) is a logic low level representing a non-selected write state or a non-write logic 1, the high power supply voltage (HVDD) is supplied. To the high voltage node (VH). 3. The sraM having a discharge path as described in claim 2, wherein the logic high level of the corresponding word line (WL) is the level of the high power supply voltage (HVdd). 4. The single-turn SRAM having a discharge path according to claim 3, wherein the delay circuit (D33) in each of the discharge paths (3) is formed by connecting an even number of inverters. In order to provide a delay time. 5. A 單埠SRAM having a discharge path as described in claim 4, wherein when the control nickname (CTL) is a logic high level representing write logic 1, the corresponding discharge path can be utilized (3) The discharge path is provided to discharge the charge stored at the high voltage node for a predetermined time. 6. The 單埠SRAM having a discharge path as described in claim 5, wherein the predetermined time interval 16 M391711 is equal to the delay time provided by the delay circuit (D33) plus the third reverse phase The sum of the fall propagation delay time of the device (123). 17